JP2000133883A - Nitride semiconductor element - Google Patents
Nitride semiconductor elementInfo
- Publication number
- JP2000133883A JP2000133883A JP30061598A JP30061598A JP2000133883A JP 2000133883 A JP2000133883 A JP 2000133883A JP 30061598 A JP30061598 A JP 30061598A JP 30061598 A JP30061598 A JP 30061598A JP 2000133883 A JP2000133883 A JP 2000133883A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- nitride semiconductor
- barrier layer
- undoped
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Lasers (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は発光ダイオード素子、レ
ーザダイオード素子等の発光素子、太陽電池、光センサ
等の受光素子、あるいはトランジスタ、パワーデバイス
等の電子デバイスに用いられる窒化物半導体(InXA
lYGa1-X-YN、0≦X、0≦Y、X+Y≦1)よりなる素
子に関する。The present invention relates to a light emitting diode element, a light-emitting element such as a laser diode element, a solar cell, a light receiving element such as an optical sensor or transistor, a power device such as a nitride semiconductor (an In X used for electronic devices, A
1 Y Ga 1 -XYN , 0 ≦ X, 0 ≦ Y, X + Y ≦ 1).
【0002】[0002]
【従来の技術】窒化物半導体は高輝度青色LED、純緑
色LEDの材料として、フルカラーLEDディスプレ
イ、交通信号灯、イメージスキャナー光源等の各種光源
で実用化されている。これらのLED素子は基本的に、
サファイア基板上にGaNよりなるバッファ層と、Si
ドープGaNよりなるn側コンタクト層と、単一量子井
戸構造(SQW:Single-Quantum- Well)のInGa
N、あるいはInGaNを有する多重量子井戸構造(M
QW:Multi-Quantum-Well)の活性層と、MgドープA
lGaNよりなるp側クラッド層と、MgドープGaN
よりなるp側コンタクト層とが順に積層された構造を有
しており、20mAにおいて、発光波長450nmの青
色LEDで5mW、外部量子効率9.1%、520nm
の緑色LEDで3mW、外部量子効率6.3%と非常に
優れた特性を示す。多重量子井戸構造は、複数のミニバ
ンドからなる構造を有し、効率よく、小さな電流でも発
光が実現することから、単一量子井戸構造より発光出力
が高くなる等の素子特性の向上が期待される。2. Description of the Related Art Nitride semiconductors have been put into practical use as materials for high-brightness blue LEDs and pure green LEDs in various light sources such as full-color LED displays, traffic signal lights, and image scanner light sources. These LED elements are basically
A buffer layer of GaN on a sapphire substrate;
N-side contact layer made of doped GaN and InGa of a single quantum well structure (SQW: Single-Quantum-Well)
Multiple quantum well structure with N or InGaN (M
QW: Multi-Quantum-Well) active layer and Mg-doped A
a p-side cladding layer of lGaN and Mg-doped GaN
And a p-side contact layer composed of a blue LED with an emission wavelength of 450 nm at 5 mA and an external quantum efficiency of 9.1% and 520 nm at 20 mA.
3mW and an external quantum efficiency of 6.3%, which are very excellent characteristics. The multiple quantum well structure has a structure composed of a plurality of minibands, and can efficiently emit light even with a small current. Therefore, improvement in device characteristics such as higher light emission output than a single quantum well structure is expected. You.
【0003】例えば、本出願人は、特開平9−3643
0号公報に、発光出力の高い素子として、100オング
ストローム以下の井戸層と、150オングストローム以
下の障壁層とからなる多重量子井戸構造の活性層を有す
る窒化物半導体発光素子を開示している。このように素
子の活性層が量子井戸構造であると、歪み量子井戸効
果、エキシントン発光効果等により高出力となる。[0003] For example, the present applicant has disclosed in Japanese Patent Application Laid-Open No. 9-3643.
No. 0 discloses a nitride semiconductor light emitting device having a multiple quantum well structure active layer including a well layer of 100 Å or less and a barrier layer of 150 Å or less as a device having a high light output. When the active layer of the device has a quantum well structure as described above, a high output is obtained due to a strained quantum well effect, an Exxington light emission effect, and the like.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、上記本
出願人が開示したLED素子は、高出力であり実用に十
分適用でき信号などの種々の製品に適用されているもの
の、近年の省エネなどの要求に応じて、低消費電力でも
発光出力の低下を伴わないように光電変換効率のさらな
る向上が望まれる。このような、低消費電力で良好な発
光出力が得られれば、素子の寿命特性をより向上させる
こともできる。そこで、本発明の目的は、発光出力を低
下させることなく、光電変換効率を高めることができる
窒化物半導体発光素子を提供することである。However, the LED element disclosed by the present applicant has a high output, is sufficiently applicable to practical use, and is applied to various products such as signals. Accordingly, it is desired to further improve the photoelectric conversion efficiency so that the light emission output does not decrease even with low power consumption. If such a good light emission output can be obtained with low power consumption, the life characteristics of the element can be further improved. Therefore, an object of the present invention is to provide a nitride semiconductor light emitting device that can increase photoelectric conversion efficiency without lowering light emission output.
【0005】[0005]
【課題を解決するための手段】即ち、本発明は、下記
(1)〜(4)の構成により本発明の目的を達成するこ
とができる。 (1) n型窒化物半導体層と、p型窒化物半導体層と
の間に、Inを含む窒化物半導体よりなる井戸層と、井
戸層と組成の異なる窒化物半導体よりなる障壁層とが積
層されてなる多重量子井戸構造の活性層を有し、前記井
戸層がアンドープであり、前記障壁層の単一膜厚が70
〜500オングストロームを有し更に障壁層にn型不純
物が5×1016〜1×1019/cm3ドープされている
ことを特徴とする窒化物半導体素子。 (2) 前記活性層が、アンドープ窒化物半導体層上に
成長されてなることを特徴とする前記(1)に記載の窒
化物半導体素子。 (3) 前記アンドープ窒化物半導体層が、10〜50
0オングストロームの膜厚を有することを特徴とする前
記(2)に記載の窒化物半導体素子。 (4) 前記アンドープ窒化物半導体層が、アンドープ
GaNからなることを特徴とする前記(2)又は(3)
に記載の窒化物半導体素子。That is, the present invention can achieve the object of the present invention by the following constitutions (1) to (4). (1) A well layer made of a nitride semiconductor containing In and a barrier layer made of a nitride semiconductor having a composition different from that of the well layer are stacked between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer. An active layer having a multiple quantum well structure, wherein the well layer is undoped, and the barrier layer has a single thickness of 70 nm.
A nitride semiconductor device having a thickness of up to 500 angstroms and a barrier layer doped with an n-type impurity at a concentration of 5 × 10 16 to 1 × 10 19 / cm 3 . (2) The nitride semiconductor device according to (1), wherein the active layer is grown on an undoped nitride semiconductor layer. (3) The undoped nitride semiconductor layer has a thickness of 10 to 50.
The nitride semiconductor device according to the above (2), which has a thickness of 0 Å. (4) The above (2) or (3), wherein the undoped nitride semiconductor layer is made of undoped GaN.
3. The nitride semiconductor device according to item 1.
【0006】つまり、本発明は、多重量子井戸構造の障
壁層を特定の膜厚、つまり従来のものに比べて厚膜に
し、この障壁層にn型不純物を特定の濃度で含有させ、
更に、井戸層をアンドープとすることにより、低い順方
向電圧(Vf)と少リーク電流を可能とし、発光出力を
低下させることなく光電変換効率を向上させることがで
きる窒化物半導体素子を提供することができる。That is, according to the present invention, a barrier layer having a multiple quantum well structure is made to have a specific thickness, that is, a thicker film than a conventional one, and this barrier layer contains an n-type impurity at a specific concentration.
Further, by providing an undoped well layer, it is possible to provide a nitride semiconductor device which enables a low forward voltage (Vf) and a small leak current, and can improve photoelectric conversion efficiency without lowering light emission output. Can be.
【0007】前記した特開平9−36430号公報に
は、活性層にn型不純物を添加してもよいことが記載さ
れているが、障壁層の膜厚とn型不純物の添加濃度につ
いては何ら記載されていない。また、特開平10−65
271号公報には、障壁層のみにSi、Cd、Zn、M
gなどの不純物をドープすることが記載され、実施例に
膜厚30オングストロームの障壁層が具体的に記載され
ているが、このような膜厚では光電変換効率を十分満足
できる程度に向上させ難い。また更に、特開平10−1
35514号公報には、障壁層に不純物を含有させても
よいことが記載されているが、障壁層の膜厚を30〜5
0オングストロームとしているので上記公報と同様に光
電変換効率を十分満足できる程度に向上させにくい。Japanese Patent Application Laid-Open No. 9-36430 describes that an n-type impurity may be added to the active layer. However, the thickness of the barrier layer and the concentration of the n-type impurity are not limited. Not listed. Also, Japanese Patent Application Laid-Open No. 10-65
No. 271 discloses that Si, Cd, Zn, M
Doping with an impurity such as g is described, and a barrier layer having a thickness of 30 Å is specifically described in the examples. However, it is difficult to improve the photoelectric conversion efficiency to a sufficiently satisfactory level with such a thickness. . Furthermore, Japanese Patent Application Laid-Open No. 10-1
Japanese Patent No. 35514 discloses that impurities may be contained in the barrier layer.
Since the thickness is set to 0 angstroms, it is difficult to improve the photoelectric conversion efficiency to a sufficiently satisfactory level as in the above publication.
【0008】これに対して、本発明者は、光電変換効率
を向上させるべく、種々検討した結果、多重量子井戸構
造の活性層の障壁層の膜厚を厚膜にすることにより、解
決できることを見出した。しかし、障壁層の膜厚を厚膜
とすると、順方向電圧(Vf)が高くなる傾向があり、
単に障壁層を厚膜にしただけでは低消費電力で高光電変
換効率を達成しにくい。このVf上昇といった問題点に
対し、種々検討した結果、厚膜にした障壁層にn型不純
物を添加することによりVfを低下させることができる
が、n型不純物の添加量が高いとかえって光電変換効率
が低下するばかりか、I−V特性においてリーク電流が
増加する傾向があることがわっかた。このように、障壁
層を厚膜として光電変換効率を向上させるとVfが上昇
し、Vfを低下させるためにn型不純物を添加するとリ
ーク電流が増加するといったように、これらの特性全て
において満足できない。このような問題点に対し、本発
明は、上記構成、つまり障壁層の膜厚と障壁層に添加す
るn型不純物の濃度との関係を詳細に検討し、この結
果、障壁層を特定の膜厚及び特定の濃度のn型不純物を
添加し、且つ井戸層をアンドープとし、このアンドープ
井戸層と前記障壁層とを組み合わせることにより、低V
f及び少リーク電流で光電変換効率を向上させることが
できるため、低消費電力でさえも良好な発光出力を得る
ことができる。On the other hand, the present inventor has made various studies to improve the photoelectric conversion efficiency. As a result, the present inventors have found that the problem can be solved by increasing the thickness of the barrier layer of the active layer of the multiple quantum well structure. I found it. However, when the thickness of the barrier layer is large, the forward voltage (Vf) tends to increase,
Simply increasing the thickness of the barrier layer makes it difficult to achieve high photoelectric conversion efficiency with low power consumption. As a result of various studies on the problem of the increase in Vf, Vf can be reduced by adding an n-type impurity to a thick barrier layer. It has been found that not only does the efficiency drop, but the leak current tends to increase in the IV characteristics. As described above, when the photoelectric conversion efficiency is improved by using the barrier layer as a thick film, Vf increases, and when an n-type impurity is added to lower Vf, the leak current increases, and all these characteristics cannot be satisfied. . In order to solve such a problem, the present invention examines in detail the above configuration, that is, the relationship between the thickness of the barrier layer and the concentration of the n-type impurity added to the barrier layer. By adding a thick and specific concentration of n-type impurity and undoping the well layer and combining the undoped well layer and the barrier layer, a low V
Since the photoelectric conversion efficiency can be improved with f and a small leak current, a good light emission output can be obtained even with low power consumption.
【0009】更に本発明は、多重量子井戸構造の活性層
が、アンドープ窒化物半導体層上に、好ましくは膜厚1
0〜500オングストロームのアンドープ窒化物半導体
層上に、より好ましくはアンドープGaN層上に、積層
成長されると、活性層の結晶性がより良好となり、光電
変換効率の向上及び低Vfとするのに好ましい。Further, according to the present invention, an active layer having a multiple quantum well structure is provided on an undoped nitride semiconductor layer, preferably with a thickness of 1 nm.
When the active layer is grown and grown on an undoped nitride semiconductor layer having a thickness of 0 to 500 angstroms, and more preferably on an undoped GaN layer, the crystallinity of the active layer becomes better, so that the photoelectric conversion efficiency can be improved and the Vf can be reduced. preferable.
【0010】[0010]
【発明の実施の形態】本発明において、活性層は、井戸
層と障壁層とを順次積層した多層膜構造の多重量子井戸
構造である。多重量子井戸構造の最小積層構造は、1つ
の障壁層とこの障壁層の両側に設けられた(2つの)井
戸層とからなる3層構造または1つの井戸層とその両側
に設けられた(2つの)障壁層とからなる3層構造であ
り得る。多重量子井戸構造において、両側の2つの最外
層は、それぞれ井戸層または障壁層により構成される。
また、一方の最外層が井戸層で他方の最外層が障壁層と
なるように構成されてもよい。また、多重量子井戸構造
は、p側の窒化物半導体層に接近した側が障壁層で終わ
っても井戸層で終わっても良い。DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, the active layer has a multi-quantum well structure having a multilayer structure in which a well layer and a barrier layer are sequentially stacked. The minimum stacked structure of the multiple quantum well structure is a three-layer structure including one barrier layer and (two) well layers provided on both sides of the barrier layer, or one well layer and two well layers (2 And three barrier layers. In the multiple quantum well structure, the two outermost layers on both sides are each formed of a well layer or a barrier layer.
Further, one outermost layer may be configured as a well layer and the other outermost layer may be configured as a barrier layer. In the multiple quantum well structure, the side close to the p-side nitride semiconductor layer may end with the barrier layer or the well layer.
【0011】このような多重量子井戸構造の活性層にお
いて、井戸層及び障壁層は、両者をインジウムとガリウ
ムとを含む窒化物半導体(好ましくはInGaN)で形
成することができる(ただし、両者の組成は異なる)
が、井戸層をインジウムとガリウムを含む窒化物半導体
(好ましくは、InGaN)で形成し、障壁層を他の窒
化物半導体で、例えばInNやGaNで形成することも
できる。例えば、多重量子井戸構造よりなる活性層の井
戸層は少なくともInを含む窒化物半導体、好ましくは
InXGa1-XN(0<X<1)とする。一方、障壁層
は、井戸層よりもバンドギャップエネルギーが大きい窒
化物半導体を選択し、好ましくはInYGa1-YN(0≦
Y<1、X>Y)又はAlZGa1-ZN(0<Z<0.5)と
する。但し井戸層及び障壁層をInAlNとすることも
可能である。In such an active layer having a multiple quantum well structure, both the well layer and the barrier layer can be formed of a nitride semiconductor containing indium and gallium (preferably, InGaN) (however, the composition of both). Is different)
However, the well layer may be formed of a nitride semiconductor containing indium and gallium (preferably, InGaN), and the barrier layer may be formed of another nitride semiconductor, for example, InN or GaN. For example, the well layer of the active layer having the multiple quantum well structure is a nitride semiconductor containing at least In, preferably In x Ga 1 -xN (0 <X <1). On the other hand, for the barrier layer, a nitride semiconductor having a band gap energy larger than that of the well layer is selected, and preferably, In Y Ga 1-Y N (0 ≦
Y <1, X> Y) or Al Z Ga 1-Z N ( 0 to <Z <0.5). However, the well layer and the barrier layer can be made of InAlN.
【0012】本発明において、活性層の総膜厚は、特に
限定されないが、井戸層と障壁層の積層された層の合計
の膜厚であり、例えば具体的には500〜5000オン
グストロームであり、好ましくは1000〜3000オ
ングストロームである。活性層の総膜厚が上記範囲であ
ると発光出力及び活性層の結晶成長に要する時間の点で
好ましい。活性層の多重量子井戸構造を構成する障壁層
の単一膜厚は、70〜500オングストロームであり、
好ましくは100〜300オングストロームである。障
壁層の単一膜厚が上記範囲であると、光電変換効率が向
上し、低Vf及び少リーク電流となり好ましい。また活
性層の井戸層の単一膜厚は、100オングストローム以
下、好ましくは70オングストローム以下、より好まし
くは50オングストローム以下である。井戸層の単一膜
厚の下限は、特に限定されないが、10オングストロー
ム以上であることが好ましい。井戸層の単一膜厚が上記
範囲であると、発光出力及び発光スペクトル半値幅の点
で好ましい。In the present invention, the total thickness of the active layer is not particularly limited, but is the total thickness of the stacked layers of the well layer and the barrier layer, for example, specifically, 500 to 5000 Å. Preferably it is 1000-3000 angstroms. When the total thickness of the active layer is within the above range, it is preferable in terms of the light emission output and the time required for crystal growth of the active layer. The single thickness of the barrier layer constituting the multiple quantum well structure of the active layer is 70 to 500 Å,
Preferably it is 100 to 300 angstroms. When the single thickness of the barrier layer is in the above range, the photoelectric conversion efficiency is improved, and the Vf and the leakage current are preferably low. The single thickness of the well layer of the active layer is 100 Å or less, preferably 70 Å or less, more preferably 50 Å or less. The lower limit of the single thickness of the well layer is not particularly limited, but is preferably 10 Å or more. When the single thickness of the well layer is within the above range, it is preferable in terms of emission output and emission spectrum half width.
【0013】本発明において、活性層の井戸層はアンド
ープ(意図的に不純物をドープしない状態)であり、障
壁層にのみn型不純物がドープされる。障壁層にドープ
するn型不純物にはSi、Ge、Sn、S、O、Ti、
Zr等のIV族、若しくはVI族元素を用いることができ、
好ましくはSi、Ge、Snを用いる。障壁層へのn型
不純物のドープ量は5×1016/cm3〜1×1019/c
m3、好ましくは5×1016/cm3〜1×1018/cm3、さ
らに好ましくは5×1016/cm3〜3×1017/cm3の範
囲に調整する。n型不純物のドープ量が、上記範囲であ
ると、光電変換効率を低下させず、I−V特性において
リーク電流の増加が見られず、Vfを低下でき好まし
い。In the present invention, the well layer of the active layer is undoped (in a state where impurities are not intentionally doped), and only the barrier layer is doped with n-type impurities. The n-type impurities to be doped into the barrier layer include Si, Ge, Sn, S, O, Ti,
A group IV or group VI element such as Zr can be used,
Preferably, Si, Ge, and Sn are used. The doping amount of the n-type impurity into the barrier layer is 5 × 10 16 / cm 3 to 1 × 10 19 / c
m 3 , preferably 5 × 10 16 / cm 3 to 1 × 10 18 / cm 3 , more preferably 5 × 10 16 / cm 3 to 3 × 10 17 / cm 3 . When the doping amount of the n-type impurity is within the above range, the photoelectric conversion efficiency is not reduced, and the leakage current is not increased in the IV characteristics, and Vf is preferably reduced.
【0014】以下に、多重量子井戸構造の活性層の障壁
層の単一膜厚と、この障壁層へのn型不純物のドープ量
の値について更に詳細に説明する。但し、図2及び図3
は、活性層の障壁層として、後述の実施例1の単一膜厚
300オングストローム、Siを9×1016/cm3ド
ープしてなる障壁層を有する活性層を用いた場合のデー
タである。Hereinafter, the single film thickness of the barrier layer of the active layer having the multiple quantum well structure and the value of the doping amount of the n-type impurity into the barrier layer will be described in more detail. However, FIGS. 2 and 3
The data are obtained when an active layer having a single thickness of 300 Å and a barrier layer doped with 9 × 10 16 / cm 3 of Si of Example 1 described later is used as a barrier layer of the active layer.
【0015】障壁層へドープする不純物濃度は、図2
(a)に示したように、印加電圧−5Vにおいて、低濃
度の場合はリーク電流の上昇率は小さいものの、1×1
019/cm3を超えるとリーク電流の上昇率が大きくな
る傾向がある。一方、図2(b)に示すように、不純物
濃度を徐々に低下させていくと、ドープ量に反比例して
順方向電圧が上昇するが、不純物のドープ量が5×10
16/cm3以上となると順方向電圧の上昇が大きくなる
傾向がある。また、障壁層の単一膜厚は、図3(a)に
示すように、厚くなればなるほど順方向電圧が比例して
上昇する傾向があるが、窒化物半導体素子の耐久性及び
規格等の点から、順方向電圧は3.8V以下であること
が好ましい。このことから、障壁層の単一膜厚の上限を
500オングストローム以下とする。また図3(b)に
示すように、薄膜の場合は発光出力が小さく、単一膜厚
を70オングストロームまで徐々に厚くすると、発光出
力は急な上昇を有して高くなるが、70オングストロー
ム以上とすると、発光出力の上昇が緩やかとなる傾向が
ある。このことから、障壁層の単一膜厚の膜厚の下限を
70オングストローム以上とする。The impurity concentration doped into the barrier layer is shown in FIG.
As shown in (a), at an applied voltage of -5 V, the rate of increase of the leak current is small when the concentration is low, but 1 × 1
If it exceeds 0 19 / cm 3 , the rate of increase in leak current tends to increase. On the other hand, as shown in FIG. 2B, as the impurity concentration is gradually decreased, the forward voltage increases in inverse proportion to the doping amount, but the impurity doping amount is 5 × 10
When it is 16 / cm 3 or more, the increase in the forward voltage tends to increase. Further, as shown in FIG. 3A, as the single thickness of the barrier layer increases, the forward voltage tends to increase in proportion to the increase in the thickness, but the durability and the standard of the nitride semiconductor element are not so high. From the viewpoint, the forward voltage is preferably 3.8 V or less. For this reason, the upper limit of the single thickness of the barrier layer is set to 500 Å or less. As shown in FIG. 3 (b), in the case of a thin film, the luminous output is small, and when the single film thickness is gradually increased to 70 Å, the luminous output rises with a sharp rise, but is increased to 70 Å or more. Then, the light emission output tends to increase slowly. For this reason, the lower limit of the single thickness of the barrier layer is set to 70 Å or more.
【0016】以上ことから、光電変換効率を高めるため
に障壁層の単一膜厚を厚くすることにより引き起こされ
る種々の問題点を、光電変換効率の向上と同時に解決す
るために種々検討の結果、障壁層の単一膜厚を70〜5
00オングストロームとし、障壁層への不純物のドープ
量を5×1016/cm3〜1×1019/cm3とすること
により障壁層を厚膜にしたことにより生じる諸問題の解
決及び光電変換効率の向上を良好にすることができる。From the above, as a result of various investigations to solve various problems caused by increasing the single film thickness of the barrier layer in order to increase the photoelectric conversion efficiency and simultaneously improve the photoelectric conversion efficiency, The single thickness of the barrier layer is 70 to 5
The solution of various problems and the photoelectric conversion efficiency caused by making the barrier layer thick by setting the thickness of the barrier layer to 5 × 10 16 / cm 3 to 1 × 10 19 / cm 3 by setting the barrier layer to an impurity doping of 5 × 10 16 / cm 3 to 1 × 10 19 / cm 3 Can be improved.
【0017】本発明において、活性層を成長させる直前
に形成させるアンドープ窒化物半導体層とは、意図的に
不純物をドープしないで形成した層を示し、隣接する層
からの不純物の拡散、原料又は装置からのコンタミネー
ションにより不純物が混入した層であっても、意図的に
不純物をドープしていない場合にはアンドープ層とす
る。このようなアンドープ窒化物半導体層を形成した上
に、活性層を成長させると、活性層の結晶性が向上し、
光電変換効率及び発光スペクトル半値幅がより良好とな
る。In the present invention, the undoped nitride semiconductor layer formed immediately before the growth of the active layer refers to a layer formed without intentionally doping impurities, the diffusion of impurities from an adjacent layer, a material or a device. Even if a layer is mixed with an impurity due to contamination from the substrate, if the impurity is not intentionally doped, the layer is an undoped layer. When an active layer is grown after forming such an undoped nitride semiconductor layer, the crystallinity of the active layer is improved,
The photoelectric conversion efficiency and the half width of the emission spectrum become better.
【0018】本発明において、上記アンドープ窒化物半
導体層は、上記活性層に比較してバンドギャップエネル
ギーの大きい、アンドープGaN、一般式InaGa1-a
N(0<a<0.5、好ましくはa<0.2)で表され
るアンドープInGaN、一般式AlbGa1-bN(0<
b<1、好ましくはb<0.2)で表せるアンドープA
lGaNのうちいずれか1つからなることが好ましい。
また、一般式InXAlYGa1-X-YN(0<X、0<
Y、X+Y<1)を用いて構成してもよい。なお、アン
ドープ窒化物半導体層としてアンドープInGaNを用
いる場合、該アンドープInGaNにおいてGaに対す
るInの比率を上記井戸層に比較して小さく設定する。
上記アンドープ窒化物半導体層の膜厚は10〜500オ
ングストローム、好ましくは10〜300オングストロ
ーム、より好ましくは20〜100オングストロームで
ある。膜厚が上記範囲であると、光電変換効率、及び発
光出力の点で好ましい。In the present invention, the undoped nitride semiconductor layer has a larger band gap energy than that of the active layer, and has undoped GaN and a general formula In a Ga 1 -a.
Undoped InGaN represented by N (0 <a <0.5, preferably a <0.2), and a general formula Al b Ga 1-b N (0 <
undoped A represented by b <1, preferably b <0.2)
Preferably, it is made of any one of lGaN.
In addition, the general formula In x Al Y Ga 1 -XYN (0 <X, 0 <
Y, X + Y <1). When undoped InGaN is used as the undoped nitride semiconductor layer, the ratio of In to Ga in the undoped InGaN is set to be smaller than that in the well layer.
The thickness of the undoped nitride semiconductor layer is 10 to 500 Å, preferably 10 to 300 Å, more preferably 20 to 100 Å. It is preferable that the film thickness is in the above range in terms of photoelectric conversion efficiency and light emission output.
【0019】本発明において、n型及びp型窒化物半導
体層としては特に限定されず、種々の窒化物半導体層を
組み合わせて用いることができる。また、前記活性層の
直前に形成されるアンドープ窒化物半導体層の他に、同
一組成又は異なる組成の種々のアンドープの窒化物半導
体を窒化物半導体素子のいずれかの部分に用いてもよ
い。例えば、サファイアなどの異種基板上に200〜9
00℃でGaNよりなるバッファ層を成長させるとバッ
ファ層の上に高温(900℃程度より高い温度)で成長
させる窒化物半導体の結晶性が良好となり好ましい。ま
た活性層の上層に、MgをドープさせたAlGaN等の
層を形成すると発光出力の点で好ましい。このように種
々の窒化物半導体層を組み合わせて素子を構成すること
ができる。窒化物半導体素子の具体例としては、後述の
実施例に示したLED素子を構成する窒化物半導体を用
いることができる。また電極としては、種々のオーミッ
ク接触を有する電極を適宜選択して用いることができ
る。In the present invention, the n-type and p-type nitride semiconductor layers are not particularly limited, and various types of nitride semiconductor layers can be used in combination. Further, in addition to the undoped nitride semiconductor layer formed immediately before the active layer, various undoped nitride semiconductors having the same composition or different compositions may be used in any part of the nitride semiconductor device. For example, 200 to 9 on a heterogeneous substrate such as sapphire.
It is preferable to grow a buffer layer made of GaN at 00 ° C. because the nitride semiconductor grown on the buffer layer at a high temperature (higher than about 900 ° C.) has good crystallinity. It is preferable to form a layer of Mg-doped AlGaN or the like on the active layer in terms of light emission output. Thus, an element can be formed by combining various nitride semiconductor layers. As a specific example of the nitride semiconductor element, a nitride semiconductor constituting an LED element described in an example described later can be used. Further, as the electrodes, electrodes having various ohmic contacts can be appropriately selected and used.
【0020】また、前記多重量子井戸構造の活性層を成
長させる直前に成長させるアンドープ窒化物半導体層
は、単一井戸構造の活性層を成長させる直前に成長させ
ると多重量子井戸構造の活性層の直前に成長させる場合
と同様に光電変換効率を向上させることができる。The undoped nitride semiconductor layer grown just before the growth of the active layer having the multiple quantum well structure is grown just before the growth of the active layer having the single quantum well structure. The photoelectric conversion efficiency can be improved as in the case of immediately preceding growth.
【0021】[0021]
【実施例】以下に本発明の一実施の形態である実施例を
示すが、本発明はこれに限定されない。 [実施例1]実施例1は、図1に示される発光ダイオー
ド(LED)を作成する。サファイア基板1のC面上
に、300オングストロームの厚さのGaNバッファ層
2を550℃で成長させ、GaNバッファ層2上に0.
7μmの厚さのアンドープGaN層3を1050℃で成
長させる。次に同一温度で、Siがドープされたn型G
aN層4を3.3μmの厚さに成長させる。EXAMPLES Examples which are embodiments of the present invention will be shown below, but the present invention is not limited to these. Embodiment 1 In Embodiment 1, a light emitting diode (LED) shown in FIG. 1 is formed. A GaN buffer layer 2 having a thickness of 300 Å is grown at 550 ° C. on the C-plane of the sapphire substrate 1.
An undoped GaN layer 3 having a thickness of 7 μm is grown at 1050 ° C. Next, at the same temperature, the Si-doped n-type G
The aN layer 4 is grown to a thickness of 3.3 μm.
【0022】そして、活性層を成長させる前に、105
0℃で、アンドープGaN層5を400オングストロー
ムの厚さに成長させる。Then, before growing the active layer, 105
At 0 ° C., an undoped GaN layer 5 is grown to a thickness of 400 Å.
【0023】次に、Siが9×1016/cm3ドープさ
れたGaNよりなる障壁層を300オングストロームの
膜厚で成長させ、続いて温度を800℃にして、TM
G、TMI、アンモニアを用いアンドープIn0.3Ga
0.6Nよりなる井戸層を30オングストロームの膜厚で
成長させる。そして障壁+井戸+障壁+井戸・・・・+
障壁の順で障壁層を6層、井戸層を5層、交互に積層し
て、総膜厚1950オングストロームの多重量子井戸構
造よりなる活性層7を成長させる。Next, a barrier layer made of GaN doped with 9 × 10 16 / cm 3 of Si is grown to a thickness of 300 angstroms.
Undoped In 0.3 Ga using G, TMI and ammonia
A 0.6 N well layer is grown to a thickness of 30 Å. And barrier + well + barrier + well ... +
The active layer 7 having a multiple quantum well structure having a total thickness of 1950 angstroms is grown by alternately stacking six barrier layers and five well layers in the order of the barriers.
【0024】次に、Mgがドープされた300オングス
トロームの厚さのp型Al0.2Ga0 .8Nからなるp型A
lGaN層7を成長させ、さらにMgがドープされた
0.2μmの厚さのp型GaN層8を成長させる。Next, Mg is made of p-type Al 0.2 Ga 0 .8 N having a thickness of 300 angstroms doped p-type A
An lGaN layer 7 is grown, and a Mg-doped p-type GaN layer 8 having a thickness of 0.2 μm is grown.
【0025】反応終了後、温度を室温まで下げ、さらに
窒素雰囲気中、ウェーハを反応容器内において、700
℃でアニーリングを行い、p型層を低抵抗化する。After completion of the reaction, the temperature is lowered to room temperature, and the wafer is placed in a reaction vessel in a nitrogen atmosphere.
Anneal at ℃ to reduce the resistance of the p-type layer.
【0026】アニーリング後、ウェーハを反応容器から
取り出し、最上層のp側GaN層8の表面に所定の形状
のマスクを形成し、RIE(反応性イオンエッチング)
装置で、積層されたp型GaN層8、p型AlGaN層
7、活性層6及びアンドープGaN層5をエッチングに
より部分的に除去して、n電極を形成するためn型Ga
N層4の表面を露出させる。After annealing, the wafer is taken out of the reaction vessel, a mask of a predetermined shape is formed on the surface of the uppermost p-side GaN layer 8, and RIE (reactive ion etching) is performed.
In the apparatus, the stacked p-type GaN layer 8, p-type AlGaN layer 7, active layer 6, and undoped GaN layer 5 are partially removed by etching to form an n-type Ga for forming an n-electrode.
The surface of the N layer 4 is exposed.
【0027】次に、p型GaN層8の上にNi/Auか
らなるp電極を形成し、n型GaN層4上に露出させた
表面にTi/Alからなるn電極11を形成してLED
素子を作製する。Next, a p-electrode made of Ni / Au is formed on the p-type GaN layer 8, and an n-electrode 11 made of Ti / Al is formed on the surface exposed on the n-type GaN layer 4, thereby forming an LED.
A device is manufactured.
【0028】このLED素子は順方向電流20mAにお
いて、470nmの青色発光を示し、Vfは3.5V
で、発光出力は6.5mWであり、従来の多重量子井戸
構造のLED素子に比較して、Vfで0.3V近く低下
し、出力は1.5倍以上に向上した。なお、従来の多重
量子井戸構造のLED素子としては、上記実施例1にお
いて活性層を構成する障壁層をアンドープの20オング
ストロームの膜厚に変更する他は同様にしてLEDを作
製した。上記のように本発明の素子は、比較の素子と比
べ、同一の順方向電流値で発光出力が上昇し、光電変換
効率が向上でき、このことから低消費電力化が可能とな
る。This LED device emits blue light of 470 nm at a forward current of 20 mA, and Vf is 3.5 V
The light emission output was 6.5 mW, and the Vf was reduced by nearly 0.3 V at Vf, and the output was improved by 1.5 times or more, as compared with the conventional multiple quantum well structure LED element. As a conventional LED element having a multiple quantum well structure, an LED was fabricated in the same manner as in Example 1 except that the barrier layer constituting the active layer was changed to an undoped film thickness of 20 angstroms. As described above, in the device of the present invention, the light emission output is increased at the same forward current value as compared with the comparative device, and the photoelectric conversion efficiency can be improved. As a result, power consumption can be reduced.
【0029】[実施例2]実施例1において、活性層を
成長させる直前に成長させたアンドープGaN層5を形
成しない他は同様にしてLED素子を作製する。得られ
たLED素子は、実施例1に比べるとやや光電変換効率
が低下し発光スペクトル半値幅がやや広くなるものの、
ほぼ同様の良好な特性を有する。[Example 2] An LED element is manufactured in the same manner as in Example 1, except that the undoped GaN layer 5 grown immediately before growing the active layer is not formed. Although the obtained LED element has a slightly lower photoelectric conversion efficiency and a slightly wider half-width of the emission spectrum as compared with Example 1,
It has almost the same good characteristics.
【0030】[比較例1]実施例1において、井戸層に
Siを2×1019/cm3ドープした他は同様にしてL
ED素子を作製する。得られたLED素子は、印加電圧
−5Vで、リーク電流800mA、発光出力0.5mW
といった特性を示し、良好な結果が得られなかった。[Comparative Example 1] In the same manner as in Example 1, except that the well layer was doped with 2 × 10 19 / cm 3 of Si,
An ED element is manufactured. The obtained LED element had an applied voltage of -5 V, a leakage current of 800 mA, and a light emission output of 0.5 mW.
, And good results could not be obtained.
【0031】[0031]
【発明の効果】本発明は、多重量子井戸構造の活性層の
井戸層をアンドープとし、更に障壁層の膜厚及び不純物
濃度を規定することにより、従来の問題点を解決し、低
消費電力でも良好な発光出力を有する光電変換効率の高
い窒化物半導体発光素子を提供することができる。The present invention solves the conventional problems by undoping the well layer of the active layer of the multiple quantum well structure, and further defining the thickness and impurity concentration of the barrier layer, thereby achieving low power consumption. It is possible to provide a nitride semiconductor light emitting device having good light emission output and high photoelectric conversion efficiency.
【図1】図1は、本発明の一実施の形態であるLED素
子の構造を示す模式断面図である。FIG. 1 is a schematic sectional view showing a structure of an LED element according to an embodiment of the present invention.
【図2】図2は、実施例1の活性層の障壁層の不純物濃
度を段階的に変化させたときのリーク電流[図2
(a)]及び、順方向電圧[図2(b)]の変化をプロ
ットしたグラフである。FIG. 2 is a graph showing a leakage current when the impurity concentration of a barrier layer of an active layer in Example 1 is changed stepwise [FIG.
(A)] and a graph plotting changes in forward voltage [FIG. 2 (b)].
【図3】図3は、実施例1の活性層の障壁層の厚みを段
階的に変化させたときの順方向電圧[図3(a)]及
び、発光出力[図3(b)]の変化をプロットしたグラ
フである。FIG. 3 is a graph showing the relationship between the forward voltage [FIG. 3 (a)] and the emission output [FIG. 3 (b)] when the thickness of the barrier layer of the active layer in Example 1 is changed stepwise. It is the graph which plotted the change.
1・・・サファイア基板 2・・・バッファ層 3・・・アンドープGaN層 4・・・SiドープGaN層 5・・・アンドープGaN層 6・・・活性層 7・・・MgドープAlGaN層 8・・・MgドープGaN層 9・・・p電極 11・・・n電極 REFERENCE SIGNS LIST 1 sapphire substrate 2 buffer layer 3 undoped GaN layer 4 undoped GaN layer 5 undoped GaN layer 6 active layer 7 Mg doped AlGaN layer 8 ..Mg-doped GaN layer 9 ... p electrode 11 ... n electrode
Claims (4)
体層との間に、Inを含む窒化物半導体よりなる井戸層
と、井戸層と組成の異なる窒化物半導体よりなる障壁層
とが積層されてなる多重量子井戸構造の活性層を有し、
前記井戸層がアンドープであり、前記障壁層の単一膜厚
が70〜500オングストロームを有し更に障壁層にn
型不純物が5×1016〜1×1019/cm3ドープされ
ていることを特徴とする窒化物半導体素子。A well layer made of a nitride semiconductor containing In and a barrier layer made of a nitride semiconductor having a composition different from that of the well layer between an n-type nitride semiconductor layer and a p-type nitride semiconductor layer. Having an active layer of a multiple quantum well structure in which
The well layer is undoped, the barrier layer has a single thickness of 70 to 500 angstroms, and the barrier layer has n
A nitride semiconductor element, wherein a type impurity is doped at 5 × 10 16 to 1 × 10 19 / cm 3 .
層上に成長されてなることを特徴とする請求項1に記載
の窒化物半導体素子。2. The nitride semiconductor device according to claim 1, wherein said active layer is grown on an undoped nitride semiconductor layer.
〜500オングストロームの膜厚を有することを特徴と
する請求項2に記載の窒化物半導体素子。3. An undoped nitride semiconductor layer comprising:
3. The nitride semiconductor device according to claim 2, wherein the nitride semiconductor device has a thickness of about 500 Å.
ドープGaNからなることを特徴とする請求項2又は3
に記載の窒化物半導体素子。4. The undoped nitride semiconductor layer is made of undoped GaN.
3. The nitride semiconductor device according to item 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30061598A JP2000133883A (en) | 1998-10-22 | 1998-10-22 | Nitride semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30061598A JP2000133883A (en) | 1998-10-22 | 1998-10-22 | Nitride semiconductor element |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000133883A true JP2000133883A (en) | 2000-05-12 |
JP2000133883A5 JP2000133883A5 (en) | 2005-12-08 |
Family
ID=17886998
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30061598A Pending JP2000133883A (en) | 1998-10-22 | 1998-10-22 | Nitride semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2000133883A (en) |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003065526A1 (en) * | 2002-01-31 | 2003-08-07 | Nec Corporation | Quantum well structure and semiconductor element using it and production method of semiconductor element |
US6958497B2 (en) | 2001-05-30 | 2005-10-25 | Cree, Inc. | Group III nitride based light emitting diode structures with a quantum well and superlattice, group III nitride based quantum well structures and group III nitride based superlattice structures |
JP2007134507A (en) * | 2005-11-10 | 2007-05-31 | Sumitomo Electric Ind Ltd | Semiconductor light emitting element and manufacturing method thereof |
WO2009008202A1 (en) * | 2007-07-11 | 2009-01-15 | Sumitomo Electric Industries, Ltd. | Nitride semiconductor light emitting element and method for manufacturing nitride semiconductor light emitting element |
JP2009278088A (en) * | 2008-05-15 | 2009-11-26 | Palo Alto Research Center Inc | Light-emitting device with modulation doped active layers |
US7692182B2 (en) | 2001-05-30 | 2010-04-06 | Cree, Inc. | Group III nitride based quantum well light emitting device structures with an indium containing capping structure |
US7781777B2 (en) | 2004-03-08 | 2010-08-24 | Showa Denko K.K. | Pn junction type group III nitride semiconductor light-emitting device |
US20110121265A1 (en) * | 2009-07-15 | 2011-05-26 | Sumitomo Electric Industries, Ltd. | Group iii nitride semiconductor optical device |
JP2011159771A (en) * | 2010-01-29 | 2011-08-18 | Nec Corp | Nitride semiconductor light-emitting element, and manufacturing method of the nitride semiconductor light-emitting element, and electronic device |
US8344398B2 (en) | 2007-01-19 | 2013-01-01 | Cree, Inc. | Low voltage diode with reduced parasitic resistance and method for fabricating |
JP2013115372A (en) * | 2011-11-30 | 2013-06-10 | Sharp Corp | Semiconductor light-emitting element and manufacturing method therefor, manufacturing system for semiconductor light-emitting element |
US8507924B2 (en) | 2004-07-02 | 2013-08-13 | Cree, Inc. | Light emitting diode with high aspect ratio submicron roughness for light extraction and methods of forming |
US8519437B2 (en) | 2007-09-14 | 2013-08-27 | Cree, Inc. | Polarization doping in nitride based diodes |
US8536615B1 (en) | 2009-12-16 | 2013-09-17 | Cree, Inc. | Semiconductor device structures with modulated and delta doping and related methods |
US8575592B2 (en) | 2010-02-03 | 2013-11-05 | Cree, Inc. | Group III nitride based light emitting diode structures with multiple quantum well structures having varying well thicknesses |
US8604461B2 (en) | 2009-12-16 | 2013-12-10 | Cree, Inc. | Semiconductor device structures with modulated doping and related methods |
US8679876B2 (en) | 2006-11-15 | 2014-03-25 | Cree, Inc. | Laser diode and method for fabricating same |
US8772757B2 (en) | 2005-05-27 | 2014-07-08 | Cree, Inc. | Deep ultraviolet light emitting devices and methods of fabricating deep ultraviolet light emitting devices |
US9012937B2 (en) | 2007-10-10 | 2015-04-21 | Cree, Inc. | Multiple conversion material light emitting diode package and method of fabricating same |
US9417468B2 (en) | 2014-07-18 | 2016-08-16 | Samsung Electronics Co., Ltd. | Transmission type high-absorption optical modulator and method of manufacturing the same |
CN114038955A (en) * | 2021-02-25 | 2022-02-11 | 重庆康佳光电技术研究院有限公司 | Epitaxial structure of light-emitting chip, light-emitting chip and display back plate |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0997921A (en) * | 1995-07-21 | 1997-04-08 | Sumitomo Chem Co Ltd | Manufacture of iii-v compd. semiconductor |
JPH09116130A (en) * | 1995-02-03 | 1997-05-02 | Sumitomo Chem Co Ltd | Iii-v compound semiconductor and its manufacture and light emitting device |
JPH09129920A (en) * | 1995-10-27 | 1997-05-16 | Sumitomo Chem Co Ltd | Iii-v compound semiconductor for light emitting device and light emitting device |
JPH10126006A (en) * | 1995-11-06 | 1998-05-15 | Nichia Chem Ind Ltd | Nitride semiconductor device |
JPH10200215A (en) * | 1997-01-08 | 1998-07-31 | Mitsubishi Cable Ind Ltd | Semiconductor light emitting element and manufacturing method thereof |
-
1998
- 1998-10-22 JP JP30061598A patent/JP2000133883A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09116130A (en) * | 1995-02-03 | 1997-05-02 | Sumitomo Chem Co Ltd | Iii-v compound semiconductor and its manufacture and light emitting device |
JPH0997921A (en) * | 1995-07-21 | 1997-04-08 | Sumitomo Chem Co Ltd | Manufacture of iii-v compd. semiconductor |
JPH09129920A (en) * | 1995-10-27 | 1997-05-16 | Sumitomo Chem Co Ltd | Iii-v compound semiconductor for light emitting device and light emitting device |
JPH10126006A (en) * | 1995-11-06 | 1998-05-15 | Nichia Chem Ind Ltd | Nitride semiconductor device |
JPH10200215A (en) * | 1997-01-08 | 1998-07-31 | Mitsubishi Cable Ind Ltd | Semiconductor light emitting element and manufacturing method thereof |
Cited By (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9054253B2 (en) | 2001-05-30 | 2015-06-09 | Cree, Inc. | Group III nitride based quantum well light emitting device structures with an indium containing capping structure |
US6958497B2 (en) | 2001-05-30 | 2005-10-25 | Cree, Inc. | Group III nitride based light emitting diode structures with a quantum well and superlattice, group III nitride based quantum well structures and group III nitride based superlattice structures |
US7312474B2 (en) | 2001-05-30 | 2007-12-25 | Cree, Inc. | Group III nitride based superlattice structures |
US8044384B2 (en) | 2001-05-30 | 2011-10-25 | Cree, Inc. | Group III nitride based quantum well light emitting device structures with an indium containing capping structure |
US7692182B2 (en) | 2001-05-30 | 2010-04-06 | Cree, Inc. | Group III nitride based quantum well light emitting device structures with an indium containing capping structure |
US9112083B2 (en) | 2001-05-30 | 2015-08-18 | Cree, Inc. | Group III nitride based light emitting diode structures with a quantum well and superlattice, group III nitride based quantum well structures and group III nitride based superlattice structures |
US8546787B2 (en) | 2001-05-30 | 2013-10-01 | Cree, Inc. | Group III nitride based quantum well light emitting device structures with an indium containing capping structure |
US7183584B2 (en) | 2002-01-31 | 2007-02-27 | Nec Corporation | Quantum well structure and semiconductor device using it and production method of semiconductor element |
WO2003065526A1 (en) * | 2002-01-31 | 2003-08-07 | Nec Corporation | Quantum well structure and semiconductor element using it and production method of semiconductor element |
US7781777B2 (en) | 2004-03-08 | 2010-08-24 | Showa Denko K.K. | Pn junction type group III nitride semiconductor light-emitting device |
US8507924B2 (en) | 2004-07-02 | 2013-08-13 | Cree, Inc. | Light emitting diode with high aspect ratio submicron roughness for light extraction and methods of forming |
US8772757B2 (en) | 2005-05-27 | 2014-07-08 | Cree, Inc. | Deep ultraviolet light emitting devices and methods of fabricating deep ultraviolet light emitting devices |
JP2007134507A (en) * | 2005-11-10 | 2007-05-31 | Sumitomo Electric Ind Ltd | Semiconductor light emitting element and manufacturing method thereof |
US7547910B2 (en) | 2005-11-10 | 2009-06-16 | Sumitomo Electric Industries, Ltd. | Semiconductor light-emitting device and method of manufacturing semiconductor light-emitting device |
US8679876B2 (en) | 2006-11-15 | 2014-03-25 | Cree, Inc. | Laser diode and method for fabricating same |
US9041139B2 (en) | 2007-01-19 | 2015-05-26 | Cree, Inc. | Low voltage diode with reduced parasitic resistance and method for fabricating |
US8344398B2 (en) | 2007-01-19 | 2013-01-01 | Cree, Inc. | Low voltage diode with reduced parasitic resistance and method for fabricating |
US7973322B2 (en) | 2007-07-11 | 2011-07-05 | Sumitomo Electric Industries, Ltd. | Nitride semiconductor light emitting device and method for forming the same |
WO2009008202A1 (en) * | 2007-07-11 | 2009-01-15 | Sumitomo Electric Industries, Ltd. | Nitride semiconductor light emitting element and method for manufacturing nitride semiconductor light emitting element |
US8519437B2 (en) | 2007-09-14 | 2013-08-27 | Cree, Inc. | Polarization doping in nitride based diodes |
US9012937B2 (en) | 2007-10-10 | 2015-04-21 | Cree, Inc. | Multiple conversion material light emitting diode package and method of fabricating same |
JP2009278088A (en) * | 2008-05-15 | 2009-11-26 | Palo Alto Research Center Inc | Light-emitting device with modulation doped active layers |
US8927962B2 (en) * | 2009-07-15 | 2015-01-06 | Sumitomo Electric Industries, Ltd. | Group III nitride semiconductor optical device |
US20110121265A1 (en) * | 2009-07-15 | 2011-05-26 | Sumitomo Electric Industries, Ltd. | Group iii nitride semiconductor optical device |
US8604461B2 (en) | 2009-12-16 | 2013-12-10 | Cree, Inc. | Semiconductor device structures with modulated doping and related methods |
US8536615B1 (en) | 2009-12-16 | 2013-09-17 | Cree, Inc. | Semiconductor device structures with modulated and delta doping and related methods |
JP2011159771A (en) * | 2010-01-29 | 2011-08-18 | Nec Corp | Nitride semiconductor light-emitting element, and manufacturing method of the nitride semiconductor light-emitting element, and electronic device |
US8575592B2 (en) | 2010-02-03 | 2013-11-05 | Cree, Inc. | Group III nitride based light emitting diode structures with multiple quantum well structures having varying well thicknesses |
JP2013115372A (en) * | 2011-11-30 | 2013-06-10 | Sharp Corp | Semiconductor light-emitting element and manufacturing method therefor, manufacturing system for semiconductor light-emitting element |
US9417468B2 (en) | 2014-07-18 | 2016-08-16 | Samsung Electronics Co., Ltd. | Transmission type high-absorption optical modulator and method of manufacturing the same |
CN114038955A (en) * | 2021-02-25 | 2022-02-11 | 重庆康佳光电技术研究院有限公司 | Epitaxial structure of light-emitting chip, light-emitting chip and display back plate |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3719047B2 (en) | Nitride semiconductor device | |
JP3250438B2 (en) | Nitride semiconductor light emitting device | |
JP3622562B2 (en) | Nitride semiconductor light emitting diode | |
JP3868136B2 (en) | Gallium nitride compound semiconductor light emitting device | |
JP3063756B1 (en) | Nitride semiconductor device | |
JP3744211B2 (en) | Nitride semiconductor device | |
JP4629178B2 (en) | Nitride semiconductor device | |
JP2000133883A (en) | Nitride semiconductor element | |
JP3890930B2 (en) | Nitride semiconductor light emitting device | |
JP3460641B2 (en) | Nitride semiconductor device | |
WO2013015035A1 (en) | Semiconductor light-emitting element | |
JP2001148507A (en) | Nitride semiconductor device | |
JP2000232237A (en) | Nitride semiconductor element | |
JP2001168390A (en) | Nitride semiconductor element | |
JPH07162038A (en) | Gallium nitride compound semiconductor light emitting diode | |
JP3470622B2 (en) | Nitride semiconductor light emitting device | |
JP4356555B2 (en) | Nitride semiconductor device | |
JP4815732B2 (en) | Nitride semiconductor device | |
JP4770058B2 (en) | LIGHT EMITTING ELEMENT AND DEVICE | |
JP3620292B2 (en) | Nitride semiconductor device | |
JPH11191638A (en) | Nitride semiconductor device | |
JP2001298215A (en) | Light-emitting element | |
JP4622466B2 (en) | Nitride semiconductor device | |
JP4085782B2 (en) | Nitride semiconductor device | |
JP3271661B2 (en) | Nitride semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20051021 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20051021 |
|
A131 | Notification of reasons for refusal |
Effective date: 20090303 Free format text: JAPANESE INTERMEDIATE CODE: A131 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090507 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20100316 |
|
A521 | Written amendment |
Effective date: 20100616 Free format text: JAPANESE INTERMEDIATE CODE: A523 |
|
A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Effective date: 20100727 Free format text: JAPANESE INTERMEDIATE CODE: A911 |
|
A912 | Removal of reconsideration by examiner before appeal (zenchi) |
Effective date: 20101112 Free format text: JAPANESE INTERMEDIATE CODE: A912 |