US8772757B2 - Deep ultraviolet light emitting devices and methods of fabricating deep ultraviolet light emitting devices - Google Patents
Deep ultraviolet light emitting devices and methods of fabricating deep ultraviolet light emitting devices Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
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- B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
Definitions
- This invention relates to semiconductor light emitting devices and methods of fabricating light emitting devices.
- a semiconductor light emitting device includes a semiconductor light emitting element having one or more semiconductor layers that are configured to emit coherent and/or incoherent light upon energization thereof.
- a light emitting diode or laser diode generally includes an active region on a microelectronic substrate.
- the microelectronic substrate may be, for example, gallium arsenide, gallium phosphide, alloys thereof, silicon carbide and/or sapphire.
- LEDs that are fabricated in or on silicon carbide, because these LEDs can emit radiation in the blue/green portions of the visible spectrum. See, for example, U.S. Pat. No. 5,416,342 to Edmond et al., entitled BLUE LIGHT-EMITTING DIODE WITH HIGH EXTERNAL QUANTUM EFFICIENCY, assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein. There also has been much interest in LEDs that include gallium nitride-based diode regions on silicon carbide substrates, because these devices also may emit light with high efficiency. See, for example, U.S. Pat. No.
- Ultraviolet light emitting devices have also been described, for example, in U.S. Pat. No. 6,734,033 to Emerson et al. entitled ULTRAVIOLET LIGHT EMITTING DIODE; U.S. Pat. No. 6,664,560 to Emerson et al. entitled ULTRAVIOLET LIGHT EMITTING DIODE; U.S. Pat. No. 5,661,074 to Tischler entitled HIGH BRIGHTNESS ELECTROLUMINESCENT DEVICE EMITTING IN THE GREEN TO ULTRAVIOLET SPECTRUM AND METHOD OF MAKING THE SAME; U.S. Pat. No. 5,874,747 to Redwing et al.
- Some embodiments of the present invention provide light emitting devices and methods of fabricating light emitting devices that emit at wavelengths less than 360 nm with wall plug efficiencies of at least than 4%. In other embodiments, the wall plug efficiencies are at least 5%. In further embodiments, the wall plug efficiencies are at least 6%. Additionally, the semiconductor light emitting devices may have a direct current lifetime of at least 100 hours, at least 500 hours or at least 1000 hours.
- the light emitting devices emit at wavelengths less than 345 nm with wall plug efficiencies of at least 2%. In other embodiments, the wall plug efficiencies of devices emitting in this wavelength range are at least 3%. In further embodiments, the wall plug efficiencies are at least 4%. Additionally, the semiconductor light emitting devices may have a direct current lifetime of at least 100 hours, at least 500 hours or at least 1000 hours.
- the light emitting devices emit at wavelengths less than 330 nm with wall plug efficiencies of at least 0.4%. Additionally, the semiconductor light emitting devices may have a direct current lifetime of at least 100 hours, at least 500 hours or at least 1000 hours.
- the light emitting devices have a peak output wavelength of 345 nm or less and a wall plug efficiency of at least 4% at a current density of less than 0.35 ⁇ A/ ⁇ m 2 and/or a wall plug efficiency of at least 6% at a current density of less than 0.08 ⁇ A/ ⁇ m 2 .
- Further embodiments of the present invention provide light emitting devices and methods of fabricating light emitting devices having a peak output wavelength of not greater than 360 nm and provides a radiant output of at least about 0.047 ⁇ W/ ⁇ m 2 normalized to chip size.
- the peak output wavelength is 345 nm or less.
- the light emitting device may have a wall plug efficiency of at least 3% or even a wall plug efficiency of at least 6%.
- the peak output wavelength is 320 nm or less.
- Some embodiments of the present invention provide light emitting devices and methods of fabricating light emitting devices that include a low defect density base structure comprising an n-type SiC substrate and a GaN layer doped with n-type dopants.
- a quantum well active region is provided on the low defect density base structure that emits light at a wavelength of less than 360 nm.
- the quantum well active region comprises a GaN, AlGaN or AlInGaN layer and a doped AlGaN barrier layer.
- An AlGaN layer is provided on the quantum well active region and a GaN based contact layer is provided on the AlGaN layer.
- the doped GaN layer may be a doped GaN layer having a defect density of less than about 4 ⁇ 10 8 cm ⁇ 2 .
- the GaN layer doped with n-type dopants may comprise GaN doped with silicon.
- the AlGaN layer on the quantum well active region may comprise an AlGaN layer doped with a p-type dopant on the quantum well active region and the GaN based contact layer on the AlGaN layer may comprise a GaN based contact layer doped with a p-type dopant.
- the p-type dopant may comprise Mg.
- the barrier layer may be doped with Si.
- the quantum well active region comprises ten quantum well layers and eleven barrier layers with the quantum well layers being disposed between adjacent barrier layers. In other embodiments, the quantum well active region comprises five quantum well layers and six barrier layers with the quantum well layers being disposed between adjacent barrier layers.
- the light emitting device may have an overall thickness of less than about 2.5 ⁇ m. In further embodiments, the device may have an overall thickness of less than 2.0 ⁇ m or even 1.0 ⁇ m.
- Some embodiments of the present invention provide light emitting devices and methods of fabricating light emitting devices that include a quantum well active region on the doped GaN layer.
- the quantum well active region is configured to emit at a peak output wavelength of not greater than 360 nm and comprises a barrier layer comprising Al w In x Ga 1-x-w N, where 0 ⁇ w ⁇ 1, 0 ⁇ x ⁇ 1 and 0 ⁇ w+x ⁇ 1 and where w and x provide a barrier energy greater than a bandgap energy of GaN or within about 1 eV of the bandgap energy of GaN and a well layer comprising Al y In z Ga 1-y-z N on the barrier layer, where 0 ⁇ y ⁇ 1, 0 ⁇ z ⁇ 1 and 0 ⁇ y+z ⁇ 1.
- this buffer structure comprises a GaN layer doped with an n-type dopant and a quantum well active region is provided on the GaN layer doped with an n-type dopant.
- Additional embodiments of the present invention include a semiconductor substrate and the quantum well active region is provided on the semiconductor substrate.
- the semiconductor substrate may be conducting or insulating.
- the semiconductor substrate comprises SiC or GaN. In other embodiments, the semiconductor substrate comprises sapphire.
- a first layer of Al p Ga 1-p N doped with a p-type dopant may be provided on the quantum well active region where 0 ⁇ p ⁇ 0.8 and a second layer of Al q Ga 1-q N doped with a p-type dopant is provided on the first layer, where 0 ⁇ q ⁇ p.
- the barrier layer is doped with the n-type dopant.
- the n-type dopant may be Si.
- the p-type dopant may be Mg.
- the barrier layer may have a thickness of from about 10 ⁇ to about 100 ⁇ and the well layer may have a thickness of from about 10 ⁇ to about 30 ⁇ .
- the first layer may have a thickness of about 50 ⁇ and the second layer may have a thickness of about 300 ⁇ .
- the barrier layer comprises Al w In x Ga 1-x-w N, where 0.2 ⁇ w ⁇ 0.8, 0 ⁇ x ⁇ 0.2 and 0.2 ⁇ w+x ⁇ 1 and has a thickness of from about 10 ⁇ to about 50 ⁇
- the well layer comprises Al y In z Ga 1-y-z N on the barrier layer, where 0 ⁇ y ⁇ 0.4, 0 ⁇ z ⁇ 0.1 and 0 ⁇ y+z ⁇ 0.4 and has a thickness of from about 10 ⁇ to about 30 ⁇
- the first layer comprises Al p Ga 1-p N doped with a p-type dopant on the quantum well active region where 0.3 ⁇ p ⁇ 0.8 and has a thickness of from about 50 ⁇ to about 250 ⁇
- the second layer comprises Al q Ga 1-q N doped with a p-type dopant on the first layer, where 0 ⁇ q ⁇ p and the second layer has a thickness of from about 200 ⁇ to about 600 ⁇
- the quantum well active region comprises from about 3 to about 12 quantum wells of the well layer and
- the barrier layer comprises Al w In x Ga 1-x-w N, where 0.3 ⁇ w ⁇ 0.8, 0 ⁇ x ⁇ 0.2 and 0.3 ⁇ w+x ⁇ 1 and has a thickness of from about 10 ⁇ to about 50 ⁇
- the well layer comprises Al y In z Ga 1-y-z N on the barrier layer, where 0 ⁇ y ⁇ 0.4, 0 ⁇ z ⁇ 0.1 and 0 ⁇ y+z ⁇ 0.5 and has a thickness of from about 10 ⁇ to about 30 ⁇
- the first layer comprises Al p Ga 1-p N doped with a p-type dopant on the quantum well active region where 0.3 ⁇ p ⁇ 0.8 and has a thickness of from about 50 ⁇ to about 250 ⁇
- the second layer comprises Al q Ga 1-q N doped with a p-type dopant on the first layer, where 0 ⁇ q ⁇ p and the second layer has a thickness of from about 200 ⁇ to about 600 ⁇
- the quantum well active region comprises from about 3 to about 12 quantum wells of the well layer and
- the quantum well active region comprises ten quantum wells of the well layer and corresponding barrier layers and a peak output wavelength of the light emitting device is approximately 340 nm.
- the quantum well active region comprises ten quantum wells of the well layer and corresponding barrier layers and a peak output wavelength of the light emitting device is approximately 325 nm.
- FIG. 1 is a cross-sectional view illustrating deep ultraviolet semiconductor light emitting devices according to some embodiments of the present invention.
- FIG. 2 is a detailed view of an active region of deep ultraviolet semiconductor light emitting devices according to some embodiments of the present invention.
- FIG. 3 is a graph of device performance of an LED according to embodiments of the present invention emitting at a peak wavelength of 335 nm.
- FIG. 4 is a graph of burn-in characteristics of multiple 340 nm LEDs according to embodiments of the present invention.
- first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
- relative terms such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, can therefore, encompasses both an orientation of “lower” and “upper,” depending of the particular orientation of the figure.
- Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated or described as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention.
- references to a structure or feature that is disposed “adjacent” another feature may have portions that overlap or underlie the adjacent feature.
- LEDs disclosed herein include a substrate
- the epitaxial growth substrate on which the epitaxial layers comprising an LED are grown may be removed, and the freestanding epitaxial layers may be mounted on a substitute carrier substrate or submount which may have different thermal, electrical, structural and/or optical characteristics than the original substrate.
- the invention described herein is not limited to structures having crystalline epitaxial growth substrates and may be utilized in connection with structures in which the epitaxial layers have been removed from their original growth substrates and bonded to substitute carrier substrates.
- Some embodiments of the present invention may provide for deep ultraviolet light emitting devices having an active region formed on a low defect density base structure as described herein.
- deep ultraviolet refers to a peak output wavelength of not greater than 360 nm.
- Further embodiments of the present invention provide for deep ultraviolet light emitting devices having improved wall plug efficiency. Wall plug efficiency refers to the ratio of output power to input power.
- some embodiments of the present invention provide deep ultraviolet light emitting devices having improved direct current lifetimes. Direct current lifetime refers to the time it takes for the output power of the device to degrade 50% in continuous wave operation or the equivalent of continuous wave operation. For example, if pulsed operation is utilized, the direct current lifetime is the total time that the device is active and does not include the time when the device is inactive. Still other embodiments of the present invention provide deep ultraviolet light emitting devices that support a high current density.
- Embodiments of the present invention may be particularly well suited for use in nitride-based light emitting devices such as Group III-nitride based devices.
- Group III nitride refers to those semiconducting compounds formed between nitrogen and the elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and/or indium (In).
- Al aluminum
- Ga gallium
- In indium
- the term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN.
- the Group III elements can combine with nitrogen to form binary (e.g., GaN), ternary (e.g., AlGaN, AlInN), and quaternary (e.g., AlInGaN) compounds. These compounds all have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements. Accordingly, formulas such as Al x Ga 1-x N where 0 ⁇ x ⁇ 1 may be used to describe them. Furthermore, references to a GaN based material refers to a material that includes GaN and may include binary, ternary, quaternary or other materials that include GaN.
- Light emitting devices may include a light emitting diode, laser diode and/or other semiconductor device which includes one or more semiconductor layers, which may include silicon, silicon carbide, gallium nitride and/or other semiconductor materials, a substrate which may include sapphire, silicon, silicon carbide gallium nitride and/or other microelectronic substrates, and one or more contact layers which may include metal and/or other conductive layers.
- deep ultraviolet light emitting devices such as LEDs, having a peak output wavelength of not greater than 360 nm are provided.
- deep ultraviolet light emitting devices, such as LEDs, having a peak output wavelength of not greater than 345 nm are provided.
- deep ultraviolet light emitting devices, such as LEDs, having a peak output wavelength of not greater than 330 nm are provided.
- light emitting devices are provided that have a peak output wavelength of not greater than 360 nm and a wall plug efficiency of greater than 4% and in some embodiments, greater than 5% and in others greater than 6% where in all cases the current density is less than 0.35 ⁇ A/ ⁇ m 2 .
- Some embodiments of the present invention provide light emitting devices that have a peak output wavelength of 345 nm or less and a wall plug efficiency of greater than 2% or greater than 3% or greater than 4% where in all cases the current density is less than 0.35 ⁇ A/ ⁇ m2.
- the wallplug efficiency is greater than 6% when the current density is less than 0.08 ⁇ A/ ⁇ m 2 .
- Some embodiments of the present invention provide light emitting devices that have a peak output wavelength of 330 nm or less and a wall plug efficiency of at least 0.4% when the current density is less than 0.35 ⁇ A/ ⁇ m 2 .
- light emitting devices are provided that have a peak output wavelength of not greater than 360 nm and an output power of at least 5 mW at a current density of less than roughly 0.35 ⁇ A/ ⁇ m 2 .
- Some embodiments of the present invention provide light emitting devices that have a peak output wavelength of 345 nm or less and an output power of at least 3 mW at a current density of less than about 0.35 ⁇ A/ ⁇ m 2 .
- light emitting devices that have a peak output wavelength of 330 nm or less and an output power of at least 0.3 mW at a current density of less than about 0.35 ⁇ A/ ⁇ m 2 .
- current density refers the current per unit area.
- unit area may correspond to an area of the light emitting device and the per unit area measurement refers to the average current density in the area of the light emitting device.
- particular regions of the device may have a higher than average current density while other regions of the device have a lower than average current density.
- characterizations of the performance of light emitting devices that may apply to arrays of chips or single chips are provided herein with reference to a single chip as opposed to an array of chips.
- the output power of 3 mW is the output power of a single chip, not an array of chips.
- a base structure refers to a structure on which the active region is formed.
- a low defect density base structure refers to a base structure having a layer on which the active region is formed that has a defect density of less than about 4 ⁇ 10 8 cm ⁇ 2 .
- the term defect density refers to a number of threading dislocations per unit area. Such unit area may correspond to an area of the light emitting device and the per unit area measurement refers to the average number of defects in the area of the light emitting device. Thus, for example, particular regions of the device may have a higher than average number of defects while other regions of the device have a lower than average number of defects.
- Measurement of dislocation density may be made using conventional defect measurement techniques, such as those used in measuring threading dislocation defects in Group III nitride materials. Such techniques may include, for example, etching and optical imaging and/or atomic force microscopy. Following etching or polishing, small diameter, shallow pits are formed at the site of threading dislocations and are readily observed by atomic force microscopy. The threading dislocation density is sampled and the average value used to characterize the threading dislocation defect density.
- light emitting devices are provided that have a peak output wavelength of not greater than 360 nm and a direct current lifetime of greater than 100 hours, in some embodiments greater than 500 hours and in some embodiments, greater than 1000 hours.
- Some embodiments of the present invention provide light emitting devices that have a peak output wavelength of 345 nm or less and a direct current lifetime of greater than 100 hours, in some embodiments greater than 500 hours and in some embodiments, greater than 1000 hours.
- Some embodiments of the present invention provide light emitting devices that have a peak output wavelength of 330 nm or less and a direct current lifetime of greater than 100 hours, in some embodiments greater than 500 hours and in some embodiments, greater than 1000 hours.
- FIG. 1 illustrates a light emitting device, such as a light emitting diode, according to some embodiments of the present invention.
- an n-type SiC substrate 10 has an optional buffer layer 12 disposed on a first surface of the substrate 10 .
- the SiC substrate may be a substrate such as available from Cree, Inc., Durham, N.C. Techniques for fabricating SiC substrates are known to those of skill in the art and, therefore, need not be described further herein. For example, methods for producing SiC substrates are described, for example, in U.S. Pat. Nos. Re. 34,861; 4,946,547; 6,706,114, the contents of which are incorporated herein by reference in their entirety.
- the SiC substrate may be 6H or 4H polytypes of SiC. While exemplary embodiments of the present invention are described with reference to a conductive SiC substrate, other substrates may be used, such as a conductive GaN substrate. Also, insulating substrates, such as sapphire and/or insulating or semi-insulating SiC or GaN, could also be utilized with a lateral device structure.
- the buffer layer 12 may be an AlGaN or other suitable buffer layer capable of providing for growth of a low defect density Group III nitride layer on the buffer layer 12 .
- the buffer layer 12 may, optionally, include gallium nitride dots (not shown) on the surface of the silicon carbide substrate, with the dots in turn being covered with AlGaN caps.
- the buffer layer 12 can also be described as being on the dots and their caps.
- Such a structure and method of fabricating such structures are described in U.S. Pat. Nos. 6,734,033 and 6,664,560, the disclosures of which are incorporated herein as if set forth in their entirety.
- Exemplary buffer structures and compositions are also set forth in U.S. Pat. Nos. 5,393,993 and 5,523,589, the disclosures of which are incorporated herein as if set forth in their entirety.
- the buffer layer 12 may include optional mask regions 14 that may, for example, be a SiN layer and a Group III nitride layer 16 , such as a GaN layer doped with Si, formed on the buffer layer and the mask regions 14 .
- the SiN may be stoichiometric or non-stoichiometric.
- the inclusion of the SiN layer 14 may provide for epitaxial lateral overgrowth of the Group III nitride layer 16 to thereby reduce the defect density of the Group III nitride layer 16 .
- Other techniques for growing a Group III nitride layer, such as a GaN layer may also be utilized, such as cantilevered or pendeo-epitaxial growth.
- a Group III nitride layer 16 is provided on the buffer layer 12 .
- the Group III nitride layer is doped with n-type dopants, such as Si.
- the Group III nitride layer is GaN doped with Si.
- the Group III nitride layer 16 may be a low defect density layer as discussed above and having a defect density of 4 ⁇ 10 8 cm ⁇ 2 or less.
- the Group III nitride layer 16 has a thickness of from about 0.8 ⁇ m to about 2.0 ⁇ m.
- the substrate 10 , buffer layer 12 and/or Group III nitride layer 16 are absorbing in the wavelength range of the output of the light emitting device.
- a quantum well active region 20 is provided on the Group III nitride layer 16 .
- the quantum well active region 20 may include one or more quantum well structures where the barrier layers of the quantum well structures have a barrier energy of greater than the bandgap of GaN or near the bandgap energy of GaN, such as within about 1 eV of the bandgap energy of GaN.
- the quantum well active region 20 includes from 3 to 12 quantum wells.
- the thickness and composition of the well layers may be selected so as to provide a desired output wavelength. Furthermore, changes in composition of the well layer may be offset by changes in the thickness of the well layer.
- GaN well layer having a thickness of about 15 ⁇ may be utilized, whereas to provide an output wavelength of 320 mm, an AlGaN well layer may be utilized.
- the thickness and composition of the barrier and well layers may be selected so as to provide optimized performance. This may include balancing sufficient composition to provide carrier confinement for the emission wavelength while maintaining performance. This may also include optimizing thickness to provide sufficient carrier confinement while minimizing stress (strain) in the film, which in turn minimizes cracking in the epitaxial layers.
- stress stress
- FIG. 2 is a more detailed view of a quantum well active region 20 according to some embodiments of the present invention. While FIG. 2 is illustrated as having five quantum well structures, other numbers of quantum well structures as described herein may be provided. As seen in FIG. 2 , the quantum well structures include a barrier layer 22 and a well layer 24 with multiple repetitions of each. The well layers 24 are each disposed between two opposing barrier layers 22 . Thus, for n well layers 24 , n+1 barrier layers 22 may be provided. Furthermore, a barrier layer 22 may be provided as one or more layers as described, for example, in United States Patent Publication No.
- the barrier layers 22 and the well layers 24 may be fabricated using conventional Group III nitride growth techniques such as those discussed above.
- the barrier layer 22 has a thickness of from about 10 ⁇ to about 100 ⁇ and the well layer 24 has a thickness of from about 10 ⁇ to about 30 ⁇ .
- an AlGaN layer 30 doped with p-type dopants is provided on the quantum well active region 20 .
- the AlGaN layer 30 may be doped with Mg.
- the AlGaN layer 30 may have an aluminum percentage of from about 40% to about 60%.
- the AlGaN layer 30 may have a thickness of from about 50 ⁇ to about 250 ⁇ .
- a contact layer 32 may also be provided on the AlGaN layer 30 .
- the contact layer 32 may be a GaN based layer and may have a lower percentage of Al than the AlGaN layer 30 .
- the contact layer 32 may be doped with a p-type dopant, such as Mg, and may have a thickness of from about 200 ⁇ to about 600 ⁇ .
- the AlGaN layer 30 and the contact layer 32 may be fabricated using conventional. Group III nitride growth techniques such as those discussed above.
- an ohmic contact 40 may be provided on the contact layer 32 and an ohmic contact 42 may be provided on a second surface of the substrate 10 opposite the first surface.
- the contact 40 may be a platinum contact.
- Other materials may be used for the ohmic contact 40 .
- the ohmic contact may comprise rhodium, zinc oxide, palladium, palladium oxide, titanium, nickel/gold, nickel oxide/gold, nickel oxide/platinum and/or titanium/gold.
- the ohmic contact has an average thickness less than 50 ⁇ .
- the ohmic contact has an average thickness less than 25 ⁇ , and in further embodiments, the ohmic contact has an average thickness less than 15 ⁇ .
- the ohmic contact has an average thickness of about 10 ⁇ .
- the ohmic contact has an average thickness of 5 ⁇ or less, 3 ⁇ or less or even about 1 ⁇ .
- the ohmic contact 40 may be formed by electron beam (e-beam) evaporation or any other suitable techniques for controllably forming atomically thin metallic films.
- e-beam electron beam
- a metal source target is heated in a vacuum chamber to the point of vaporization by a high intensity electron beam which melts a region of the target.
- An epitaxial wafer placed within the chamber is controllably coated with vaporized metal.
- E-beam evaporation and other film deposition methods are described in Chapter 6 of I NTRODUCTION TO M ICROELECTRONIC F ABRICATION by R. Jaeger (2nd Ed. 2002).
- the deposition rate of the process may be controlled by changing the current and energy of the electron beam. In some embodiments, the deposition rate is maintained at a low rate, e.g. in the range of 0.1-0.5 ⁇ per second in order to maintain adequate control of film thickness.
- the film deposition may be controlled during deposition by monitoring the transmission properties of a witness slide on which the ohmic metal film is simultaneously deposited.
- the witness slide may be sapphire, quartz, or any other optically transmissive material on which a metal film may be deposited.
- the transmission sensitivity to the metal thickness is dependent upon the wavelength of the light used in the monitoring process. Namely, the transmission sensitivity is enhanced at shorter wavelengths.
- the transmission properties of a sapphire witness slide are measured during or after film deposition by means of a monitoring system employing a UV source capable of emitting light at wavelengths of 350 nm or less, such as a UV spectrophotometer.
- the contact 42 may be any suitable material for forming an ohmic contact to the n-type SiC substrate 10 .
- the ohmic contact 42 may be nickel or other suitable material.
- the substrate 10 may be absorbing at the output wavelength of the device, the contact 42 need not be transparent or reflecting.
- any suitable technique for forming an ohmic contact to the substrate 10 may be utilized. Such techniques are known to those of skill in the art and, therefore, need not be described further herein.
- the barrier layer 22 comprises Al w In x Ga 1-x-w N, where 0.2 ⁇ w ⁇ 0.8, 0 ⁇ x ⁇ 0.2 and 0.2 ⁇ w+x ⁇ 1 and has a thickness of about 10 ⁇ to 60 ⁇ .
- the well layer 24 comprises Al y In z Ga 1-y-z N on the barrier layer, where 0 ⁇ y ⁇ 0.4, 0 ⁇ z ⁇ 0.1 and 0 ⁇ y+z ⁇ 0.5 and has a thickness of from about 10 ⁇ to about 30 ⁇ .
- the AlGaN layer 30 comprises Al p Ga 1-p N doped with a p-type dopant on the quantum well active region where 0.3 ⁇ p ⁇ 0.8 and has a thickness of from about 50 ⁇ to about 250 ⁇ and the contact layer 32 comprises Al q Ga 1-q N doped with a p-type dopant on the AlGaN layer 30 , where 0 ⁇ q ⁇ p and the contact layer 32 has a thickness of from about 200 ⁇ to about 600 ⁇ .
- the quantum well active region 20 comprises from about 3 to about 12 quantum wells of the well layer 24 and corresponding barrier layers 22 .
- the AlGaN layer 30 comprises Al p Ga 1-p N doped with a p-type dopant on the quantum well active region where 0.3 ⁇ p ⁇ 0.8 and has a thickness of from about 50 ⁇ to about 250 ⁇ and the contact layer 32 comprises Al q Ga 1-q N doped with a p-type dopant on the AlGaN layer 30 , where 0 ⁇ q ⁇ p and the contact layer 32 has a thickness of from about 200 ⁇ to about 600 ⁇ .
- the quantum well active region 20 comprises from about 3 to about 12 quantum wells of the well layer 24 and corresponding barrier layers 22 .
- the barrier layer 22 comprises Al w In x Ga 1-x-w N, where 0.3 ⁇ w ⁇ 0.8, 0 ⁇ x ⁇ 0.2 and 0.3 ⁇ w+x ⁇ 1 and has a thickness of from about 10 ⁇ to about 50 ⁇ and the well layer 24 comprises Al y In z Ga 1-y-z N on the barrier layer, where 0 ⁇ y ⁇ 0.4, 0 ⁇ z ⁇ 0.1 and 0 ⁇ y+z ⁇ 0.5 and has a thickness of from about 10 ⁇ to about 30 ⁇ .
- the AlGaN layer 30 comprises Al p Ga 1-p N doped with a p-type dopant on the quantum well active region where 0.3 ⁇ p ⁇ 0.8 and has a thickness of from about 50 ⁇ to about 250 ⁇ and the contact layer 32 comprises Al q Ga 1-q N doped with a p-type dopant on the AlGaN layer 30 , where 0 ⁇ q ⁇ p and the contact layer 32 has a thickness of from about 200 ⁇ to about 600 ⁇ .
- the quantum well active region 20 comprises from about 3 to about 12 quantum wells of the well layer 24 and corresponding barrier layers 22 .
- the quantum well active region 20 comprises ten quantum wells of the well layer and corresponding barrier layers.
- the quantum well active region 20 comprises ten quantum wells of the well layer and corresponding barrier layers.
- the GaN layer doped with an n-type dopant has a defect density of less than about 4 ⁇ 10 8 cm 2 .
- the overall thickness of the light emitting device is about 2.5 ⁇ m or less. In further embodiments of the present invention, the overall thickness of the light emitting device is from about 1 ⁇ m to about 2.5 ⁇ m.
- FIGS. 1 and 2 While embodiments of the present invention are illustrated in FIGS. 1 and 2 with reference to particular light emitting device structures, other structures may be provided according to some embodiments of the present invention.
- a sapphire substrate rather than a SiC substrate may be utilized.
- a contact layer may be provided between the sapphire substrate and the quantum well active region.
- embodiments of the present invention may be provided on conducting or insulating substrates and as vertical or lateral devices.
- FIGS. 1 and 2 these exemplary materials are not intended to limit the scope of the present invention other than as described herein.
- five quantum well structures are illustrated in FIG. 2
- other numbers of quantum well structures may be utilized. Accordingly, embodiments of the present invention should not be construed as limited to the particular illustrations of FIGS. 1 and 2 .
- FIG. 3 illustrates the device performance of an LED emitting at a peak wavelength of 335 nm.
- the device has a chip size of 290 ⁇ m ⁇ 290 ⁇ m, a device mesa size of 250 ⁇ m ⁇ 250 ⁇ m, and a device p-electrode size of 240 ⁇ m ⁇ 240 ⁇ m.
- the device is supporting a current density of 0.347 ⁇ A/ ⁇ m 2 .
- the device has an output power of 2.6 mW at a forward voltage of 3.7V.
- the corresponding wall plug efficiency for this example at 20 mA drive current is 3.5%. As the drive current is reduced, the wall plug efficiency increases with wall plug efficiency rising above 5% for drive currents less than 5 mA.
- FIG. 4 illustrates burn-in characteristics for multiple 340 nm devices.
- the device has a chip size of 290 ⁇ m ⁇ 290 ⁇ m, a device mesa size of 250 ⁇ m ⁇ 250 ⁇ m, and a device p-electrode size of 240 ⁇ m ⁇ 240 ⁇ m. Accordingly, at a drive current of 20 mA, the device is supporting a current density of 0.347 ⁇ A/ ⁇ m 2 . The devices were run in constant current mode at 20 mA and output power was measured periodically. At 1000 hours, degradation of 10-20% is observed.
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Also Published As
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WO2006130392A1 (en) | 2006-12-07 |
DE112006001360T5 (en) | 2008-04-17 |
TW200703722A (en) | 2007-01-16 |
JP2008543056A (en) | 2008-11-27 |
US20060267043A1 (en) | 2006-11-30 |
US20080142783A1 (en) | 2008-06-19 |
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