JP2000122864A5 - - Google Patents

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Publication number
JP2000122864A5
JP2000122864A5 JP1999288062A JP28806299A JP2000122864A5 JP 2000122864 A5 JP2000122864 A5 JP 2000122864A5 JP 1999288062 A JP1999288062 A JP 1999288062A JP 28806299 A JP28806299 A JP 28806299A JP 2000122864 A5 JP2000122864 A5 JP 2000122864A5
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JP
Japan
Prior art keywords
data processing
instruction
processing
type
executed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1999288062A
Other languages
English (en)
Japanese (ja)
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JP2000122864A (ja
Filing date
Publication date
Priority claimed from US09/170,690 external-priority patent/US6418527B1/en
Application filed filed Critical
Publication of JP2000122864A publication Critical patent/JP2000122864A/ja
Publication of JP2000122864A5 publication Critical patent/JP2000122864A5/ja
Pending legal-status Critical Current

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JP11288062A 1998-10-13 1999-10-08 デ―タ処理システムおよび集合化を用いた命令システム Pending JP2000122864A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/170,690 US6418527B1 (en) 1998-10-13 1998-10-13 Data processor instruction system for grouping instructions with or without a common prefix and data processing system that uses two or more instruction grouping methods
US170690 1998-10-13

Publications (2)

Publication Number Publication Date
JP2000122864A JP2000122864A (ja) 2000-04-28
JP2000122864A5 true JP2000122864A5 (enExample) 2006-11-16

Family

ID=22620876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11288062A Pending JP2000122864A (ja) 1998-10-13 1999-10-08 デ―タ処理システムおよび集合化を用いた命令システム

Country Status (10)

Country Link
US (1) US6418527B1 (enExample)
EP (1) EP0994413B1 (enExample)
JP (1) JP2000122864A (enExample)
KR (1) KR100690225B1 (enExample)
CN (1) CN1129843C (enExample)
AT (1) ATE266226T1 (enExample)
DE (1) DE69916962T2 (enExample)
ES (1) ES2221282T3 (enExample)
SG (1) SG95605A1 (enExample)
TW (1) TW497073B (enExample)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1039375A1 (en) * 1999-03-19 2000-09-27 Motorola, Inc. Method and apparatus for implementing zero overhead loops
US6606700B1 (en) * 2000-02-26 2003-08-12 Qualcomm, Incorporated DSP with dual-mac processor and dual-mac coprocessor
EP1261910A2 (en) * 2000-03-08 2002-12-04 Sun Microsystems, Inc. Vliw computer processing architecture having a scalable number of register files
US6725360B1 (en) * 2000-03-31 2004-04-20 Intel Corporation Selectively processing different size data in multiplier and ALU paths in parallel
US7010788B1 (en) * 2000-05-19 2006-03-07 Hewlett-Packard Development Company, L.P. System for computing the optimal static schedule using the stored task execution costs with recent schedule execution costs
GB2366643B (en) * 2000-05-25 2002-05-01 Siroyan Ltd Methods of compressing instructions for processors
US6415376B1 (en) * 2000-06-16 2002-07-02 Conexant Sytems, Inc. Apparatus and method for issue grouping of instructions in a VLIW processor
US6877084B1 (en) * 2000-08-09 2005-04-05 Advanced Micro Devices, Inc. Central processing unit (CPU) accessing an extended register set in an extended register mode
KR20040064713A (ko) * 2001-11-26 2004-07-19 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 프로세서, 인스트럭션 세트, 인스트럭션 분배 방법 및컴파일링 방법
US7697946B2 (en) * 2002-06-04 2010-04-13 Forster Ian J Reflective communication using radio-frequency devices
JP3627725B2 (ja) * 2002-06-24 2005-03-09 セイコーエプソン株式会社 情報処理装置及び電子機器
US6944749B2 (en) * 2002-07-29 2005-09-13 Faraday Technology Corp. Method for quickly determining length of an execution package
US6865662B2 (en) * 2002-08-08 2005-03-08 Faraday Technology Corp. Controlling VLIW instruction operations supply to functional units using switches based on condition head field
CN1809810B (zh) * 2003-06-25 2010-06-09 皇家飞利浦电子股份有限公司 指令控制数据处理设备
US7340588B2 (en) * 2003-11-24 2008-03-04 International Business Machines Corporation Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
US7873815B2 (en) 2004-03-04 2011-01-18 Qualcomm Incorporated Digital signal processors with configurable dual-MAC and dual-ALU
US20060149926A1 (en) * 2004-12-23 2006-07-06 Yuval Sapir Control words for instruction packets of processors and methods thereof
US20060150171A1 (en) * 2004-12-28 2006-07-06 Ceva D.S.P. Ltd. Control words for instruction packets of processors and methods thereof
US20060149922A1 (en) * 2004-12-28 2006-07-06 Ceva D.S.P. Ltd. Multiple computational clusters in processors and methods thereof
US7350040B2 (en) * 2005-03-03 2008-03-25 Microsoft Corporation Method and system for securing metadata to detect unauthorized access
US7526633B2 (en) * 2005-03-23 2009-04-28 Qualcomm Incorporated Method and system for encoding variable length packets with variable instruction sizes
US7793078B2 (en) * 2005-04-01 2010-09-07 Arm Limited Multiple instruction set data processing system with conditional branch instructions of a first instruction set and a second instruction set sharing a same instruction encoding
JP5217431B2 (ja) * 2007-12-28 2013-06-19 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US8407680B2 (en) * 2008-12-16 2013-03-26 International Business Machines Corporation Operand data structure for block computation
US8327345B2 (en) * 2008-12-16 2012-12-04 International Business Machines Corporation Computation table for block computation
US8281106B2 (en) * 2008-12-16 2012-10-02 International Business Machines Corporation Specifying an addressing relationship in an operand data structure
US8458439B2 (en) * 2008-12-16 2013-06-04 International Business Machines Corporation Block driven computation using a caching policy specified in an operand data structure
US8285971B2 (en) * 2008-12-16 2012-10-09 International Business Machines Corporation Block driven computation with an address generation accelerator
GB2486737B (en) * 2010-12-24 2018-09-19 Qualcomm Technologies Int Ltd Instruction execution
GB2565242B (en) * 2010-12-24 2019-04-03 Qualcomm Technologies Int Ltd Encapsulated instruction set
WO2012131437A1 (en) * 2011-03-30 2012-10-04 Freescale Semiconductor, Inc. Integrated circuit device and method for enabling cross-context access
US8898433B2 (en) * 2012-04-26 2014-11-25 Avago Technologies General Ip (Singapore) Pte. Ltd. Efficient extraction of execution sets from fetch sets
KR102210997B1 (ko) * 2014-03-12 2021-02-02 삼성전자주식회사 Vliw 명령어를 처리하는 방법 및 장치와 vliw 명령어를 처리하기 위한 명령어를 생성하는 방법 및 장치
US9940242B2 (en) * 2014-11-17 2018-04-10 International Business Machines Corporation Techniques for identifying instructions for decode-time instruction optimization grouping in view of cache boundaries
US9733940B2 (en) 2014-11-17 2017-08-15 International Business Machines Corporation Techniques for instruction group formation for decode-time instruction optimization based on feedback
US10402199B2 (en) * 2015-10-22 2019-09-03 Texas Instruments Incorporated Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor
US20170192788A1 (en) * 2016-01-05 2017-07-06 Intel Corporation Binary translation support using processor instruction prefixes
CN107688854B (zh) * 2016-08-05 2021-10-19 中科寒武纪科技股份有限公司 一种能支持不同位宽运算数据的运算单元、方法及装置
US10761849B2 (en) * 2016-09-22 2020-09-01 Intel Corporation Processors, methods, systems, and instruction conversion modules for instructions with compact instruction encodings due to use of context of a prior instruction
CN111813446A (zh) * 2019-04-12 2020-10-23 杭州中天微系统有限公司 一种数据加载和存储指令的处理方法和处理装置
WO2023146519A1 (en) * 2022-01-26 2023-08-03 Google Llc Parallel decode instruction set computer architecture with variable-length instructions

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0827716B2 (ja) * 1985-10-25 1996-03-21 株式会社日立製作所 データ処理装置及びデータ処理方法
EP0221577B1 (en) * 1985-11-08 1996-01-17 Nec Corporation Microprogram control unit
EP0454985B1 (en) * 1990-05-04 1996-12-18 International Business Machines Corporation Scalable compound instruction set machine architecture
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
JPH04156613A (ja) * 1990-10-20 1992-05-29 Fujitsu Ltd 命令バッファ装置
EP0651321B1 (en) * 1993-10-29 2001-11-14 Advanced Micro Devices, Inc. Superscalar microprocessors
US5689672A (en) * 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
EP0651320B1 (en) * 1993-10-29 2001-05-23 Advanced Micro Devices, Inc. Superscalar instruction decoder
EP0652510B1 (en) 1993-11-05 2000-01-26 Intergraph Corporation Software scheduled superscalar computer architecture
DE69430018T2 (de) * 1993-11-05 2002-11-21 Intergraph Corp., Huntsville Befehlscachespeicher mit assoziativem Kreuzschienenschalter
US5630083A (en) * 1994-03-01 1997-05-13 Intel Corporation Decoder for decoding multiple instructions in parallel
US5822778A (en) * 1995-06-07 1998-10-13 Advanced Micro Devices, Inc. Microprocessor and method of using a segment override prefix instruction field to expand the register file
JPH09265397A (ja) * 1996-03-29 1997-10-07 Hitachi Ltd Ｖｌｉｗ命令用プロセッサ
US6275927B2 (en) * 1998-09-21 2001-08-14 Advanced Micro Devices. Compressing variable-length instruction prefix bytes

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