KR100690225B1 - 데이터 처리기 시스템 및 그룹화를 이용한 명령 시스템 - Google Patents

데이터 처리기 시스템 및 그룹화를 이용한 명령 시스템 Download PDF

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Publication number
KR100690225B1
KR100690225B1 KR1019990044023A KR19990044023A KR100690225B1 KR 100690225 B1 KR100690225 B1 KR 100690225B1 KR 1019990044023 A KR1019990044023 A KR 1019990044023A KR 19990044023 A KR19990044023 A KR 19990044023A KR 100690225 B1 KR100690225 B1 KR 100690225B1
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instruction
prefix
field
command
word
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KR1019990044023A
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Korean (ko)
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KR20000029005A (ko
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로젠세인즈비카
토카야콥
데이얀우리
저젼죠폴
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프리스케일 세미컨덕터, 인크.
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Electrophonic Musical Instruments (AREA)
KR1019990044023A 1998-10-13 1999-10-12 데이터 처리기 시스템 및 그룹화를 이용한 명령 시스템 Expired - Fee Related KR100690225B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US9/170,690 1998-10-13
US09/170,690 US6418527B1 (en) 1998-10-13 1998-10-13 Data processor instruction system for grouping instructions with or without a common prefix and data processing system that uses two or more instruction grouping methods
US09/170,690 1998-10-13

Publications (2)

Publication Number Publication Date
KR20000029005A KR20000029005A (ko) 2000-05-25
KR100690225B1 true KR100690225B1 (ko) 2007-03-12

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US (1) US6418527B1 (enExample)
EP (1) EP0994413B1 (enExample)
JP (1) JP2000122864A (enExample)
KR (1) KR100690225B1 (enExample)
CN (1) CN1129843C (enExample)
AT (1) ATE266226T1 (enExample)
DE (1) DE69916962T2 (enExample)
ES (1) ES2221282T3 (enExample)
SG (1) SG95605A1 (enExample)
TW (1) TW497073B (enExample)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1039375A1 (en) * 1999-03-19 2000-09-27 Motorola, Inc. Method and apparatus for implementing zero overhead loops
US6606700B1 (en) * 2000-02-26 2003-08-12 Qualcomm, Incorporated DSP with dual-mac processor and dual-mac coprocessor
WO2001067234A2 (en) * 2000-03-08 2001-09-13 Sun Microsystems, Inc. Vliw computer processing architecture having a scalable number of register files
US6725360B1 (en) * 2000-03-31 2004-04-20 Intel Corporation Selectively processing different size data in multiplier and ALU paths in parallel
US7010788B1 (en) * 2000-05-19 2006-03-07 Hewlett-Packard Development Company, L.P. System for computing the optimal static schedule using the stored task execution costs with recent schedule execution costs
GB2362733B (en) 2000-05-25 2002-02-27 Siroyan Ltd Processors having compressed instructions.
US6415376B1 (en) * 2000-06-16 2002-07-02 Conexant Sytems, Inc. Apparatus and method for issue grouping of instructions in a VLIW processor
US6877084B1 (en) * 2000-08-09 2005-04-05 Advanced Micro Devices, Inc. Central processing unit (CPU) accessing an extended register set in an extended register mode
EP1451678B1 (en) * 2001-11-26 2012-04-18 Nytell Software LLC Vliw architecture with power down instruction
US7697946B2 (en) * 2002-06-04 2010-04-13 Forster Ian J Reflective communication using radio-frequency devices
JP3627725B2 (ja) * 2002-06-24 2005-03-09 セイコーエプソン株式会社 情報処理装置及び電子機器
US6944749B2 (en) * 2002-07-29 2005-09-13 Faraday Technology Corp. Method for quickly determining length of an execution package
US6865662B2 (en) * 2002-08-08 2005-03-08 Faraday Technology Corp. Controlling VLIW instruction operations supply to functional units using switches based on condition head field
CN1809810B (zh) * 2003-06-25 2010-06-09 皇家飞利浦电子股份有限公司 指令控制数据处理设备
US7340588B2 (en) * 2003-11-24 2008-03-04 International Business Machines Corporation Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
US7873815B2 (en) * 2004-03-04 2011-01-18 Qualcomm Incorporated Digital signal processors with configurable dual-MAC and dual-ALU
US20060149926A1 (en) * 2004-12-23 2006-07-06 Yuval Sapir Control words for instruction packets of processors and methods thereof
US20060150171A1 (en) * 2004-12-28 2006-07-06 Ceva D.S.P. Ltd. Control words for instruction packets of processors and methods thereof
US20060149922A1 (en) * 2004-12-28 2006-07-06 Ceva D.S.P. Ltd. Multiple computational clusters in processors and methods thereof
US7350040B2 (en) * 2005-03-03 2008-03-25 Microsoft Corporation Method and system for securing metadata to detect unauthorized access
US7526633B2 (en) * 2005-03-23 2009-04-28 Qualcomm Incorporated Method and system for encoding variable length packets with variable instruction sizes
US7793078B2 (en) * 2005-04-01 2010-09-07 Arm Limited Multiple instruction set data processing system with conditional branch instructions of a first instruction set and a second instruction set sharing a same instruction encoding
JP5217431B2 (ja) * 2007-12-28 2013-06-19 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US8327345B2 (en) * 2008-12-16 2012-12-04 International Business Machines Corporation Computation table for block computation
US8285971B2 (en) * 2008-12-16 2012-10-09 International Business Machines Corporation Block driven computation with an address generation accelerator
US8407680B2 (en) * 2008-12-16 2013-03-26 International Business Machines Corporation Operand data structure for block computation
US8281106B2 (en) * 2008-12-16 2012-10-02 International Business Machines Corporation Specifying an addressing relationship in an operand data structure
US8458439B2 (en) * 2008-12-16 2013-06-04 International Business Machines Corporation Block driven computation using a caching policy specified in an operand data structure
GB2565242B (en) * 2010-12-24 2019-04-03 Qualcomm Technologies Int Ltd Encapsulated instruction set
GB2486737B (en) 2010-12-24 2018-09-19 Qualcomm Technologies Int Ltd Instruction execution
US20140019990A1 (en) * 2011-03-30 2014-01-16 Freescale Semiconductor, Inc. Integrated circuit device and method for enabling cross-context access
US8898433B2 (en) * 2012-04-26 2014-11-25 Avago Technologies General Ip (Singapore) Pte. Ltd. Efficient extraction of execution sets from fetch sets
KR102210997B1 (ko) * 2014-03-12 2021-02-02 삼성전자주식회사 Vliw 명령어를 처리하는 방법 및 장치와 vliw 명령어를 처리하기 위한 명령어를 생성하는 방법 및 장치
US9733940B2 (en) 2014-11-17 2017-08-15 International Business Machines Corporation Techniques for instruction group formation for decode-time instruction optimization based on feedback
US9940242B2 (en) * 2014-11-17 2018-04-10 International Business Machines Corporation Techniques for identifying instructions for decode-time instruction optimization grouping in view of cache boundaries
US10402199B2 (en) 2015-10-22 2019-09-03 Texas Instruments Incorporated Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor
US20170192788A1 (en) * 2016-01-05 2017-07-06 Intel Corporation Binary translation support using processor instruction prefixes
CN107688854B (zh) * 2016-08-05 2021-10-19 中科寒武纪科技股份有限公司 一种能支持不同位宽运算数据的运算单元、方法及装置
US10761849B2 (en) * 2016-09-22 2020-09-01 Intel Corporation Processors, methods, systems, and instruction conversion modules for instructions with compact instruction encodings due to use of context of a prior instruction
CN111813446A (zh) * 2019-04-12 2020-10-23 杭州中天微系统有限公司 一种数据加载和存储指令的处理方法和处理装置
JP7642849B2 (ja) * 2022-01-26 2025-03-10 グーグル エルエルシー 可変長の命令を用いた並列復号命令セットコンピュータアーキテクチャ

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5475853A (en) * 1990-05-10 1995-12-12 International Business Machines Corporation Cache store of instruction pairs with tags to indicate parallel execution
US5560028A (en) * 1993-11-05 1996-09-24 Intergraph Corporation Software scheduled superscalar computer architecture

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0827716B2 (ja) * 1985-10-25 1996-03-21 株式会社日立製作所 データ処理装置及びデータ処理方法
US4907192A (en) * 1985-11-08 1990-03-06 Nec Corporation Microprogram control unit having multiway branch
ATE146611T1 (de) * 1990-05-04 1997-01-15 Ibm Maschinenarchitektur für skalaren verbundbefehlssatz
JPH04156613A (ja) * 1990-10-20 1992-05-29 Fujitsu Ltd 命令バッファ装置
EP0651321B1 (en) * 1993-10-29 2001-11-14 Advanced Micro Devices, Inc. Superscalar microprocessors
US5689672A (en) * 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
EP0651320B1 (en) * 1993-10-29 2001-05-23 Advanced Micro Devices, Inc. Superscalar instruction decoder
EP0974894B1 (en) * 1993-11-05 2002-02-27 Intergraph Corporation Instruction cache associative cross-bar switch
US5630083A (en) * 1994-03-01 1997-05-13 Intel Corporation Decoder for decoding multiple instructions in parallel
US5822778A (en) * 1995-06-07 1998-10-13 Advanced Micro Devices, Inc. Microprocessor and method of using a segment override prefix instruction field to expand the register file
JPH09265397A (ja) * 1996-03-29 1997-10-07 Hitachi Ltd Ｖｌｉｗ命令用プロセッサ
US6275927B2 (en) * 1998-09-21 2001-08-14 Advanced Micro Devices. Compressing variable-length instruction prefix bytes

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5475853A (en) * 1990-05-10 1995-12-12 International Business Machines Corporation Cache store of instruction pairs with tags to indicate parallel execution
US5560028A (en) * 1993-11-05 1996-09-24 Intergraph Corporation Software scheduled superscalar computer architecture

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Publication number Publication date
ES2221282T3 (es) 2004-12-16
TW497073B (en) 2002-08-01
US20020056035A1 (en) 2002-05-09
EP0994413B1 (en) 2004-05-06
US6418527B1 (en) 2002-07-09
DE69916962D1 (de) 2004-06-09
JP2000122864A (ja) 2000-04-28
CN1129843C (zh) 2003-12-03
CN1250906A (zh) 2000-04-19
EP0994413A2 (en) 2000-04-19
KR20000029005A (ko) 2000-05-25
DE69916962T2 (de) 2005-04-07
EP0994413A3 (en) 2002-01-23
SG95605A1 (en) 2003-04-23
ATE266226T1 (de) 2004-05-15

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