JP2000112443A - Power source circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make suppressible the power consumption without degrading the display quality of a liquid crystal panel by providing V/F circuits to respective output voltages which are supplied to a liquid crystal panel and providing control circuits changing driving powers of the V/F circuits with external inputs. SOLUTION: P-channel Trs 11, 12, N-channel Trs 21, 22 and an N-channel Tr 23 constitute a differential circuit respectively as active loads, a differential pair and a current source. Moreover, an output circuit is constituted of a P- channel Tr 13 and N-channel Trs 24, 25. A reference voltage VREF 3 applies the constant voltage based on voltage divided potentials V5, V1 to control the gate potential of Trs 23, 25. The driving power of the output circuit is changed over by operating the output circuit part periodically with Tr 25 and the gate signal of Tr 25 is supplied from a timing generating circuit. The timing generating circuit is made to have a constitution in which its poetential is made to be dependent so as to able to control the output voltage and it can be arbitrarily set by a potential control circuit. Thus, this power source circuit suppresses unnecessary break-through power of the liquid crystal panel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a power supply circuit.

[0002]

2. Description of the Related Art As a peripheral component for displaying a small liquid crystal panel used in a portable device or the like, an LCD driver,
A power supply IC for a liquid crystal panel is required. In the field of portable devices and the like, low power consumption and long operation time are key, and reduction in current consumption of each component is inevitable. However, when using general-purpose components, the power consumption of the power supply section is constant regardless of the panel capacity in the power supply IC or LCD driver IC with a built-in power supply circuit. This is a problem in terms of low current consumption. FIG. 3 shows a voltage dividing circuit section and a V / F circuit section of a general liquid crystal panel driving power supply circuit. In FIG. 3, V5 voltage 2 is a voltage Vo for driving the liquid crystal panel.
p is arbitrarily set, and then, to obtain a bias ratio suitable for the liquid crystal panel, arbitrary resistors 45 to 49 are connected to the VDD voltage 1−.
Connected in series between V5 and voltage 2. For example, if Duty is 1
In the case of / 16, the general formula for calculating the Bias ratio is SQ
RT (16) + 1 = 5, so that it is sufficient to set resistance 45 = resistance 46 = resistance 47 = resistance 48 = resistance 49. At this time, since the resistors 45 to 49 are connected in series between the VDD voltage 1 and the V2 voltage 2, current is consumed. Therefore, it is desirable to increase this resistance as much as possible within a range where the next stage V / F circuit operates. Next, the potentials at the connection points of the resistors are buffered by the V / F circuits of the operational amplifiers 61 to 64, respectively. Further, by connecting the capacitors 32 to 35 between the potentials 71 to 74 and VDD1, respectively, the driving capability of the V / F circuit is suppressed, and the capacitors 32 to 3 are connected.
5 is a general structure for supplementing the current supply. In the prior art, the operational amplifier 61 in the power supply circuit described above is used.
For example, the V / F circuit of ~ 64 is devised as shown in FIG. FIG. 4 is a circuit diagram showing a conventional V / F circuit, which is of an N-channel Tr input type. In FIG. 4, P-channel Trs 11 and 12 are active loads, N-channel Tr2
Reference numerals 1 and 22 denote a differential pair, an N-channel Tr 23 forms a differential circuit as a current source, and a P-channel Tr 13 and an N-channel T
An output circuit is configured by r24, 26, and 27. V
REG voltage 3 provides a constant voltage based on V5 voltage 1 and T
The gate potentials of r23, 24 and 26 are controlled. Capacity 31
Is a frequency correction capacitor. The G1 terminal 4 is a positive-phase input terminal and provides a potential to be buffered, and the G2 terminal 5 is a negative-phase input terminal and provides an output voltage VOUT7 for negative feedback. In FIG. 4, Trs that determine the driving capability of the V / F circuit are 24 and 26. The power consumption of the liquid crystal panel occurs sharply at the point where the display data changes, and almost no power is consumed when there is no change in the display data. Therefore, the timing of the Tr 24 for constantly flowing a very small current of about 1 μA or less and the timing at the time of the change of the data which consumes the most current by the liquid crystal panel are turned on by the switch of the Tr 26 for a certain period tON at the timing of the display clock. Tr27 is added to reduce current consumption. Tr
The current consumption of 26 differs depending on the specifications of the IC, but is designed to be several tens μA or more as a general drive current. In addition, Tr2
The gate potential of 7 is designed so that the ON resistance of Tr27 is sufficiently smaller than that of Tr26. The certain period tON is:
For example, it is generated by a circuit as shown in FIG. In FIG. 5, an output of a delay element DL66 that captures a change point of a signal obtained by inverting a signal CL9, which is a data change timing, by an inverter 65 and the output of the delay element DL66 are taken, so that DCL is obtained only for the delay period of the inverter 65 + DL element 66. The output pulse width 6 is generated. FIG. 6 shows a timing waveform in each part of the timing generation circuit shown in FIG. In FIG. 6, only during the HIGH period of the DCL signal 9,
Tr27 in FIG. 4 operates. In addition, by connecting capacitors 32 to 35 between the output units 71 to 74 of the operational amplifiers 61 to 64 and the VDD voltage 1, respectively, V /
The driving capability of the F circuit is suppressed as much as possible, and a load exceeding the capability of the V / F circuit is compensated by the charges charged in the capacitors 32 to 35, thereby suppressing the display deterioration of the liquid crystal panel.

[0003]

In the above-mentioned conventional method, the driving capability of the V / F circuit is designed to be fixed and large in a general-purpose power supply IC. The current consumption is constant. If the driving capability of the V / F circuit is excessive with respect to the panel capacity due to the small size of the liquid crystal panel or the like, there is a problem that current is wasted unnecessarily. SUMMARY OF THE INVENTION An object of the present invention is to provide a power supply circuit in which the driving capability of a V / F circuit is arbitrarily set in accordance with the capacity of a liquid crystal panel after manufacturing an IC, thereby suppressing current consumption without deteriorating display quality of the liquid crystal panel. It is in.

[0004]

A driving IC for displaying a liquid crystal panel has a V / F circuit for each output voltage supplied to the liquid crystal panel, and the driving capability of the V / F circuit is controlled by an external input. A power supply circuit comprising a control circuit for changing. The power supply circuit further includes a circuit that controls the potential of an operation pulse of the V / F circuit as control of the driving capability of the V / F circuit.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a power supply control circuit of a power supply for driving a liquid crystal panel according to the present invention will be described with reference to the accompanying drawings. FIG. 1 shows an embodiment of a drive capability switching circuit of a V / F circuit of a power supply control circuit according to the present invention. 1, the circuit configuration is substantially the same as that of the conventional embodiment shown in FIG.
The difference between FIG. 4 and FIG. 4 is that the configuration of the N-channel Tr 26 and the N-channel Tr 27 for switching the driving capability by periodically operating the output circuit unit is replaced by only one N-channel Tr 25, and this gate signal Is supplied from the timing generation circuit shown in FIG. The timing generation circuit has a structure in which the potential is made independent so that the output voltage can be controlled, and can be arbitrarily set by, for example, a potential control circuit shown in FIG. In FIG.
The resistance elements 41 to 44 are connected in series between VREG-V5, an intermediate potential between the respective resistors is drawn out, each is connected to one end of switches 51 to 54, and the other switch 51 to 54 is commonly used for the power supply output Va8. Connecting. Here, the switches 51 to 54 are selected and controlled by an arbitrary external setting. VREG in FIG.
3 may be a VDD voltage 1, and the resistance elements of the resistors 41 to 44 may be polysilicon or Tr ON resistors or the like, and the resistances of the resistors 41 to 44 may be arbitrarily set at the design stage without being equal. An arbitrary voltage Va8 can be obtained depending on the mode of each switch. By setting the voltage Va8 and operating the timing generation circuit shown in FIG. 5,
The gate voltage of Tr25 in FIG. 1 is controlled to change the output capability of the V / F circuit. In FIG. 5, Tr driven by the voltage Va8 may be only the NAND circuit 67 of the output unit instead of the entire timing generation circuit. When the entire timing generation circuit is controlled by the voltage Va8, the delay time of the DL element 66 slightly changes, so that it is necessary to consider it at the time of design. However, by driving only the NAND circuit 67 with the power supply Va8, the DELAY values of the delay circuits 66 and 65 when the voltage Va8 is changed become constant. In the above description, an N-channel Tr input V / F circuit has been described, but the same applies to a P-channel Tr input V / F circuit. As described above, in the present embodiment, by controlling the gate voltage of the driving Tr that operates at the timing of displaying the liquid crystal panel, an arbitrary driving capability suitable for the liquid crystal panel can be set, and the current consumption can be minimized. Can be suppressed. Further, a through current is generated during the operation of the Tr 25, but the through current can be suppressed by optimizing the capability of the Tr 25.

[0006]

As described above, according to the present invention, the driving capability of the power supply circuit can be optimally set by the user after IC production without changing the design of the IC for a wide range of liquid crystal panel sizes. It is possible to provide a power supply circuit for a liquid crystal panel which suppresses a through current and consumes no current without deteriorating display quality.

[Brief description of the drawings]

FIG. 1 is a V / F circuit diagram of the present embodiment.

FIG. 2 is a power supply control circuit diagram for a timing generation circuit according to the embodiment.

FIG. 3 is a power supply circuit diagram of a conventional liquid crystal panel power supply.

FIG. 4 is a V / F circuit diagram of a conventional liquid crystal panel power supply circuit.

FIG. 5 is a timing generation circuit diagram.

FIG. 6 is a timing chart of a timing generation circuit.

[Explanation of symbols]

1 is a VDD ground, 71 is a divided potential V1, 72 is a divided potential V2, 73 is a divided potential V3, 74 is a divided potential V4,
2 is a divided potential V5, 3 is a reference potential VREG, 4 is a positive phase input terminal G1, 5 is a negative phase input terminal G2, 6 is a gate control signal DCL generated from CL, 7 is an output potential VOUT, 8
Is a power supply potential Va for the timing generation circuit, 9 is a clock CL for liquid crystal display, 11 to 13 are P-channel Trs, 21 to 2
7 is an N-channel Tr, 31 is a frequency correction capacitor, and 32 to
35 is a power auxiliary capacitor, 41 to 44 are resistors for dividing the power supply potential Va for the timing generation circuit, and 45 to 48 are Bias.
Setting resistors 51 to 54 are switches, 61 to 64 are voltage follower circuits, 65 is an inverter circuit, 66 is a delay circuit, and 67 is a two-input AND.

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Claims (1)

[Claims] A voltage follower (hereinafter, referred to as V / F) circuit comprising a differential circuit section and an output circuit section, wherein the output section of the V / F circuit operates periodically with a circuit in which the output section always operates. In the power supply circuit configured by the
A power supply circuit having a circuit for controlling the potential of a control signal for periodically operating an output circuit of an F circuit, wherein the control circuit is set by an external input.