JP3175983B2 - Constant voltage generating circuit and semiconductor integrated circuit device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant voltage generating circuit and a semiconductor integrated circuit device using the same, and more particularly to a constant voltage generating circuit and a semiconductor integrated circuit device suitable for a driver circuit for driving a liquid crystal panel or the like. About.

[0002]

2. Description of the Related Art FIG. 19 is a schematic diagram of a conventional constant voltage generating circuit. As shown in FIG. 19, the constant voltage circuit 16 includes the operational amplifier 12 as an impedance converter. Further, the resistance between the high-potential power supply VDD and the low-potential ground GND is divided by two resistors RA and RB, and the reference potential V
B is generated. A potential VB generated by the resistors RA and RB is applied to an operational amplifier 1 called a voltage follower type.
2 positive input terminal. The operational amplifier 12 negatively feeds back its own output voltage VB 'to its negative input terminal.

According to the above configuration, the potential VB is
The impedance is converted by the operational amplifier 12, and the same voltage is sent out as an output voltage VB 'to another circuit (not shown).

The output voltage VB 'obtained as described above
Is supplied to another circuit as a constant voltage, the operational amplifier 1
2 lowers the impedance. Therefore, it is possible to realize a large current driving capability that cannot be obtained only by the resistance division.

In a drive power supply for a liquid crystal panel or the like,
A large number of such constant voltage generating circuits are arranged to drive a liquid crystal panel serving as a capacitive load.

FIG. 22 is a circuit block diagram of a conventional liquid crystal driving power supply. As shown in FIG.
In order to supply a potential to the segment / common capacitive load CS of the liquid crystal panel, a drive circuit 100 and a plurality of output units 102 provided corresponding to each load CS are provided. The driving circuit 100 includes a voltage dividing circuit 105 and an operational amplifier circuit 109. The operational amplifier circuit 109 includes a plurality of operational amplifiers 10.
4 The voltage dividing circuit 105 divides the liquid crystal high potential VDD and the liquid crystal low potential VEE by the resistors R1 to R6 to generate potentials V1 to V5. Each of the potentials V1 to V5 is supplied to a plurality of operational amplifiers 104 of the operational amplifier circuit 109. The operational amplifier 104 receives the input potentials V1 to V5
Are set to the same potentials V1 'to V5' as the power supply wiring 1
Send to 03. Power supply wiring 103 is high potential VDD for liquid crystal
And potentials V1 'to V5'. Potential V
Capacitors C1 to C5 are connected to the wiring 103 where 1 'to V5' appear. The liquid crystal high potential VDD selected by the transfer gate 108 based on the selection signals S0 to S5.
And one of the potentials V1 'to V5' is the high potential V
DD ", output voltages V1", V2 ", V3", V4 ", V
5 ″ is supplied to the segment / common capacitive load CS via the external connection terminal 101. The operational amplifier 10
4 is supplied with either the voltage VN or VP from the operational amplifier reference power supply circuit 106.

FIG. 23 is a circuit diagram showing a specific configuration example of the operational amplifier reference power supply circuit 106 in FIG.
As shown in the drawing, a P-type MOS transistor 17, a resistor RC, and an N-type MOS transistor 18 are connected in series between the liquid crystal high potential VDD and the liquid crystal low potential VEE. MOS transistor 17 and N-type MOS
Each of the transistors 18 has a drain and a gate connected. Then, the voltage VP and the voltage VN are derived from both ends of the resistor RC.

FIG. 20 shows an operational amplifier 104 shown in FIG.
FIG. 2 is a circuit diagram showing a specific configuration example of FIG. 1, particularly illustrating a P-top type circuit. As shown in the figure, the voltage VP is applied between the gate of the P-type MOS transistor 30 and the P-type M transistor.
It is supplied to the gate of the OS transistor 35. The voltage V5 is supplied to the gate of the P-type MOS transistor 31. The sources of the P-type MOS transistors 30 and 35 are connected to the liquid crystal high potential VDD. Further, the drain of the P-type MOS transistor 30 is
1, 32 sources. The sources of the N-type MOS transistors 33, 34, 36 are connected to the liquid crystal low potential VEE. The gates of the N-type MOS transistors 33 and 34 are commonly connected, and are connected to a connection point between the drain of the P-type MOS transistor 32 and the drain of the N-type MOS transistor 34. P-type MOS transistor 31 and N-type M
The drains of the OS transistors 33 are connected to each other, and the connection point is connected to the gate of the N-type MOS transistor 36. The drain of the P-type MOS transistor 35 and the drain of the N-type MOS transistor 36 are connected to each other,
An output voltage V5 'is output from the connection point. This output voltage V5 'is fed back to the gate of the P-type MOS transistor 32. P-type MOS transistor 32
And a gate of the N-type MOS transistor 36, a phase compensation capacitor CP for preventing oscillation of the operational amplifier is connected. This capacitor may not be provided.

FIG. 21 is a circuit diagram showing another example of the operational amplifier 104 in the configuration shown in FIG. 22, particularly illustrating an N-top type circuit. As shown in FIG.
N is the gate of the N-type MOS transistor 70 and the N-type MOS
The signal is supplied to the gate of the S transistor 75. The voltage V1 is supplied to the gate of the N-type MOS transistor 71. N
The sources of the type MOS transistors 70 and 75 are connected to the liquid crystal low potential VEE. The drain of the N-type MOS transistor 70 is connected to the sources of the N-type MOS transistors 71 and 72. P-type MOS transistors 73, 74, 7
The source 6 is connected to the liquid crystal high potential VDD. P type M
The gates of the OS transistors 73 and 74 are commonly connected, and the drain of the N-type MOS transistor 72 and the P-type
Connected to the drain connection point of S transistor 74.
The drain of the N-type MOS transistor 71 and the drain of the P-type MOS transistor 73 are connected.
It is connected to the gate of the type MOS transistor 76. The drain of the N-type MOS transistor 75 and the drain of the P-type MOS transistor 76 are connected, and an output voltage V1 'is output from the connection point. This output voltage V1 'is N
The signal is fed back to the gate of the type MOS transistor 72. Gate of N-type MOS transistor 72 and P-type MO
A capacitor CN is connected between the gates of the S transistors 76 for phase compensation for preventing oscillation of the operational amplifier.

Whether the circuit of FIG. 20 is used as the operational amplifier 104 or the circuit of FIG.
1, V2, V3, V4, V5 and the characteristics of the amplifier. In the operational amplifier circuit 109, the operational amplifier 104
20 and FIG. 21 are mixed.

In the configuration described above, in the voltage dividing circuit 105 in the drive circuit 100, resistors R1 to R6 are provided in series between the high potential VDD for the liquid crystal and the low potential VEE for the liquid crystal, Potential VDD for liquid crystal and low potential VEE for liquid crystal
Are divided by resistance to obtain potentials V1 to V5. Each of these voltages V1 to V5 is input to each operational amplifier 104. As shown in FIGS. 20 and 21, the operational amplifier 104 has a configuration generally known as a voltage follower type configured to feed back each output to one terminal. That is, the inputted potentials V1 to V5 are changed to the potentials V1 'to V1 of the same voltage.
The impedance is converted as it is at 5 'and supplied to the power supply wiring 103. The potentials V1 to V5 and the potentials V1 'to V5' have the same voltage but different current supply capabilities. That is, the current supply capability of the potentials V1 to V5 is determined by the resistance values of the resistors R1 to R6 constituting the voltage dividing circuit 105. On the other hand, in the latter, a larger output current can be obtained because the current supply capability of the potentials V1 'to V5' is determined by the current supply capability of the operational amplifier 104. As a result, the power supply wiring 103 receiving the output current of the operational amplifier 104 and the output unit 102 are connected to the external segment / common capacitive load CS.
The load driving ability to the load increases. The liquid crystal high potential VDD and the obtained potentials V1 'to V5' are selected in the output unit 102 based on the selection signals S0 to S5, and supplied to the segment / common capacitive load CS via the external connection terminal 101. . As a result, the load CS is charged and discharged to a predetermined voltage.

FIG. 24 is a timing chart for explaining the operation of the configuration of FIG. In the figure, (A)
Is the selection signal S1, (B) is the selection signal S4, (C) is the selection signal S5, (D) is the operational amplifier current IOP flowing through the operational amplifier 104, and (E) is the external connection terminal 1 of the output unit 102.
The voltage applied to the segment / common capacitive load CS from 01 is shown.

As shown in FIG. 24, selection signals S1, S
When S4 and S5 are sequentially input, the external connection terminal 101 of FIG. 22 corresponds to each of the selection signals S1, S4, and S5.
The potentials V1 ", V4", V5 ", V1" are sequentially output. At this time, the segment / common capacitive load CS connected to the external connection terminal 101 is charged and discharged to these potentials. In this case, the operational amplifier section current IOP flows through the operational amplifier 104 in FIG. As a result, the segment / common capacitive load CS which is a load constituting the liquid crystal panel is driven.

[0014]

Since the conventional power supply for driving a liquid crystal is configured as described above, there is a drawback that the power consumption is large as described below. For example, as can be seen from FIG. 24, the output V1 'from the operational amplifier 104 (1)
, The voltage V1 ″ is output from the selected external connection terminal 101 to the segment / common capacitive load CS via the transfer gate 108 (1) by the selection signal S1. It is assumed that an output V4 ″ based on the output V4 ′ from another operational amplifier 104 (4) is output after the time Tf. Similarly, it is assumed that the output changes from the output V5 "to the output V1" after the time Tr. During these times Tf and Tr, the operational amplifier current IOP must continue to flow in order to drive the load. Conversely, while the voltage such as the voltage potential V4 'does not change and the output of the same voltage value continues to be output. The time Ts is also the operational amplifier current IOP
Keeps flowing. This current flowing during these unnecessary periods is not negligible and causes an increase in power consumption. On the other hand, in the case of a large liquid crystal panel or the like, the number and capacity of the segment / common capacitive loads CS increase. Therefore, the time Tf and the time Tr need to be long, and the time Tf and the time Tr need to be short. For this purpose, the operational amplifier 1
04, which is a current constantly flowing through the operational amplifier section IO
As a result, P must be increased, resulting in further increase in power consumption.

On the other hand, the potential V output from the voltage dividing circuit 105
A method is also conceivable in which 1 to V5 are directly connected to the potentials V1 'to V5', the operational amplifier 104 requiring the operational amplifier current IOP is eliminated, and the current is reduced. That is, the resistors R1 to R6
, The output impedance dance of the potentials V1 to V5 is lowered and the segment /
The output current supplied to the common capacitive load CS can be increased. However, in the case of a semiconductor integrated circuit, if the resistances R1 to R6 are made too small, manufacturing variations will increase. Further, if the resistances R1 to R6 are made of a thin P-type or N-type diffusion resistance layer, etc. Receives substrate modulation effect and the like. For this reason, for example, there is a problem in that even if the resistance R1 is as expected, the resistance R6 has an abnormally large value. That is, it is difficult to properly manage the resistance value and properly maintain the accuracy of the potentials V1 to V5. To eliminate this, it is only necessary to increase the resistance values of the resistors R1 to R6 to suppress the variation in manufacturing. However, in this case, it is inevitable that the driving capability is reduced. For this reason, the resistance value may be increased because it is a realistic choice except for the purpose of driving a small watch display liquid crystal panel that does not require much the current value and the potential accuracy of V1 to V5. I can't say. Therefore, in a large-sized liquid crystal panel having a large load capacity and a large driving capability, the operational amplifier 104 for impedance conversion is indispensable.

As shown in FIGS. 20 and 21, there are two types of operational amplifiers: a P-top type and an N-top type.

In particular, in the N-top type operational amplifier, the transistors 70 and 75 have a constant current, and the output voltage V
If 1 'fluctuates significantly higher, the output voltage V1' cannot be reduced immediately because the transistor 75 has a constant current. In order to reduce the output voltage V1 'quickly, it is necessary to use a transistor having a certain magnitude for the transistor 75 as a load driving unit, and the constant current flowing inevitably increases. Therefore, even when the output voltage V1 'is outputting a voltage equal to the input voltage V1, a large current flows through the transistor 75, and a large current is consumed.

In the P-top type operational amplifier, the transistors 30 and 35 have a constant current, and the output voltage V
If 5 'fluctuates significantly lower, the output voltage V5' cannot be quickly increased because the transistor 35 is made constant current. In order to quickly increase the output voltage V5 ', it is necessary to use a transistor having a certain magnitude for the transistor 35 as a load driving unit, and the constant current that flows inevitably increases. For this reason, even when the output voltage V5 'is outputting a voltage equal to the input voltage V5, a large current flows through the transistor 35 and consumes a large current.

In a liquid crystal panel or the like, a segment / common, which is two electrodes for determining light transmission (lighting) and non-light transmission (non-lighting) with respect to a liquid crystal, is a capacitance component when viewed from a semiconductor circuit driving this load. It is. Liquid crystal panels have become larger and larger, and the liquid crystal voltages and the segments / commons of the liquid crystal panels used for the liquid crystal panels have also increased due to the larger panels. The current consumption required to display a liquid crystal panel depends on fCV (frequency X capacitance value X voltage). For this reason, as the voltage and capacity to be used increase as the size of the liquid crystal panel increases, the current consumption further increases.

In recent years, personal computers, word processors, and the like having large liquid crystal panels have been reduced in size and become book-type. As a result, there is a problem that the battery life is short, although it is convenient to carry it anywhere. That is, there is a great demand for reducing the power consumption of the liquid crystal panel.

In response to the above requirements, when a constant voltage generating circuit as shown in FIG. 19 is constructed using an operational amplifier as shown in FIGS. 20 and 21, the transistor 35 in FIG. Since the output section of the transistor 21 and the like 21 is a constant current source, the divided potential V in the configuration of FIG.
Even if B and the output voltage VB 'are equal to each other, they have a large driving capability at all times, have a constant current, and have a drawback of increasing power consumption.

An object of the present invention is to solve the above-mentioned problems of the prior art. A constant voltage having a large driving capability is applied to a capacitive load such as a liquid crystal panel which is increasing in size and driving voltage is increasing. It is an object of the present invention to provide a constant voltage generation circuit and a semiconductor integrated circuit device which can reduce current consumption even when supplying.

[0023]

According to the present invention, there is provided a constant voltage generating circuit for converting an impedance of a first reference voltage into a second reference voltage and outputting the second reference voltage. Two reference voltages are directly input, and a comparator for inverting an output according to a first case and a second case where a difference between these two reference voltages is larger than a predetermined offset voltage; In the case of (1), switch means for controlling connection / disconnection of the second reference voltage to / from a power supply according to the output level of the comparator is configured.

[0024]

When the second reference voltage changes with respect to the first reference voltage beyond the offset voltage of the comparator, the output of the impedance conversion circuit, for example, of a relatively low impedance, is switched through the switch means. Power supply is connected. As a result, the second reference voltage is returned to the first reference voltage.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a constant voltage generating circuit device according to one embodiment of the present invention. As shown in FIG. 1, an input voltage Vin is passed through an impedance conversion circuit 1 to a voltage V which is impedance-converted to the same voltage as the input voltage Vin.
output as in '. The output of the impedance conversion circuit 1 is provided to a positive input terminal of an operational amplifier 2 that operates as a comparator. The input voltage Vin is provided to a negative input terminal of the operational amplifier 2. The operational amplifier 2 is intentionally provided with an offset. That is, the operational amplifier 2
The voltage of the positive input terminal is compared with the voltage of the negative input terminal. The output is inverted with the point at which the voltage difference becomes the voltage difference corresponding to the offset as the operating point, and the switch 3 is turned on / off. The switch 3 performs an intermittent operation between the output voltage Vin 'of the impedance conversion circuit 1 and a power supply having a voltage VA. Incidentally, the voltage VA is supplied with low impedance.

Next, the operation of the above configuration will be described.

The operational amplifier 2 is intentionally provided with an offset. This is because the input voltage Vin and the voltage Vin ′
This is to give a specific width of insensitiveness in comparing with. The operational amplifier 2 has an input voltage Vin ′ of the positive input terminal.
When a voltage difference equal to or more than the offset voltage occurs between the input voltage Vin and the input voltage Vin of the negative input terminal, a comparison operation is performed at this operating point and the switch 3 is turned on. When the switch 3 is turned on, the voltage VA is applied to the output of the impedance conversion circuit 1, and the output voltage Vin 'of the impedance conversion circuit 1 is output.
To the voltage VA side.

The impedance conversion circuit 1 receives the input voltage V
is supplied to the load as a voltage Vin 'obtained by impedance-converting "in". The output impedance of the impedance conversion circuit 1 is not set so low in order to reduce the current consumption. For this reason, when the load requires an excessive current, the voltage Vin 'naturally drops. When this voltage drop exceeds the offset given to the operational amplifier 2, the operational amplifier 2 turns on the switch 3 based on the comparison operation. As a result, the power supply VA is directly connected to the voltage Vin ', and the reduced voltage is quickly recovered.

As described above, the voltage V
The decrease in in 'is suppressed. When the voltage Vin 'recovers, this is detected by the operational amplifier 2. In response, the operational amplifier 2 turns off the switch 3 and sets the voltage Vi
The voltage VA is disconnected from n '. As a result, the voltage Vin '
Can maintain a constant voltage irrespective of a load fluctuation, and a normal operation of the load supplied with the voltage Vin ′ is ensured.

There is no need to provide a large driving capability to the output of the impedance conversion circuit 1. Therefore, low power consumption of the impedance conversion circuit 1 is possible. When the load requires a large current, the output voltage Vin 'of the impedance conversion circuit 1 decreases. The operational amplifier 2
When the voltage drop exceeds the offset, the switch 3 is turned on. In response to this, a low-impedance voltage VA is connected to the voltage Vin ', and a necessary current is supplied to the load from the voltage VA.

Incidentally, the offset provided to the operational amplifier 2 is set to a dead voltage width for preventing a malfunction due to noise or the like when the input voltage Vin and the voltage Vin 'are very close to each other.

FIG. 25 shows symbols when the operational amplifier 2 is used as a comparator. As shown in FIG. 25, the operational amplifier 2 operates to invert the output out when the + input exceeds the − input. FIG. 26 shows a circuit diagram of a P-top type MOS comparator corresponding to this symbol, and FIG. 27 shows a circuit diagram of an N-top type MOS comparator.

In FIG. 26, the gate input of the transistor 31 is positive and the gate input of the transistor 32 is negative. Transistors 30, 3
1, 32, 33, and 34 constitute a comparison unit. The comparison result is derived as an output out from a connection point (drain) between the transistors 35 and 36.

As described above, normally, the comparator includes:
As shown in FIG. 26, an output unit for deriving an output result is often provided. When the transistors 31 and 32 and the transistors 33 and 34 of the comparison unit are formed as a semiconductor circuit, W / L (gate width /
Gate length). Originally, the purpose of the comparator is to accurately compare the difference between the plus voltage input to the gate of the transistor 31 and the voltage input to the gate of the transistor 32. The accuracy of the comparison, that is, the sensitivity difference between the two input terminals is usually 1 mV or less.

However, the operational amplifier 2 shown in FIG. 1 is intentionally provided with an offset when operating as a comparator. There are several methods for providing this offset. In this regard, FIG.
A description will be given based on the circuit of FIG.

One of the methods for providing an offset is to provide a difference between the W / Ls of the transistors 31 and 32 and the transistors 31 and 33 and the transistors 32 and 3
4 and the like. An easy way to adjust the offset voltage is to provide a difference between the W / L of the transistors 31 and 32. In particular, a method of providing a difference in the gate width W while keeping the gate length L the same is effective.

Now, suppose that W / L of the transistor 31 = 1
Assume that W / L of the transistor 32 is 80 and the gate width of the transistor 31 is larger than the gate width of the transistor 32. In this case, the gate voltage 32 needs to be higher than the gate voltage 31 in order to flow the same current through the transistors 31 and 32. In other words, unless a gate input voltage VG32 higher than the gate input voltage VG31 is applied, the on-resistance of the transistor 32 will not be equal to the on-resistance of the transistor 31.

The gate input voltage VG31 of the transistor 31 and the gate input voltage VG3 of the transistor 32
When the relationship with 2 is VG31 <VG32 = VG31 + ΔVGOFF (1) (where ΔVGOFF is a desired offset voltage between input terminals as a comparator), the on-resistances of the transistors 31 and 32 and the flowing current are equal. This is the branch point where the output signal of the comparator is normal or inverted, that is, the operating point of the comparison result. Therefore, by changing the W / L of the transistors 31 and 32, the input voltage input to the comparator can have an offset of ΔVGOFF.

By making the W / L of the transistor 32 smaller than the W / L of the transistor 31, when VG31 <VG32−ΔVGOFF (2) is given, that is, VG32−VG31> ΔVGOFF. When (2 ′) is obtained, a voltage greater than the + input terminal by the predetermined offset voltage ΔVGOFF is applied to the − input terminal of the comparator, and the output out has a low level (GND level). A signal is output.

Conversely, when VG31> VG32−ΔVGOFF (3) is given to the − input terminal of the comparator as compared with the + input terminal, that is, VG32−VG31 <ΔVGOFF (3 ′) In this case, the voltage at the + input terminal is equal to the predetermined offset voltage ΔV with respect to the voltage at the − input terminal of the comparator.
Does not have a voltage difference greater than GOFF. Therefore, a high-level (VDD level) signal is output to the output out.

Conversely, W / L of transistor 31 = 80,
When the gate width of the transistor 31 is smaller than the gate width of the transistor 32 assuming that W / L of the transistor 32 is 100, the way of giving the offset voltage can be changed. At this time, the W / L of the transistor 31
Is smaller than the W / L of the transistor 32. For this reason,
If the same current as the transistor 32, that is, the same on-resistance is applied to the transistor 31, the transistor 31
Needs to add an additional voltage to the gate input voltage VG31, that is, an offset voltage ΔVGOFF.

Accordingly, when the W / L of the transistor 31 is smaller than the W / L of the transistor 32, VG31−ΔVGOFF> VG32 (4) That is, VG31> VG32−ΔVGOFF (4 ′) When the input voltage of the + input terminal becomes larger than the input voltage of the − input terminal by the offset ΔVGOFF voltage with the increase of the input voltage of the + input terminal, the comparison output out is at a high level (VDD level). Becomes

On the other hand, VG31−ΔVGOFF <VG32 (5) That is, VG31 <VG32−ΔVGOFF (5 ′), and the input voltage at the + input terminal is offset ΔVGOFF from the input voltage at the − input terminal. If the voltage does not become larger than the voltage, the comparison output out becomes low level (GND level).

That is, the offset voltage can be set by setting one of the transistors 31 and 32 to have a larger W / L than the other W / L. That is, a case where the transistor 31 is considered as a reference will be described. Transistor 3 more than W / L of transistor 31
2 is small. In this case, a voltage at which the output out switches between high and low by the comparison operation of the comparator requires a voltage corresponding to the offset ΔVGOFF on the negative input terminal side. On the other hand, the W of the transistor 31
When W / L of the transistor 32 is larger than / L,
The voltage for the comparison operation is the offset ΔV on the − input terminal side.
This means that the voltage may be lower by the voltage of GOFF.

The above is reversed when the transistor 32 is considered. W / of transistor 32
It is assumed that W / L of the transistor 31 is smaller than L. In this case, the comparator performs a comparison operation, and the voltage at which the output out switches between high and low requires a voltage higher by the offset ΔVGOFF on the + input terminal side.
W / L of transistor 32 is greater than W / L of transistor 32
When / L is large, the voltage for the comparison operation may be a voltage having a low offset ΔVGOFF on the + input terminal side.

Incidentally, the W /
Even if the magnitude of L is exchanged, the meaning of the − input terminal and the + input terminal and the polarity of the output do not change, and only the comparison operation point as the comparator changes.

In FIG. 27, the gate input of the transistor 71 is a positive input, and the gate input of the transistor 72 is a negative input. Transistors 70, 7
1, 72, 73 and 74 constitute a comparison unit. The comparison result is derived as an output out from the drains of the transistors 75 and 76.

Also in such an N-top type, the W / L of the transistor 71 is changed to the W / L of the transistor 72.
By making it larger than this, it is possible to give an offset to the voltage between the two input terminals with respect to the operating point.

That is, the gate input voltage VG71 of the transistor 71 and the gate input voltage VG of the transistor 72
In the relationship of 72, VG71 <VG72−ΔVGOFF (6) That is, VG72−VG71> ΔVGOFF (6 ′), so that the − input terminal side is more than the + input terminal side.
When a voltage at least as large as the offset voltage ΔVGOFF is applied, the output out becomes low level (GND level).

On the other hand, when the voltage difference between the negative input terminal side and the positive input terminal side is smaller than the offset voltage ΔVGOFF, VG71> VG72−ΔVGOFF (7), ie, VG72−VG71 <ΔVGOFF ( 7 '), and the output out goes high (VDD level).

Conversely, consider the case where the W / L of the transistor 71 is smaller than the W / L of the transistor 72, that is, the case where the W / L of the transistor 72 is larger than the W / L of the transistor 71. In this case, the gate input voltage Vg applied to the transistor 72 is higher than the gate input voltage VG71 applied to the transistor 71.
When G72 is given at least as higher than the offset voltage ΔVGOFF, that is, when VG71−ΔVGOFF> VG72 (8) That is, when VG71−VG72> ΔVGOFF (8 ′), the output out becomes high level (VDD). Level).

On the other hand, the gate input voltage VG71 applied to the transistor 71 is smaller than the gate input voltage VG72 applied to the transistor 72 by an offset voltage ΔVG.
If it is not larger than OFF, VG71−ΔVGOFF <VG72 (9) That is, VG72−VG71 <ΔVGOFF (9 ′), and the output out becomes low level (GND level).

That is, by making the W / L of one of the transistors 71 and 72 larger than the other, the generation of the offset voltage can be set. Considering the transistor 71 as a reference, it is as follows. That is, it is assumed that the W / L of the transistor 72 is smaller than the W / L of the transistor 71. In this case, the voltage at which the comparator performs a comparison operation and the output out switches between high and low is offset ΔVGOFF to the − input terminal side.
A minute voltage difference is required. On the other hand, it is assumed that the W / L of the transistor 72 is larger than the W / L of the transistor 71. In this case, the voltage at which the output out switches between high and low when the comparator performs the comparison operation may be such that the input voltage on the negative input terminal side is lower by the voltage difference of the offset ΔVGOFF.

Conversely, the opposite is true with reference to the transistor 72. That is, it is assumed that the W / L of the transistor 72 is larger than the W / L of the transistor 71. In this case, the comparator performs a comparison operation and outputs o.
The voltage at which ut switches between high and low may be lower on the + input terminal side by the voltage difference corresponding to the offset ΔVGOFF.
The W / L of the transistor 71 is the W / L of the transistor 72
Is smaller than In this case, a voltage at which the comparator performs a comparison operation and the output out switches between high and low is an offset ΔVGO as an input voltage on the + input terminal side.
This means that a voltage difference of FF is required.

As described above, by providing the offset voltage between the + input terminal and the − input terminal of the comparator, the voltage difference between the voltage of the + input terminal and the voltage of the − input terminal is larger than the offset voltage. In the case where the error occurs, the comparator can be operated.

FIG. 2 shows a first specific example of the configuration of FIG. A voltage follower type operational amplifier 4 is used as the impedance conversion circuit 1, and N is used as the switch 3.
Channel MOS type transistors 5 are used,
A configuration in which a GND voltage is applied as the voltage VA is illustrated. That is, theoretically, the output impedance can be almost ignored on the GND voltage side. As the operational amplifier 4, an N-top configuration as shown in FIG. 21 is applied.

As is clear from FIG. 21, the operational amplifier 4 has a voltage follower type configuration. The output is configured such that the voltage at the + input terminal is directly derived as an output voltage by negative feedback. as a result,
The input voltage Vin is the impedance-converted voltage Vi.
n '. However, there is naturally a limitation on the current driving capability for drawing current from the load. As a result, if the voltage Vin 'rises by more than the offset of the operational amplifier 2, the operational amplifier 2 inverts the output and the MOS transistor 5 is turned on.
With the turning on of the MOS transistor 5, the voltage Vin 'is lowered to the GND voltage side. Meanwhile, the load current is GND
Flowing to the side. Therefore, it is not necessary to draw an excessive current from the load to the impedance conversion circuit 1. That is, a low power consumption type configuration can be applied as the impedance conversion circuit 1.

FIG. 3 shows a second specific example of the configuration of FIG. 2 exemplifies a configuration in which a constant current source 6 is connected to a MOS transistor 5 in the configuration of FIG.

In FIG. 3, an input voltage Vin is converted into an impedance-converted voltage Vi through an operational amplifier 4.
n '. However, there is naturally a limitation on the current driving capability for drawing current from the load. As a result, if the voltage Vin 'rises by more than the offset of the operational amplifier 2, the operational amplifier 2 inverts the output and the MOS transistor 5 is turned on.
With the turning on of the MOS transistor 5, the load current flows to the constant current source 6 side. Therefore, the voltage Vin 'returns to a predetermined voltage. During that time, since the load current flows to the constant current source 6 side, it is not necessary to draw an excessive current from the load to the impedance conversion circuit 1. That is, a low power consumption type configuration can be applied as the impedance conversion circuit 1.

FIG. 4 shows a third specific example of the configuration of FIG. FIG. 3 illustrates a configuration in which a resistor 7 is applied to the impedance conversion circuit 1.

In FIG. 4, the input voltage Vin is
Is derived as a high impedance voltage Vin ′. However, the current driving capability in drawing a current from the load is limited by the output impedance of the input voltage Vin and the impedance of the resistor 7. As a result, since a large load current cannot be obtained, when the load becomes heavy, the output voltage Vin 'naturally increases. Voltage Vin '
However, when the voltage rises by more than the offset of the operational amplifier 2, the operational amplifier 2 inverts its output, and the MOS transistor 5 is turned on. With the turning on of the MOS transistor 5, the load current flows to the constant current source 6 side. Thus, the voltage Vin 'quickly returns to the predetermined voltage. During that time, since the load current flows to the constant current source 6 side, it is not necessary to draw an excessive current from the load to the impedance conversion circuit 1. Since the impedance conversion circuit 1 includes only the resistor 7 in series, power consumption during normal operation can be almost ignored.

FIG. 5 shows a fourth specific example of the configuration of FIG. This is because, in FIG. 2, the + input terminal and the − input terminal of the operational amplifier 2 are exchanged to invert the output condition of the operational amplifier 2, and the output of the operational amplifier 2 is inverted by the inverter 8 connected to the output line 9. This exemplifies a configuration provided to the gate of the MOS transistor 5.

In FIG. 5, the offset of the operational amplifier 2 is set so that the operating point is reached when the voltage Vin 'exceeds a predetermined voltage higher than the input voltage Vin. As a result, in the normal state, the operational amplifier 2 outputs a positive output. As the load current increases, the voltage Vin ′ increases and exceeds the input voltage Vin beyond the voltage difference of the offset of the operational amplifier 2.
The operational amplifier 2 performs a negative output. Inverter 8
Is a MOS transistor which inverts the signal on the output line 9 of the operational amplifier 2 and
To the gate of the type transistor 5. Therefore, when the operational amplifier 2 performs a negative output, the MOS transistor 5 is turned on. As a result, the load current is drawn to the GND side, and the output voltage Vin 'of the impedance conversion circuit 1 is drawn back to the GND side.

2, 3 and 5, when an N-top type operational amplifier as shown in FIG. 21 is used as the operational amplifier 4, the transistor 76 operates mutually with the transistor 75 and outputs the output voltage V 1 ′. It is made equal to the input voltage V1. Originally, the transistor 76 has a high driving capability and a voltage V
Needless to say, it has sufficient ability to raise 1 'to a higher voltage. However, transistor 75
Is a constant current. For this reason, it lacks the ability to quickly pull the fluctuation of the voltage V1 'to the GND voltage side.

On the other hand, in FIGS.
When in ′ becomes a high voltage, the MOS transistor 5 is turned on to share the load current in order to quickly reduce the voltage. Thus, for example, in FIG. 21, the constant current that normally flows through the transistor 75 can be reduced. That is, the transistor 75 only needs to have the minimum current capability necessary to keep the input voltage Vin and the voltage Vin 'the same. Therefore, when the input voltage Vin and the output voltage Vin ′ are almost equal, it is not necessary to flow an unnecessary large current in the operational amplifier 4. As a result, not only can the current consumption be significantly reduced, but also the followability of the input voltage Vin to the voltage Vin 'can be improved.

As described above, in the above-described embodiment, there are various methods for giving the offset of the operational amplifier. The offset given to the comparator can be arbitrarily selected according to the follow-up property of the voltage Vin ′ with respect to the input voltage Vin, the logic configuration of other peripheral circuits, and the like.

FIG. 6 is a block diagram of a constant voltage generating circuit according to a second embodiment of the present invention. FIG. 6 shows an example in FIG. 1 in which a voltage follower type operational amplifier 4 is used as the impedance conversion circuit 1, a P-channel MOS transistor 10 is used as the switch 3, and a VDD voltage is applied as the voltage VA. That is, VD
The D voltage side has a very low output impedance. Note that, as the operational amplifier 4, a P-top type configuration as shown in FIG. 20 is applied.

As is clear from FIG. 6, the operational amplifier 4
Has a voltage-follower type configuration, in which the voltage at the + input terminal is directly derived as an output voltage by negatively feeding back its output. As a result, the input voltage Vin is derived as the impedance-converted voltage Vin ′, but the current driving capability for supplying current to the load is naturally limited. As a result, when the voltage Vin 'drops below the offset of the operational amplifier 11, the operational amplifier 11 inverts its output,
The MOS transistor 10 turns on. As the MOS transistor 10 turns on, the voltage Vin 'is raised to the VDD voltage side. During that time, since the load current is supplied from the VDD side, it is not necessary to allow an excessive current to flow from the impedance conversion circuit 1 to the load. That is, a low power consumption type configuration can be applied as the impedance conversion circuit 1.

In FIG. 6, when the configuration shown in FIG. 20 is applied as the operational amplifier 4, the transistor 36 interacts with the transistor 35, and the output voltage V5 'becomes equal to the input voltage V5. It is needless to say that the transistor 36 originally has a high driving ability, and has a sufficient ability to reduce the voltage V5 'to a low voltage. However, since the transistor 35 has a constant current, the transistor 35 lacks the ability to quickly pull the fluctuation of the voltage V5 'toward the high potential power supply VDD.

On the other hand, in FIG. 6, when the voltage Vin 'becomes low, the MOS transistor 10 is turned on to share the load current in order to quickly raise the voltage Vin'. Thus, for example, in FIG. 20, the constant current that normally flows through the transistor 35 can be reduced. That is, the transistor 35 need only have the minimum current capability necessary to keep the input voltage Vin and the voltage Vin 'the same. Therefore, the input voltage V
When in and the output voltage Vin 'are almost equal, it is not necessary to flow an unnecessary large current in the operational amplifier 4. As a result, not only can the current consumption be significantly reduced, but also the followability of the input voltage Vin to the voltage Vin 'can be improved.

FIG. 7 is a block diagram of a constant voltage generating circuit according to a third embodiment of the present invention. As shown in FIG. 7, the input voltage Vin is passed through the impedance conversion circuit 1 to a voltage V that is impedance-converted to the same voltage as the input voltage Vin.
output as in '. The output of the impedance conversion circuit 1 is provided to the positive input terminals of two operational amplifiers 2 and 11 operating as comparators. Input voltage Vin
Is supplied to the negative input terminals of the operational amplifiers 2 and 11.
The operational amplifiers 2 and 11 are intentionally provided with different offsets, compare the voltage at the positive input terminal with the voltage at the negative input terminal, and determine the output point as the operating point at which the voltage difference between the two becomes the offset. And switches 3 and 13 are turned on / off. The switch 3 performs an intermittent operation between the output voltage Vin ′ of the impedance conversion circuit 1 and GND. The switch 13 performs an intermittent operation between the output voltage Vin ′ of the impedance conversion circuit 1 and the high potential power supply VDD. Incidentally, both the GND voltage and the high potential power supply VDD have low impedance.

Next, the operation of the above configuration will be described.

The operational amplifiers 2 and 11 are intentionally provided with an offset. This is because the input voltage Vin and the voltage V
This is for giving a specific dead band when comparing with in ′. The operational amplifiers 2 and 11 perform a comparison operation from this operating point when a voltage difference equal to or more than the offset occurs between the input voltage Vin ′ of the positive input terminal and the input voltage Vin of the negative input terminal. Then, the switches 3 and 13 are turned on. When the switch 3 is turned on, the output of the impedance conversion circuit 1 is connected to GND, and the output voltage Vin 'of the impedance conversion circuit 1 is reduced to the GND voltage side.
On the other hand, when the switch 13 is turned on, the output of the impedance conversion circuit 1 is connected to the high potential power supply VDD, and the output voltage Vin ′ of the impedance conversion circuit 1 is changed to the high potential power supply VDD.
Raise to D side.

Now, the impedance conversion circuit 1
The input voltage Vin is the impedance-converted voltage Vi.
n '. Of course, there is a limit to the current drive capability when drawing current from the load. As a result, when a voltage rise of the voltage Vin ′ by more than the offset of the operational amplifier 2 occurs, the operational amplifier 2 inverts the output and the switch 3 is turned on. When the switch 3 is turned on, the voltage Vin 'is pulled back to the GND voltage side. During that time, since the load current flows to the GND side, it is not necessary to draw an excessive current from the load to the impedance conversion circuit 1.

On the other hand, the current driving capability for supplying current from the impedance conversion circuit 1 to the load is naturally limited. As a result, if the voltage Vin 'drops by more than the offset of the operational amplifier 11, the operational amplifier 11 inverts its output and the switch 13 is turned on. When the switch 13 is turned on, the voltage Vin ′ becomes V
DD voltage side, during which the load current is V
Since it is supplied from the DD side, the impedance conversion circuit 1
Excessive current flow from the load to the load is suppressed.

FIG. 8 shows a specific example of the configuration of FIG. 7, in which a voltage follower type operational amplifier 4 is used as the impedance conversion circuit 1, an N-channel MOS transistor 5 is used as the switch 3, and a switch 13 is used as the switch 13. 1 shows an example in which a P-channel MOS transistor 10 is used.

As is clear from FIG. 8, the operational amplifier 4
Has a voltage-follower type configuration, in which the output thereof is negatively fed back so that the voltage at the + input terminal is directly derived as the output voltage. as a result,
The input voltage Vin is the impedance-converted voltage Vi.
n '.

In FIG. 8, the operation is almost the same as the configuration of FIG. Therefore, the operational amplifier 4 does not need a large current driving capability, and the input voltage Vin and the voltage Vi are not necessary.
It is only necessary to perform the minimum constant current operation necessary to maintain n 'at the same voltage. Therefore, the power consumption of the operational amplifier 4 can be significantly reduced. Further, the voltage Vin 'is recovered by a high potential power supply VDD or GND potential having a relatively low impedance. Therefore, the followability of the voltage Vin ′ to the input voltage Vin can be improved.

In each of the embodiments described above, for example, the configuration shown in FIG. 2 and the configuration shown in FIG. 6 are applied to the conventional power supply circuit for a liquid crystal display shown in FIG. That is, in FIG. 22, the circuit shown in FIG. 2 is applied to the circuit for converting the impedance from the voltage V2 to the voltage V2 ', and the circuit shown in FIG. 6 is used for the circuit for converting the impedance from the voltages V3 and V4 to the voltages V3' and V4 '. Consider applying.

In this case, as shown in the timing chart of FIG. 9, the current consumption IOP of each operational amplifier is SEG /
At the time of output of COM, that is, only when the voltages V1 'to V5' are particularly consumed, but at other steady states,
Relatively low, and significantly reduced in overall average. As a result, in the case of a power supply circuit for a liquid crystal display that uses many impedance conversion circuits, the power consumption can be significantly reduced.

FIG. 10 is a block diagram when the constant voltage generating circuit of the present invention is applied to a low voltage power supply. As shown in FIG. 10, in the non-inverting amplifier 15, the operational amplifier 14
The voltage V0 is input to the + input terminal, the-input terminal is connected to GND via the resistor Rs, and the output of the operational amplifier 14 is negatively fed back via Rf. Non-inverting amplifier 15
Is input to the constant voltage circuit 16 having the configuration of the present invention. Incidentally, the case where the configuration of FIG. 2 is applied as the constant voltage circuit 16 is shown.

In the above configuration, the non-inverting amplifier 1
5 amplifies the input voltage V0 by (1 + Rf / Fs) times and outputs a voltage (1 + Rf / Fs) V0. The constant voltage circuit 15 receiving this output applies the voltage (1 + Rf / Fs) V
0 'is output. When this output voltage is supplied to another circuit, the load current increases, and when the output voltage of the constant voltage circuit exceeds the offset voltage of the operational amplifier 2, the MOS transistor 5 is turned on to supply the load current to the GND side. Pull down and lower the output voltage. As a result, as a constant voltage power supply,
In normal times when the load current is not so large, the output of the non-inverting amplifier 15 is impedance-converted and output to the outside with very little current consumption.

That is, the constant voltage generating circuit device of the present invention
By incorporating it as a part of the constant voltage source, it is possible to configure a constant voltage source with constant current consumption and good followability.

FIG. 11 shows still another embodiment. FIG.
1 is applied to the negative input of the comparator 2 and Vin of FIG.
And a constant voltage circuit characterized in that a voltage Vin ″ is input instead of the constant voltage circuit.

FIG. 12 shows a case corresponding to FIG.

As shown in FIG. 22, the reference voltages V1 to V5
Is created by resistance division using a resistance element. The voltage dividing circuit 105 of FIG. 22 is configured as shown in FIG. Then, V1 is input to Vin in FIG. 12, and V1 ′ ″ is input to Vin ″ ′. Further, the resistance value is set so that the voltage of V1 obtained in FIGS. 22 and 12 is 5V and V1 '''is 5.1V. Thereby, V1 = Vin = 5V, V
1 ″ ′ = Vin ″ = 5.1 V. It is assumed that the output Vin ′ in FIGS. 11 and 12 fluctuates and exceeds the input voltage of Vin ″ of 5.1 V. At this time, if the comparator 2A having no offset is used, Vin '
Inverts the output at 5.1 V, turns on the transistor, and lowers Vin 'to the GND side. Then, when Vin 'falls below 5.1 V, the output of the comparator 2A is inverted, and the transistor 5 is turned off. In this manner, a new third reference voltage Vin ″ may be input to the comparator 2A. Further, as shown in FIG. 13, the third reference potential Vin ′ ″ can be arbitrarily set by the resistance ratio. In this case, the comparator 2A
Need not be provided with an offset. Comparator 2A
In addition, it is easier and more reliable to use a resistor rather than to design and set an offset voltage using a transistor. Needless to say, a further offset may be provided in the comparator 2A. However, it is clear that voltage setting by resistance division is simpler.

The impedance conversion circuit shown in FIGS. 11 and 12 can be a resistance element or a constant current source as shown in FIG. 3, and various modifications and applications are possible. Needless to say.

FIG. 14 shows still another embodiment. FIG.
In 4, reference numeral 30 denotes a first conductivity type field effect transistor. The source of this transistor 30 is Vin '
The gate is connected to Vin, and the drain is connected to VA.

FIG. 15 is a partial modification of FIG. 14 when it is further embodied. Transistor 3 here
Reference numeral 1 denotes a P-channel MOS transistor. Now, in this circuit, Vin 'fluctuates (rises).
Suppose you did. Then, Vin ′ is calculated by the equation Vin′−Vin
It is assumed that it becomes larger than ≧ V _THP (where V _THP is the threshold voltage of the transistor 31). Then
The transistor 31 is turned on, and the increased Vin 'is applied to GND.
(When VA is set to GND). Therefore, the operational amplifier 4 may be configured to have a small driving capability of the transistor 75 as shown in FIG.
That is, when Vin 'rises, the transistor 31 functions to lower Vin'. In addition, since a field-effect transistor is used as the transistor 31, as the Vin ′ fluctuates greatly, the on-resistance of the transistor 31 decreases, and the Vin ′ is reduced more strongly. Conversely, when Vin 'approaches Vin, the transistor 31 has an increased on-resistance and Vin'
Is less likely to cause undershoot such as exceeding Vin. With these advantages, Vi
It is possible to obtain characteristics that follow the potential fluctuation of n '. still,
Normally, Vin and Vi in the impedance conversion circuit 1
The difference (offset) from n ′ is the V
_It goes without saying that it is smaller than _THP .

FIG. 16 shows a case where VA is the high voltage V _DD and a field effect transistor of the second conductivity type (N-channel MOS transistor 32) is used as the transistor 32.

The source of the transistor 32 is set to Vin ',
The gate is connected to Vin and the drain is connected to V _DD .
Now, Vin 'drops significantly, and its potential Vin-Vi
When n ′ exceeds the threshold voltage V _THN of the transistor 32, the transistor 32 turns on. The transistor 32 has the function of raising the dropped Vin 'to the _VDD side. Then, similarly to FIG. 15, when Vin ′ approaches Vin and reaches the threshold voltage, the transistor 32 is turned off. The descent in this case is the same as in FIG.

FIG. 17 has both FIG. 15 and FIG. 16, and the operational amplifier 4 is replaced with the resistor 7 in the impedance conversion circuit, and a constant current source is provided on the source side of the transistor 31 in FIG. Things. Even in such a circuit, when Vin 'fluctuates,
When either the transistor 31 or 32 turns on,
It works to return Vin 'to the potential of Vin. still,
Naturally, the impedance conversion circuit 1 is shown in FIG.
It goes without saying that the operational amplifier shown in FIG. 16 may be used.

FIG. 18 shows still another embodiment. Here, the transistor 31 in FIG.
Is set to the third reference potential Vin ″ ′.

[0095] In FIG. 18, as' substantially equal stable potential and Vin, that is, the gate bias voltage (Vin 'output Vin''-Vin') does not exceed a threshold V _{TH P} voltage of the transistor 31 Vin '''is set to an arbitrary potential. At this time, when the output Vin 'fluctuates, the transistor 31 is turned on. Thus, it is possible to input the third reference potential.

[0096]

As described above, the constant voltage generation circuit of the present invention intentionally supplies the output voltage to the load through the impedance conversion circuit as a voltage substantially equal to the input voltage as the output voltage. The input voltage is compared with the input voltage by a comparator with an offset, and if the output voltage fluctuates beyond the operating point of the comparator, the load current depends on the other power supply. In addition, the current consumption of the impedance conversion circuit can be reduced, and the followability of the output voltage to the input voltage can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a constant voltage generation circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a first specific example of the configuration of FIG.

FIG. 3 is a block diagram showing a second specific example of the configuration of FIG. 1;

FIG. 4 is a block diagram showing a third specific example of the configuration of FIG. 1;

FIG. 5 is a block diagram showing a fourth specific example of the configuration of FIG. 1;

FIG. 6 is a block diagram of a constant voltage generation circuit according to a second example of the present invention.

FIG. 7 is a block diagram of a constant voltage generation circuit according to a third example of the present invention.

FIG. 8 is a block diagram showing a specific example of the configuration of FIG. 7;

9 is a timing chart for explaining an operation when the present invention is applied to the liquid crystal driving power supply of FIG. 22.

FIG. 10 is a block diagram when the present invention is applied to a constant voltage source.

FIG. 11 is a block diagram of still another embodiment of the present invention.

FIG. 12 is a block diagram showing a specific example of FIG. 11;

FIG. 13 is a circuit diagram illustrating an example of a voltage dividing circuit.

FIG. 14 is a block diagram of still another embodiment of the present invention.

FIG. 15 is a block diagram of a modified example of FIG. 14;

FIG. 16 is a block diagram of still another embodiment of the present invention.

FIG. 17 is a block diagram of still another embodiment of the present invention.

FIG. 18 is a block diagram of still another embodiment of the present invention.

FIG. 19 is a block diagram of a conventional constant voltage generation circuit.

FIG. 20 is a circuit diagram showing an example of a P-top MOS type operational amplifier.

FIG. 21 is a circuit diagram showing another example of an N-top MOS operational amplifier.

FIG. 22 is a block diagram illustrating an example of a known liquid crystal driving power supply.

FIG. 23 is a circuit diagram showing an example of a reference power supply circuit in the configuration of FIG. 22;

24 is a timing chart illustrating the operation of the power supply for driving a liquid crystal in FIG. 22.

FIG. 25 is a symbol diagram of a comparator.

FIG. 26 is a circuit diagram illustrating an example of a comparator.

FIG. 27 is a circuit diagram showing another example of the comparator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Impedance conversion circuit 2, 4, 11, 12, 14, 104 Operational amplifier 3, 13 Switch 5, 10, 17, 18 MOS transistor 6 Constant current source 7 Resistance 9 Output line 15 Non-inverting amplifier 16 Constant voltage circuit 100 Drive Circuit 101 External connection terminal 102 Output section 103 Wiring 105 Voltage divider 106 Reference power supply circuit 109 Operational amplifier circuit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-238509 (JP, A) JP-A-3-196317 (JP, A) JP-A-3-230188 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G05F 1/10 G05F 1/618 310

Claims (16)

(57) [Claims] An impedance conversion circuit for converting a first reference voltage into an impedance and outputting a second reference voltage, wherein the first and second reference voltages are directly input, and the two reference voltages are inputted. A comparator for inverting an output in a first case where the voltage difference is larger than a predetermined offset voltage and a second case where the voltage difference is smaller than a predetermined offset voltage; Switch means for controlling connection / disconnection of the reference voltage to / from a power supply. 2. An impedance conversion circuit for impedance-converting a first reference voltage and outputting a second reference voltage, wherein the second and third reference voltages are directly inputted, and the two reference voltages are inputted. A comparator having no offset for inverting the output according to the magnitude of the voltage; and switch means for controlling connection / disconnection of the second reference voltage to / from a power supply according to the output level of the comparator. , Constant voltage generation circuit. 3. An impedance conversion circuit for impedance-converting a first reference voltage and outputting a second reference voltage, wherein the second and third reference voltages are directly input, and the two reference voltages are inputted. A comparator having an offset for inverting the output according to the magnitude of the voltage, and switch means for controlling connection / disconnection of the second reference voltage to / from a power supply according to the output level of the comparator. Constant voltage generation circuit. 4. The constant voltage generation circuit according to claim 1, wherein said impedance conversion circuit is a voltage-type follower circuit. 5. The constant voltage generation circuit according to claim 1, wherein said impedance conversion circuit is a resistance element. 6. The power supply according to claim 1, wherein said power supply is a constant current source.
3. The constant voltage generation circuit according to claim 1. 7. The constant voltage generating circuit according to claim 1, wherein said comparator and said switch means are configured to include a MOS type field effect transistor. 8. The comparator has first and second input transistors to which the first and second reference voltages are applied to a gate terminal, and has a gate width and a gate width of the first and second input transistors. The offset voltage is determined by giving a deviation to the gate length,
A constant voltage generating circuit according to claim 1. 9. The constant voltage generating circuit according to claim 1, further comprising a voltage amplifying circuit for generating said first reference voltage by arbitrarily multiplying a fourth reference voltage. 10. A semiconductor integrated circuit device using the constant voltage generation circuit according to claim 1 as a part of a power supply circuit for driving a liquid crystal panel. 11. An impedance conversion circuit for impedance-converting a first reference voltage to output a second reference voltage, and a power supply for a second reference voltage as a source, a first reference voltage as a gate, and a drain as a power supply. And a first conductivity type field effect transistor respectively connected to the constant voltage generating circuit. 12. The constant voltage generating circuit according to claim 11, wherein said impedance conversion circuit is a voltage type follower circuit. 13. The constant voltage generation circuit according to claim 11, wherein said impedance conversion circuit is a resistance element. 14. The power supply according to claim 11, wherein said power supply is a constant current source.
14. The constant voltage generation circuit according to any one of claims 13 to 13. 15. The constant voltage generating circuit according to claim 11, further comprising a voltage amplifying circuit for generating said first reference voltage by arbitrarily multiplying a fourth reference voltage. 16. A semiconductor integrated circuit device using the constant voltage generation circuit according to claim 11 as a part of a power supply circuit for driving a liquid crystal panel.