JP2004248497A - Power supply circuit, liquid crystal device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply circuit suited for generating an electric potential for driving liquid crystal which can deal with generation of a multi electric potential level, a liquid crystal device, and an electronic apparatus, using the power supply circuit, at a low cost. <P>SOLUTION: A first booster circuit 12 of a power supply circuit 10, with a grounding level VSS serving as the reference, generates a first step-up potential level VOUT boosting a power supply level VDD. A regulator circuit 14, referring to a reference electric potential level Vref with the grounding level VSS serving as the reference, generates a center potential VC adjusting the first step-up potential level VOUT. A second booster circuit 16, making the grounding level VSS serve as the reference, generates a potential level V3 boosting the center potential VC. A multi-value potential generating circuit 18, making the grounding level VSS serve as the reference, generates potential levels V2, V1, MV1 and MV2 from a potential difference between the potential level V3 and the center potential VC, and supplies them to a panel of the liquid crystal device driven for display by an MLS drive method. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a power supply circuit suitable for generating a liquid crystal driving potential, a liquid crystal device and an electronic apparatus using the same.

  2. Description of the Related Art In recent years, liquid crystal devices incorporated in electronic devices such as mobile phones, personal digital assistants, and game devices have been strongly demanded to have lower prices and lower power consumption. In the case of a simple matrix type liquid crystal device, these requirements can be satisfied by a multiple line selection (hereinafter, abbreviated as MLS) driving method.

  In the MLS driving method, a plurality of lines of scan electrodes are selected at the same time, and in each field constituting one frame, a potential having a given orthogonal relationship and corresponding to the selected pattern is applied to each scan electrode. A potential corresponding to the pixel pattern to be turned on / off and the above-described scanning electrode selection pattern is also applied to each signal electrode. By doing so, the effective value of the voltage value applied to each electrode can be set to a required value without increasing the potential level to be applied.

  It is known that when the liquid crystal device is driven for display by the MLS driving method, it is optimal to perform the driving in accordance with the following equation (1).

L = (1 / a−1) ² (1)
Here, L is the number of display lines. A is a bias ratio. This bias ratio refers to the ratio between the effective value voltage applied when the liquid crystal is on and the effective value voltage applied when the liquid crystal is off. For example, if the bias ratio is 1/5, it means that the optimal number of display lines is 16 lines.

  By the way, recently, the size of the panel of the liquid crystal device has been increased, and accordingly, the number of lines has been increased. Therefore, the number of potential levels required for driving the liquid crystal tends to increase in order to obtain the bias ratio optimized by the equation (1).

  However, in the MLS driving method, a potential level to be applied to the scanning electrode and the signal electrode is determined based on the center potential VC. Therefore, when a twin-well process that can be reduced in cost is used, if the center potential VC is set to the ground level VSS, a large number of external parts are required to generate a potential level lower than the ground potential VC, which increases the cost of the device. There are costs and mounting problems.

  On the other hand, if the center potential VC is brought to the positive side, the highest potential level needs to be within the range of the high withstand voltage of the process to be used, and it will not be possible to cope with future multipotential levels.

  The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a low-cost, power supply circuit suitable for generating a liquid crystal driving potential capable of supporting multiple potential levels. In addition, a liquid crystal device and an electronic device using the same are provided.

  In order to solve the above problem, the present invention is a power supply circuit for generating a plurality of potentials, the power supply circuit being connected to first and second power supply lines for supplying first and second potentials. A first booster circuit that supplies a third potential boosted based on a difference between the two potentials to a third power supply line; and a first booster circuit connected to the first and third power supply lines; A potential adjusting circuit for supplying a fourth potential, which is a constant potential generated based on a potential difference, to a fourth power supply line, and a first and fourth power supply lines connected to the first and fourth power supply lines; A second booster circuit that supplies a fifth potential boosted based on a potential difference to a fifth power supply line, and is connected to the first, fourth, and fifth power supply lines; And a multi-level potential generating circuit for generating a plurality of potentials based on the fifth potential difference.

  According to the present invention, the first booster circuit causes the third potential (for example, the ground level VSS) to be based on the potential difference between the first potential (for example, the ground level VSS) and the second potential (for example, the power supply level VDD). A first boosted potential level VOUT) is generated, and a fourth potential (for example, a center potential VC) is generated by the potential adjustment circuit based on the first and third potential differences. Then, a fifth potential (for example, potential level V3) is boosted and generated based on the first and fourth potential differences by the second booster circuit, and a plurality of potential levels are generated by the multi-level potential generation circuit. I did it. Thus, only the potential on one side (positive side or negative side) of the first potential can be used, so that an external component is required to generate a plurality of potentials as in the related art. As a result, the cost of the device can be reduced, and there is no mounting problem. Further, the potential adjusting circuit does not need to have a high withstand voltage with respect to the fifth potential, so that it is possible to avoid a decrease in reliability and to cope with future multipotentials.

  Further, the invention is characterized in that the multi-level potential generation circuit supplies the fourth potential as a center potential of a plurality of potentials supplied to a liquid crystal device.

  Here, as a liquid crystal device, for example, there is a liquid crystal device including a simple matrix type liquid crystal panel driven for display by the MLS driving method.

  According to the present invention, as the center potential of the plurality of potentials supplied to such a liquid crystal device, the fourth potential on one side generated from the first potential with respect to the first potential is supplied. Thus, the present invention can be applied as a power supply circuit for supplying a multi-potential power supply to a liquid crystal device including a simple matrix type liquid crystal panel driven for display by the MLS driving method, for example. This means that a power supply circuit capable of maintaining low cost and high reliability can be provided even when the number of power supply levels required for the liquid crystal device increases as described above.

  Further, according to the present invention, at least one of the first and second booster circuits is connected between a power supply line to which a boosted potential is supplied and a power supply line on a lower potential side of the two connected power supply lines. The first to fourth switch circuits connected in series, the second switch circuit is connected to a first switch circuit connected to the boost power supply line, and the third switch is connected to the second switch circuit. When a circuit is connected and the fourth switch circuit is connected between the third switch circuit and the power supply line for supplying the low potential, the fourth switch circuit is connected in parallel with the second and third switch circuits. A drive signal for the first to fourth switch circuits is generated such that the connected capacitor, the first and third switch circuits, and the second and fourth switch circuits are turned on alternately. A timing signal generation circuit; Characterized in that it is a charge pump circuit.

  Here, the first switch circuit is connected to the boosted power supply line. However, the first switch circuit may be connected to a power supply line that supplies a low potential among two connected power supply lines. In short, when four switch circuits connected in series are sequentially referred to as a first switch circuit, a second switch circuit,..., A capacitor is connected in parallel with the second and third switch circuits. What should I do?

  At this time, for example, at the first timing when the first switch circuit and the third switch circuit connected to the boosted power supply line are on and the second and fourth switch circuits are off, the path from the boosted power supply line is , The first switch circuit, the capacitor, the third switch circuit, and the high-potential power supply line to be connected. Therefore, the difference between the potential of the boosted power supply line and the potential of the high-potential power supply line is applied to the capacitor.

  Next, at the second timing when the first switch circuit and the third switch circuit are off and the second and fourth switch circuits are on, the above-described high-potential power line, the second switch circuit, and the capacitor are used. , A fourth switch circuit and a low-potential power supply line. As a result, a difference between the potential of the high potential power supply line and the potential of the low potential power supply line is applied to the capacitor.

  Therefore, with reference to the low-potential power supply line, the difference between the potential of the high-potential power supply line and the potential of the low-potential power supply line, the potential of the boosted power supply line, and the potential of the above-described high-potential power supply line Will be generated as the boosted potential.

  As described above, according to the present invention, the current consumption can be reduced only by the switch circuit. Therefore, it is possible to contribute to lower power consumption of the power supply circuit.

  Further, in the invention, it is preferable that the first to fourth switch circuits include a first conductivity type well connected to the first power supply line, and a second conductivity type well connected to the fifth power supply line. And a twin-well structure comprising:

  According to the present invention, an inexpensive process can be used, so that the cost of the power supply circuit can be reduced.

  Further, in the invention, it is preferable that the multi-level potential generation circuit includes a first voltage dividing circuit for dividing the difference between the first and fourth potentials by resistance, and a first voltage dividing circuit for dividing the difference between the fourth and fifth potentials. 2, a voltage-follower-connected first operational amplifier circuit connected to the potential divided by the first voltage dividing circuit, and resistance-divided by the second voltage dividing circuit. A second operational amplifier circuit connected to a potential and connected to a voltage follower.

  According to the present invention, the potential obtained by dividing the resistance as the multi-valued potential generating circuit is supplied with the resistance divided potential by the operational amplifier circuit connected in a voltage follower, so that the fluctuation of the potential due to the fluctuation of the load can be avoided. In addition, a power supply circuit capable of supplying a stable potential can be provided.

  Also, in the present invention, the multi-level potential generating circuit may further include a first operational amplifier connected to a potential obtained by dividing a difference between the first and fourth potentials by resistance, and connected to a voltage follower for supplying a sixth potential. A second operational amplifier circuit connected to a circuit, a voltage follower-connected second operational amplifier circuit configured to connect a difference between the fourth and fifth potentials to a resistance-divided potential, and to supply a seventh potential; A first step-down circuit for generating an eighth potential stepped down based on a potential difference, and a second step-down circuit for generating a ninth potential stepped down based on a difference between the fourth and seventh potentials; It is characterized by including.

  According to the present invention, the difference between the first and fourth potentials is connected to the first operational amplifier circuit, which is connected by a voltage follower, to the potential obtained by dividing the resistance, and the sixth potential is supplied. The second operational amplifier circuit connected in a voltage follower connection to the potential obtained by dividing the potential of the resistor by the resistance is connected to supply the seventh potential. Then, the first and second step-down circuits generate an eighth potential based on the difference between the fourth and sixth potentials and a ninth potential based on the difference between the fourth and seventh potentials, respectively. Therefore, there is no need to use an operational amplifier circuit that consumes a large amount of current for each supply potential, and power consumption can be reduced.

  Also, in the present invention, the multi-level potential generation circuit may be configured to connect the difference between the first and fourth potentials or the difference between the fourth and fifth potentials to a resistance-divided potential and supply a sixth potential. A voltage-follower-connected first operational amplifier circuit, a third booster circuit that generates a seventh potential boosted in the fourth potential direction based on the difference between the fourth and sixth potentials, A first step-down circuit for generating an eighth potential stepped down based on the difference between the fourth and sixth potentials, and a ninth potential stepped down based on the difference between the fourth and seventh potentials And a second step-down circuit.

  Here, boosting in the fourth potential direction means that, for example, the fourth potential is compared with the sixth potential, and when the fourth potential is higher, the fourth and sixth potentials are set based on the sixth potential. This refers to increasing the potential difference, and in the case where the fourth potential is low, refers to increasing the difference between the sixth and sixth potentials with reference to the fourth potential.

  According to the present invention, the first operational amplifier circuit divides the difference between the first and fourth potentials or the difference between the fourth and fifth potentials by resistance and supplies the sixth potential. Then, the seventh booster circuit generates a seventh potential boosted in the fourth potential direction based on the difference between the fourth and sixth potentials. Then, the eighth and ninth potentials are stepped down and generated by the first and second step-down circuits based on the difference between the fourth and sixth potentials and the difference between the fourth and seventh potentials. did. As a result, the number of operational amplifier circuits can be further reduced, so that more effective power consumption can be reduced.

  Further, according to the present invention, in the first or second operational amplifier circuit, a first conductivity type transistor whose gate is supplied with a first differential output and a source is supplied with the second potential; A second conductive type transistor in which the first potential is supplied to a dynamic output and a source, and a drain of the first conductive type transistor is connected to a drain; the resistance-divided potential; and the first or second conductive type. A first conductivity type differential amplifier circuit for generating the first differential output based on a potential difference from a potential of a drain of the type transistor, the resistance-divided potential, and the first or second conductivity type. A second-conductivity-type differential amplifier circuit that generates the second differential output based on a potential difference from a potential of a drain of the transistor; and a first-conduction-type differential amplifier circuit based on the second differential output. A first method for controlling the constant current value of the differential amplifier circuit A flow control circuit, on the basis of the first differential output, characterized in that it comprises a second current control circuit for controlling the constant current value of the differential amplifier circuit of the second conductivity type.

  According to the present invention, the first current control circuit controls the constant current value of the first conductivity type differential amplifier circuit based on the differential output of the second differential amplifier circuit. The gate voltage of the first conductivity type transistor can be controlled. Further, the second current control circuit controls the magnitude of the constant current value of the second conductivity type differential amplifier circuit based on the differential output of the first differential amplifier circuit to thereby control the second conductivity type transistor. Can be controlled. Thus, the operations of the first and second conductivity type transistors can be hastened, and as a result, the output potential of the operational amplifier circuit can be quickly changed to a stable state.

  In this case, the constant current value of the first and second differential amplifier circuits is set to a value as small as possible, and a current having an optimum value is supplied only at the time of necessary stable output, thereby reducing the power consumption of the operational amplifier circuit. Can also be realized.

  In the present invention, the first and second conductivity type differential amplifier circuits may be configured such that the resistance-divided potential and the drain potential of the first or second conductivity type transistor are supplied to the gates of transistors having different capacities. It is characterized by being performed.

  According to the present invention, the same current flows through a transistor having a high current driving capability and a transistor having a low current driving capability, so that the potential of the differential output fluctuates. The gate-source voltage can be reduced, and as a result, current consumption can be reduced.

  Further, the operational amplifier circuit according to the present invention includes a first conductivity type transistor in which a first differential output is supplied to a gate and the second potential is supplied to a source, a second differential output to a gate, and a second differential output to a source. 1, a second conductivity type transistor having a drain connected to the drain of the first conductivity type transistor, a given differential input potential, and a potential of the drain of the first or second conductivity type transistor. A differential amplifier circuit of a first conductivity type for generating the first differential output based on a potential difference between the first and second conductive transistors, a given differential input potential, and a potential of a drain of the first or second conductivity type transistor And a second conductive type differential amplifier circuit for generating the second differential output based on the potential difference between the first conductive type differential amplifier circuit and the first conductive type differential amplifier circuit based on the second differential output. A first current control circuit for controlling a constant current value; Based on the differential output, characterized in that it comprises a second current control circuit for controlling the constant current value of the differential amplifier circuit of the second conductivity type.

  According to the present invention, the first current control circuit controls the constant current value of the first conductivity type differential amplifier circuit based on the differential output of the second differential amplifier circuit. The gate voltage of the first conductivity type transistor can be controlled. Further, the second current control circuit controls the magnitude of the constant current value of the second conductivity type differential amplifier circuit based on the differential output of the first differential amplifier circuit to thereby control the second conductivity type transistor. Can be controlled. Thus, the operations of the first and second conductivity type transistors can be hastened, and as a result, the output potential of the operational amplifier circuit can be quickly changed to a stable state.

  In this case, the constant current value of the first and second differential amplifier circuits is set to a value as small as possible, and a current having an optimum value is supplied only at the time of necessary stable output, thereby reducing the power consumption of the operational amplifier circuit. Can also be realized.

  Also, in the present invention, the first and second conductivity type differential amplifier circuits may be configured such that the given differential input potential and the drain potential of the first or second conductivity type transistor are connected to the gates of transistors having different capabilities. Is supplied.

  According to the present invention, the same current flows through a transistor having a high current driving capability and a transistor having a low current driving capability, so that the potential of the differential output fluctuates. The gate-source voltage can be reduced, and as a result, current consumption can be reduced.

  Further, the power supply circuit according to the present invention is a voltage dividing circuit for dividing a given potential, and the operational amplifier circuit according to the above, wherein the potential divided by the voltage dividing circuit is supplied as the given differential input potential. And characterized in that:

  According to the present invention, it is possible to provide a power supply circuit that can output a stable potential without being affected by an output load and that can reduce power consumption.

  Further, a liquid crystal device according to the present invention includes a power supply circuit according to any one of the above, a liquid crystal panel in which a plurality of scanning electrodes and a plurality of signal electrodes are arranged in an intersecting manner, and driving the scanning electrodes by receiving power from the power supply circuit And a signal electrode driving circuit that receives power from the power supply circuit and drives the signal electrodes.

  According to another aspect of the invention, an electronic apparatus includes the above-described liquid crystal device.

  A liquid crystal device and an electronic device according to the present invention include the above-described power supply circuit, and power consumption of the liquid crystal device is reduced. Therefore, the liquid crystal device and the electronic device are particularly useful for a portable electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

1. 1. Liquid Crystal Device FIG. 1 shows a main configuration of a liquid crystal device to which the power supply circuit according to the present embodiment is applied.

  The liquid crystal device 2 includes a simple matrix type liquid crystal panel 4. In the liquid crystal panel 4, a liquid crystal is sealed between a first substrate on which the scanning electrodes C0 to Cm are formed and a second substrate on which the signal electrodes S0 to Sn are formed. The intersection of one of the scanning electrodes and one of the signal electrodes becomes a display pixel, and the liquid crystal panel 4 has (m + 1) × (n + 1) display pixels.

  When the scan electrode is called a common electrode and the signal electrode is called a segment electrode, the scan electrode drive circuit may be called a common driver and the signal electrode drive circuit may be called a segment driver. Further, as the liquid crystal panel 4 in the present embodiment, instead of the simple matrix type, another liquid crystal panel such as an active matrix type can be used.

  A predetermined potential is applied to the scanning electrodes C0 to Cm formed on the liquid crystal panel 4 by the scanning electrode driving circuit 6. A predetermined potential is applied to the signal electrodes S <b> 0 to Sn formed on the liquid crystal panel 4 by the signal electrode driving circuit 8.

  The scan electrode drive circuit 6 and the signal electrode drive circuit 8 are supplied with the above-described potential from the power supply circuit 10 and, based on a signal from the drive control circuit 9, change the predetermined potential to the scan electrode C0 to Cm or the signal electrode S0 to Sn are selectively supplied.

  The liquid crystal device 2 in the present embodiment is driven for display by the MLS driving method in which the number of simultaneously selected lines is 4, based on a signal from the drive control circuit 9 corresponding to the pixel pattern to be driven for display. Therefore, the power supply circuit 10 according to the present embodiment generates a plurality of potential levels based on the center potential VC as potential levels to be supplied to the scan electrodes C0 to Cm and the signal electrodes S0 to Sn. These potential levels are potential levels generated on the positive side with the ground level VSS, which is the substrate level, as MV3, and are a total of seven potential levels (V3, V2, V1, VC, MV1, MV2, MV3).

  FIG. 2 shows an example of a driving waveform in the liquid crystal panel 4 shown in FIG.

  Here, the driving waveforms of the signal electrode S1 and the scanning electrodes C0 to C3 are shown. In addition, one frame is divided into four fields, and signal electrodes are displayed only for eight lines (two clocks for each field), and the description is omitted.

  The scan electrodes C0 to C3 are supplied with the potential of the pattern shown by the drive waveform in FIG. The signal electrode driving circuit 8 supplies the signal electrodes S1 with the potential of the pattern shown by the driving waveform in FIG. As described above, according to the MLS driving method of four lines simultaneously selected, three levels of the liquid crystal driving potentials V3, VC, and MV3 are used as the driving potentials of the scanning electrodes C0 to C3. Similarly, five levels of liquid crystal driving potentials V2, V1, VC, MV1, and MV2 are used as the driving potential of the signal electrode S1.

  Each pixel of the liquid crystal panel 4 is turned on / off by an effective value of a potential difference between a crossing scanning electrode and a signal electrode in one frame period. FIG. 2 shows an example of a drive waveform in a case where the pixel where the signal electrode S1 intersects the scanning electrodes C0 to C2 is on and the pixel which intersects the scanning electrode C3 is off.

2. Power Supply Circuit FIG. 3 shows an outline of the configuration of the power supply circuit in the present embodiment shown in FIG.

  The power supply circuit 10 according to the present embodiment includes a first booster circuit 12, a regulator circuit 14 as potential adjusting means, a second booster circuit 16, and a multi-level potential generation circuit 18.

  FIG. 4 schematically shows the operation of the power supply circuit shown in FIG.

  The first booster circuit 12 of the power supply circuit 10 according to the present embodiment includes a power supply potential supply line 20 to which the power supply level VDD is supplied, a ground potential supply line 22 to which the ground level VSS is supplied, and a first potential supply line. 24 are connected. The first booster circuit 12 supplies to the first potential supply line 24 a first boosted potential level VOUT obtained by boosting the power supply level VDD with reference to the ground level VSS.

  The regulator circuit (potential adjusting means in a broad sense) 14 is connected to the ground potential supply line 22, the first potential supply line 24, and the second potential supply line 26. The regulator circuit 14 adjusts the center potential VC obtained by adjusting the first boosted potential level VOUT supplied from the first booster circuit 12 with reference to the reference potential level Vref with reference to the ground level VSS and the second potential. Supply to supply line 26. More specifically, the regulator circuit 14 generates, from the first boosted potential level VOUT, a center potential VC that is a lower potential level and a constant potential level that can be adjusted.

  The second booster circuit 16 is connected to a ground potential supply line 22, a second potential supply line 26, and a first liquid crystal drive potential supply line. The second booster circuit 16 supplies to the first liquid crystal drive potential supply line 28 a potential level V3 obtained by boosting the center potential VC adjusted by the regulator circuit 14 with reference to the ground level VSS. Further, the second booster circuit 16 supplies the center potential VC to the multi-level potential generating circuit 18 via the center potential supply line 30 as it is.

  The multi-level potential generation circuit 18 is connected to the ground potential supply line 22, the center potential supply line 30, and the first to fifth liquid crystal drive potential supply lines 28, 32, 34, 36, 38. The multi-level potential generation circuit 18 converts the potential levels V2, V1, MV1, and MV2 generated from the potential difference between the potential level V3 from the second booster circuit 16 and the center potential VC with reference to the ground level VSS, respectively. To the fifth liquid crystal drive potential supply lines 32, 34, 36, 38. These potential levels V2, V1, MV1, and MV2 are potential levels corresponding to a bias ratio determined according to the number of display lines of a panel of a liquid crystal device driven for display by the MLS driving method. For example, as shown in FIG. 4, the multi-level potential generation circuit 18 divides or drops the potential difference between the potential level V3 and the center potential VC, or the center potential VC and the ground level VSS (MV3) to reduce each potential level. Generate.

  By doing so, the power supply circuit according to the present embodiment generates seven potential levels (V3, V2, V1, VC, MV1, MV2, MV3).

  Therefore, even when a twin-well process capable of reducing the cost is used, no external parts are required, the cost of the device is reduced, and no mounting problem occurs. In addition, the regulator circuit 14 does not need to have high withstand voltage against the potential level V3, so that it is possible to avoid a decrease in reliability and sufficiently cope with future multipotential levels.

  Hereinafter, the main components of the power supply circuit according to the present embodiment will be specifically described.

2.1 First Boost Circuit FIG. 5 shows an example of the configuration of the first booster circuit according to the present embodiment.

  The first booster circuit 12 in the present embodiment is a charge pump circuit that performs double boosting to generate a potential level higher than the center potential VC to be supplied to the liquid crystal device.

More specifically, the first booster circuit 12 includes first to fourth switch circuits 42 _{1 to} 42 ₄ connected in series between the first potential supply line 24 and the ground potential supply line 22. When, and a first switch driving circuit 44 for turning on and off driving the first to fourth switching circuits 42 ₁ to 42 _4. Here, the first booster circuit 12 includes the first switch drive circuit 44, but is not limited thereto. Each switch drive signal generated by the first switch drive circuit 44 is from outside it may be supplied to the first to fourth switching circuits 42 ₁ to 42 _4.

Assuming that connection points of the _first to fourth switch circuits 42 _{1 to} 42 ₄ are ND ₁ to ND ₃ , respectively, the first booster circuit 12 includes a capacitor 46 connected between ND ₁ and ND ₃ , It includes a capacitor 48 ₁ connected between the ND ₂ first potential supply line 24 and a capacitor 48 ₂ connected between the ND ₂ and the ground potential supply line 22.

The first switch driver circuit 44 repeats the first and third switching circuits 42 _1, 42 ₃ and a period for turning on, to the time of turning on the second and fourth switching circuits 42 _2, 42 ₄ alternately To drive the _first to fourth switch circuits 42 _{1 to} 42 ₄ .

Here, the first to third switching circuits 42 ₁ to 42 ₃ are metal oxide semiconductor p-type (first conductivity type) shown in FIG. 5 (Metal Oxide Semiconductor: MOS) transistors (hereinafter, simply referred to as transistors .), will be described as a transistor of the fourth switch circuit 42 ₄ is n-type, which is connected to the ground level VSS (second conductivity type), is not limited thereto, it has a switch function Any circuit can be applied.

  FIG. 6 shows an example of each switch drive signal generated by the first switch drive circuit 44.

The switch drive signal supplied to the first gate electrode of the p-type transistor of the switch circuit 42 ₁ XB2, a switch drive signal supplied to the gate electrode of the second p-type transistor of the switch circuit 42 ₂ XA2, third of the switch circuit 42 ₃ XB2 switch drive signal supplied to the gate electrode of the p-type transistor, a switch drive signal supplied to the gate electrode of the n-type transistor of the fourth switch circuit 42 ₄ and a.

  Each switch drive signal has a non-overlap period so that the switch circuits connected to each other are not turned on at the same time. As a result, the through path from the first potential supply line 24 to the ground potential supply line 22 is cut off, thereby reducing current consumption.

In the first timing shown in FIG. 6, the switch circuit 42 of the _first and third, 42 ₃ is turned off, the second and fourth switching circuits 42 _2, 42 ₄ it is turned on. Therefore, a capacitor 48 ₁ connected between a first potential supply line 24 and ND _2, and the capacitor 46, 48 ₂ connected in parallel between the ND ₂ and the ground potential supply line 22, in series It will be in the connected state.

On the other hand, in the second timing shown in FIG. 6, the first and third switching circuits 42 _1, 42 ₃ is turned on, the second and fourth switching circuits 42 _2, 42 ₄ are turned off. Therefore, a capacitor 46, 48 ₁ connected in parallel between the ND ₂ first potential supply line 24, and capacitor 48 ₂ connected between the ground potential supply line 22 and ND ₂ is in series It will be in the connected state.

Thus, the first through the switching operation of the fourth switch circuit 42 ₁ to 42 ₄ by the first switch driving circuit 44, a capacitor 46, for both of the capacitors 48 _1, 48 _2, parallel with the series connection The connection is alternately repeated. Thus, as the voltage value applied to both ends of the capacitor 46, 48 _1, 48 ₂ are equal, the charge stored in the capacitor 46, 48 _1, 48 ₂ is stabilized.

Accordingly, by fixing the ND ₂ to the power supply level VDD, the first boosted potential level VOUT supplied to the first potential supply line 24, based on the ground level VSS, and two times the potential of the power supply level VDD Become.

According to such a charge pump circuit, it can be by the capacitor 46, 48 _1, 48 _2, so only the first to the switching current of the fourth switch circuit 42 ₁ to 42 _4, to reduce the current consumption. Further, regardless of the capacitance value of the capacitor 46, 48 _1, 48 _2, it is possible to boost twice the accuracy power supply level VDD through the switching operation described above.

  Here, the charge pump circuit that performs double boosting has been described, but the present invention is not limited to this. As the first booster circuit 12 in the present embodiment, a charge pump circuit is preferably applied. However, if a first boosted potential level VOUT having a potential level higher than the center potential VC to be supplied to the liquid crystal device can be generated. Good.

Also, if the accuracy is not required, the first step-up circuit 12 shown in FIG. 5, be deleted capacitors 48 _1, 48 _2, you can perform the same double boosting.

2.2 Regulator Circuit FIG. 7 shows an example of the configuration of the regulator circuit in the present embodiment.

  The regulator circuit 14 in the present embodiment includes a p-type (first conductivity type) differential amplifier circuit.

  More specifically, p-type transistors 50 and 52 whose sources are connected to the first potential supply line 24 and whose gate electrodes are connected to each other are connected to the drains of the p-type transistors 50 and 52 and the drains thereof. Including n-type transistors 54 and 56. The gate electrodes of the p-type transistors 50 and 52 are connected to the drain of the p-type transistor 52, and the two transistors form a current mirror circuit. The reference potential level Vref is supplied to the gate electrode of the n-type transistor 54. The sources of the n-type transistors 54 and 56 are connected to the drain of an n-type transistor 58 having a gate electrode to which a constant voltage is applied. The source of the n-type transistor 58 is connected to the ground potential supply line 22. That is, the n-type transistor 58 becomes a current source corresponding to a potential difference between the center potential VC and the ground level VSS.

  A connection point between the drain of the p-type transistor 50 and the drain of the n-type transistor 54 is connected via a gate electrode of the p-type transistor 60 whose source is connected to the first potential supply line 24 and a capacitor 62 for preventing oscillation. It is connected to the second potential supply line 26. The drain of the p-type transistor 60 is connected to the second potential supply line 26.

  The second potential supply line 26 is connected to the drain of an n-type transistor 64 having a constant voltage applied to the gate electrode. The source of the n-type transistor 64 is connected to the ground potential supply line 22. That is, the n-type transistor 64 becomes a current source corresponding to the potential difference between the center potential VC and the ground level VSS.

  A resistance element 66 that can be resistance-divided at an arbitrary ratio is connected between the second potential supply line 26 and the ground potential supply line 22, and the resistance division potential is applied to the gate electrode of the n-type transistor 56. It is supposed to be.

  With such a feedback configuration, first, a potential corresponding to the difference between the reference potential level Vref in the p-type transistors 54 and 56 and the resistance division potential level is applied to the gate electrode of the p-type transistor 60.

  Here, when the resistance division potential level becomes higher than the reference potential level Vref, the difference between these potential levels is amplified, and the potential of the gate electrode of the p-type transistor 60 increases. Therefore, the current supply capability of p-type transistor 60 decreases. As a result, the center potential VC decreases, and the resistance division potential also decreases.

  On the other hand, when the resistance division potential level becomes lower than the reference potential level Vref, the difference between these potential levels is amplified, and the gate electrode potential of the p-type transistor 60 decreases. Therefore, the current supply capability of p-type transistor 60 increases. As a result, the center potential VC increases, and the resistance division potential also increases.

  As described above, the regulator circuit 14 generates the center potential VC so that the reference potential level Vref is equal to the resistance division potential. In this case, the center potential VC can be generated even when the load connected to the second potential supply line 26 changes. Moreover, in the resistance element 66, the center potential VC can be changed by changing the level of the resistance division potential.

2.3 Second Boost Circuit 2.3.1 Configuration Example FIG. 8 shows an example of a configuration of the second booster circuit and the multi-level potential generation circuit in the present embodiment.

  The second booster circuit 16 in the present embodiment is a charge pump circuit that boosts the center potential VC twice as much as the ground level VSS.

More specifically, the second booster circuit 16 includes _{fifth to} eighth switch circuits 42 ₅ connected in series between the first liquid crystal drive potential supply line 28 and the ground potential supply line 22. -42 includes a _8, a second switch drive circuit 70 for on-off driving the switching circuit 42 _{5-42 8} of the eighth. Here, although the second booster circuit 16 is included in the second switch drive circuit 70, the present invention is not limited to this, and each switch drive signal generated by the second switch drive circuit 70 may be an external switch drive signal. from may be supplied to the switch circuit 42 _{5-42 8} of the eighth.

When the connection point of the switching circuit 42 _{5-42 8} of the eighth to the ND ₄ to ND ₆ respectively, the second step-up circuit 16 includes a capacitor 72 connected between the ND ₄ and ND ₆ .

The second switch driver circuit 70, like the first switch driving circuit 44 shown in FIG. 5, a period for turning on the switching circuit 42 _5, 42 ₇ of the fifth and seventh, sixth and eighth as the period for turning on the switch circuit 42 _6, 42 ₈ are repeated alternately, to drive the switching circuit 42 _{5-42 8} of the eighth.

In FIG. 8, similarly to FIG. 5, the transistor of the fifth to seventh switching circuit 42 _{5-42 7} p-type (first conductivity type), the eighth switch circuit connected to the ground level VSS 42 ₈ is assumed to be a transistor of the n-type (second conductivity type), but is not limited thereto, can be applied to any circuit having a switch function.

  The switch drive signals generated by the second switch drive circuit 70 are the same as the switch drive signals generated by the first switch drive circuit 44 shown in FIG.

That is, in the first timing, the switch circuit 42 _5, 42 ₇ of the fifth and seventh off, the switch circuits 42 _6, 42 ₈ of the sixth and eighth are turned on. Therefore, one end of the capacitor 72 is electrically disconnected from the first liquid crystal drive potential supply line 28 and is connected to the center potential supply line 30 via the _sixth switch circuit 426. The other end of the capacitor 72 is connected to the ground potential supply line 22 via an _eighth switch circuit 428.

In the second timing, the fifth and seventh switching circuits 42 _5, 42 ₇ are turned on, the switch circuits 42 _6, 42 ₈ of the sixth and eighth are turned off. Thus, one end of the capacitor 72 is connected to the first liquid crystal driving voltage supply line 28 through the switching circuit 42 ₅ of the fifth. The other end of the capacitor 72 is connected to the center potential supply line 30 through the switching circuit 42 ₇ seventh is electrically disconnected from the ground potential supply line 22.

Thus, the switching operation of the second by the switch driving circuit 70 of the fifth to the eighth switch circuit 42 _{5-42 8,} center potential VC is the charge is applied and the ground potential supply line 22 at the first timing Is accumulated, the potential level of the first liquid crystal drive potential supply line 28 is set at the second timing with reference to the center potential supply line 30. As a result, the potential of the first liquid crystal driving potential supply line 28 becomes twice the value of the center potential VC.

According to such a charge pump circuit, only the switching currents of the _{fifth to eighth} switch circuits 425 to 428 are provided by the capacitor 72, and the current consumption can be reduced. Also, regardless of the capacitance value of the capacitor 72, the switching operation described above can boost the voltage to twice the center potential VC.

In the second booster circuit 16, like the first booster circuit 12 shown in FIG. 5, between the ND ₅ and the first liquid crystal drive potential supply line 28, the ND ₅ and the ground potential supply line A capacitor may be connected between the capacitors 22 and 22. In this case, the potential level can be doubled with high accuracy.

  Here, the charge pump circuit that performs double boosting has been described, but the present invention is not limited to this.

2.3.2 Example of cross-sectional structure FIG. 9 shows an example of a cross-sectional structure of a charge pump circuit formed on a substrate.

First, a p-type substrate 90 and p-well region, on the substrate 90, the high-concentration p ⁺ diffusion region 92, the high-concentration n ⁺ diffusion regions 94 and 96 are formed by being separated from each other, the switch circuits 42 ₈ eighth A certain n-type (second conductivity type) (MOS) transistor is formed. That is, the gate electrode 98 is formed on the channel region between the high concentration n ⁺ diffusion regions 94 and 96. High concentration p ⁺ diffusion region 92 and high concentration n ⁺ diffusion region 94 are electrically connected to ground potential supply line 22. The switch drive signal A is applied to the gate electrode 98. The high concentration n ⁺ diffusion region 96 becomes ND ₆ .

Further, p-type on p-type substrate 90, n-well region 100, 102, 104 is formed, the seventh by the respective well regions, sixth, fifth switch circuit 42 _7, 42 _6, 42 is ₅ (MOS) transistors are configured.

More specifically, in the n-well region 100, high-concentration p ⁺ diffusion regions 106 and 108 and a high-concentration n ⁺ diffusion region 110 are formed separately from each other. A gate electrode 112 is formed on a channel region between the high concentration p ⁺ diffusion regions 106 and 108. High-concentration n ⁺ diffusion region 106 is electrically connected to high-concentration p ⁺ diffusion region 96. High concentration p ⁺ diffusion region 108 and high concentration n ⁺ diffusion region 110 are electrically connected to center potential supply line 30. Switch drive signal XB is applied to gate electrode 112.

In the n-well region 102, high concentration p ⁺ diffusion regions 114 and 116 and a high concentration n ⁺ diffusion region 118 are formed separately from each other. A gate electrode 120 is formed on the channel region between the high concentration p ⁺ diffusion regions 114 and 116. High concentration p ⁺ diffusion region 114 is electrically connected to center potential supply line 30. The high concentration p ⁺ diffusion region 116 and the high-concentration n ⁺ diffusion region 118 is electrically connected to one another ND ₄ next. The switch drive signal XA2 is applied to the gate electrode 120.

In the n-well region 104, high-concentration p ⁺ diffusion regions 122 and 124 and a high-concentration n ⁺ diffusion region 126 are formed separately from each other. A gate electrode 128 is formed on a channel region between the high concentration p ⁺ diffusion regions 122 and 124. High concentration p ⁺ diffusion region 122 is electrically connected to ND ₄ . The high concentration p ⁺ diffusion region 124 and the high concentration n ⁺ diffusion region 126 are electrically connected to the first liquid crystal driving potential supply line 28 to which the potential level V3 is supplied. The switch drive signal XB2 is applied to the gate electrode 128.

  With this configuration, the charge pump circuit shown in FIG. 9 can be formed on a p-type (first conductivity type) substrate having a twin well structure.

  In FIG. 9, the charge pump circuit is formed by a twin-well structure formed on a p-type substrate. However, the present invention is not limited to this. May be formed. In this case, it is necessary to switch the p-type and the n-type in FIG. 9 and to invert the logic of the switch drive signals A, XB, XA2, and XB2.

2.4 Multi-Level Potential Generation Circuit 2.4.1 Configuration Example As shown in FIG. 8, the multi-level potential generation circuit 18 in the present embodiment includes a first liquid crystal driving potential supply line 28 and a center potential supply line 30. Is connected to a resistance element 74 which can be divided by an arbitrary ratio. Further, a resistance element 76 that can be resistance-divided at an arbitrary ratio is connected between the center potential supply line 30 and the ground potential supply line 22.

  Each of the resistance elements 74 and 76 is divided into three at an arbitrary ratio, and each of the resistance division potentials is connected to the + terminal of a voltage-follower-connected operational amplifier circuit 78, 80, 82, or 84. More specifically, the output terminal of the operational amplifier circuit 78 is fed back to its negative terminal and is connected to the second liquid crystal drive potential supply line 32 to which the potential level V2 is supplied. The output terminal of the operational amplifier circuit 80 is fed back to its negative terminal and is connected to a third liquid crystal driving potential supply line 34 to which the potential level V1 is supplied. The output terminal of the operational amplifier circuit 82 is fed back to its minus terminal and is connected to the fourth liquid crystal driving potential supply line 36 to which the potential level MV1 is supplied. The output terminal of the operational amplifier circuit 84 is fed back to its negative terminal and is connected to the fifth liquid crystal driving potential supply line 38 to which the potential level MV2 is supplied.

2.4.2 Set potential In the case of the MLS driving method, the potential levels V3, MV3 (VSS) and VC supplied to the first and fifth liquid crystal drive potential supply lines 28 and 22 and the center potential supply line 30 are as follows. The potential level is adjusted so as to have the following relationship.

For example, in the case of FIG. 2, the effective value voltage in one frame when the pixel is on is V _{ON (RMS)} , and the effective value voltage in one frame when the pixel is off is V _{OFF (RMS)} .

That is, since the potential difference between the scanning electrode and the signal electrode is applied to each pixel, the effective value voltage V _{ON (RMS)} by the MLS driving method with four simultaneously selected lines is expressed by the following equation (2). Can be expressed as

Similarly, the effective value voltage V _{OFF (RMS)} by the MLS driving method in which the number of simultaneously selected lines is 4 can be expressed by the following equation (3).

Here, v ₃ , v ₂ , and v ₁ are the potential differences from the potential levels V3, V2, and V1, respectively, based on the center potential VC. Further, v ₃ , v ₂ , and v ₁ are respectively equivalent to potential differences from potential levels MV3, MV2, and MV1 with reference to the center potential VC. Further, let N be the number of display lines.

Therefore, when the bias ratio a expressed by the equation (4) is used, v ₁ is expressed by the equation (5), so that V _{ON (RMS)} / V _{OFF (RMS)} becomes Equation 6) is obtained.

a = v ₂ / v ₃ (4)
v ₁ = v ₃ / 2a (5)

This equation (6) is equivalent to the brightness ratio between the ON pixel and the OFF pixel, and is also the contrast ratio. Therefore, when the value of the numerator V _{ON (RMS)} is large and the value of the denominator V _{OFF (RMS)} is small, the value of the expression (6) becomes maximum. That is, when the expression (6) becomes the maximum, the bias ratio a becomes the optimum bias ratio. Therefore, when the extreme value is obtained by differentiating equation (6), the optimum bias ratio is as shown in equation (7).

As described above, the resistance division points of the resistance elements 74 and 76 are adjusted so that the number of display lines N becomes v ₁ , v ₂ , and v ₃ as shown in Expression (7), and the potential level V1 (MV1), By determining V2 (MV2) and V3 (MV3), the contrast of the liquid crystal display can be maximized.

2.4.3 Voltage-follower-type operational amplifier circuit The multi-level potential generating circuit 18 in the present embodiment includes operational amplifier circuits 78, 80, 82, and 84 that are connected by voltage-follower connections to the resistance dividing points of the resistance elements 74 and 76. Connected. In such a configuration, it is necessary to increase the resistance in order to reduce power consumption. However, if the resistance-divided potential is applied to the electrodes for driving the liquid crystal as it is, the output impedance will increase, and the fluctuation when driving the liquid crystal will increase, thereby deteriorating the display quality of the liquid crystal. Therefore, the output impedance is reduced by connecting an operational amplifier circuit connected as a voltage follower as an impedance conversion means to each resistance dividing point. Therefore, even when the resistance elements 74 and 76 have high resistance, the liquid crystal display quality does not deteriorate.

(Constitution)
FIG. 10 shows a configuration example of the operational amplifier circuit 78 connected in a voltage follower according to the present embodiment.

  Here, the operational amplifier circuit (voltage follower type operational amplifier circuit) 78 connected to the voltage follower will be described, but the voltage follower type operational amplifier circuits 80, 82, and 84 have the same configuration.

  The voltage follower type operational amplifier circuit 78 is connected to the resistance division point of the resistance element 74, and operates as a common input using the resistance division potential level Vdiv between the potential level V3 and the center potential VC as a common input. And two differential amplifiers 130, 150.

  The voltage follower-type first differential amplifier circuit 130 includes a p-type transistor 132 and a p-type transistor 134 that forms a current mirror together with the p-type transistor 132. These p-type transistors 132 and 134 have the same size and the same capacity, and constitute a current mirror circuit.

  The first differential amplifier circuit 130 further includes an n-type transistor 136 connected in series to the p-type transistor 132 between the power supply level VDD and the ground level VSS, and a p-type transistor 136 between the power supply level VDD and the ground level VSS. And an n-type transistor 138 connected in series to the type transistor 134. The n-type transistors 136 and 138 are connected to the ground level VSS via the constant current source 140. These n-type transistors 136 and 138 have different capacities due to different sizes.

  The voltage-follower type second differential amplifier circuit 150 includes an n-type transistor 152 and an n-type transistor 154 that forms a current mirror with the n-type transistor 152. These n-type transistors 152 and 154 have the same size and the same capacity, and constitute a current mirror circuit.

  The second differential amplifier circuit 150 further includes a p-type transistor 156 connected in series to the n-type transistor 152 between the power supply level VDD and the ground level VSS, and n between the power supply level VDD and the ground level VSS. And a p-type transistor 158 connected in series to the type transistor 154. The p-type transistors 156 and 158 are connected to the power supply level VDD via the constant current source 160. These p-type transistors 156 and 158 have different capacities due to different sizes.

  From the connection point between the p-type transistor 132 and the n-type transistor 136 of the first differential amplifier circuit 130, a differential output signal is output as the first signal SS1, and the p-type transistor 142 operates.

  From a connection point between the n-type transistor 152 and the p-type transistor 156 of the second differential amplifier circuit 150, a differential output signal is output as the second signal SS2, and the n-type transistor 162 operates.

  The p-type transistor 142 and the n-type transistor 162 are connected in series between the power supply level VDD and the ground level VSS, and the potential between the p-type transistor 142 and the n-type transistor 162 supplies the potential level V2. Is supplied to the second liquid crystal drive potential supply line 32.

  Further, the first and second differential amplifier circuits 130 and 150 are provided with capacitors CC1 and CC2 for preventing oscillation and resistances R1 and R2 for electrostatic protection.

  The first differential amplifier circuit 130 includes a first current control circuit 146 including an n-type transistor 144 connected in parallel with the constant current source 140. A second signal SS2, which is a differential output signal of the second differential amplifier circuit 150, is supplied to the gate electrode of the n-type transistor 144, and as a result, the first current control circuit 146 generates the first differential signal. By controlling the constant current value of the dynamic amplifier circuit 130, the first signal SS1 is controlled to control the gate voltage of the p-type transistor 142.

  Similarly, the second differential amplifier circuit 150 includes a second current control circuit 166 including a p-type transistor 164 connected in parallel with the constant current source 160. The first signal SS1, which is the differential output signal of the first differential amplifier circuit 130, is supplied to the gate electrode of the p-type transistor 164. As a result, the second current control circuit 166 outputs the second differential signal. By controlling the constant current value of the dynamic amplifier circuit 150, the second signal SS2 is controlled to control the gate voltage of the n-type transistor 162.

  Note that when the output potential level V2 of the operational amplifier circuit 78 is stable, the n-type transistor 144 and the p-type transistor 164 are turned off and almost no current flows.

(Description of operation)
The voltage follower-type operational amplifier circuit according to the present embodiment can quickly transition to a stable state with a low power consumption and an output potential level.

<When the output potential level is lower than the stable state>
First, when the output potential level is lower than the stable state, the gate voltages of the n-type transistor 138 and the p-type transistor 158 become lower than the voltage in the original stable state.

In the first differential amplifier circuit 130, since the constant current source flows through the constant current source 140 and the gate voltage of the n-type transistor 138 decreases, the current I ₁₃₈ flowing through the n-type transistor 138 decreases, and the current I ₁₃₈ decreases accordingly. current I ₁₃₆ flowing through the mold transistor 136 increases.

  As a result, in the first differential amplifier circuit 130, the voltage of the first signal SS1 decreases, and the current flowing through the p-type transistor 142 increases.

On the other hand, in the second differential amplifier circuit 150, a constant current flows from the constant current source 160, and the sum of the currents I ₁₅₆ and I ₁₅₈ flowing through the p-type transistors 156 and 158 forming the differential pair is constant. is there. Then, as described above, due to the decrease in the gate voltage of p-type transistor 158, current I ₁₅₈ flowing in p-type transistor 158 increases, and current I ₁₅₆ flowing in p-type transistor 156 decreases accordingly.

  As a result, in the second differential amplifier circuit 150, the voltage of the second signal SS2 decreases, and the current flowing through the n-type transistor 162 decreases.

  Thus, the output potential level V2 of the operational amplifier circuit 78 rises toward a stable state.

  Incidentally, the gate voltage of the p-type transistor 142 is determined by its gate capacitance, the capacitor CC1 for preventing oscillation, and the electric charge stored in the wiring parasitic capacitance of the gate line L1. Similarly, the gate voltage of n-type transistor 162 is determined by the charge stored in its gate capacitance, capacitor CC2 for preventing oscillation, and the wiring parasitic capacitance of gate line L2. Therefore, the response to the change in the gate voltage is delayed due to the charge time stored in the charge. Therefore, the first and second current control circuits 146 and 166 improve the response of the change in the gate voltage of the transistor described above.

In other words, the current I ₁₅₆ flowing through the p-type transistor of the second differential amplifier circuit 150 is reduced, so that the reduced second signal SS2 is applied to the gate electrode of the n-type transistor 144 of the first differential amplifier circuit 130. Is applied. As a result, the current I ₁₄₄ flowing through the n-type transistor 144 decreases, and the first signal SS1 that is the gate voltage of the p-type transistor 142 is determined by the current flowing through the constant current source 140.

On the other hand, when the first signal SS1 decreases in the first differential amplifier circuit 130, the current _I164 flowing through the p-type transistor 164 of the second differential amplifier circuit 150 increases. As a result, the current flowing through the differential pair of the second differential amplifier circuit 150 and the current mirror circuit increases. That is, this corresponds to a case where the constant current value for driving the differential amplifier circuit increases, and as a result, the operation of the n-type transistor 162 can be hastened.

  Therefore, the time required to increase the output potential level V2 of the operational amplifier circuit 78 and transition to the stable state can be shortened.

  In particular, the steady current caused by the constant current sources 140 and 160 causes an increase in current consumption. Therefore, the constant current values of the constant current sources 140 and 160 are set to be as small as possible, and as described above, the current having the optimum value is supplied only at the time of the necessary stable output, thereby reducing the power consumption of the operational amplifier circuit. Can also be realized.

  Furthermore, in the first differential amplifier circuit 130, the n-type transistors 136 and 138 forming a differential pair have different capabilities. Hereinafter, for example, it is assumed that the capability of the n-type transistor 138 is higher than the capability of the n-type transistor 136.

  In this case, in a stable state in which the same current flows, the gate-source voltage of n-type transistor 138 may be lower than the gate-source voltage of n-type transistor 136. However, when the outputs of the first and second differential amplifier circuits 130 and 150 are short-circuited, the gate-source voltages of the n-type transistors 136 and 138 are equal. Therefore, the same current flows through n-type transistors 136 and 138, although n-type transistor 138 has the ability to flow more current. In this case, the gate potentials of the p-type transistors 132 and 134 decrease, and as a result, the potential of the first signal SS1 increases. This means that the voltage between the gate and the source of the p-type transistor 142 decreases, and the current flowing through the p-type transistor 142 can be reduced.

  On the other hand, in the second differential amplifier circuit 150 as well, there is a difference in performance between the p-type transistors 156 and 158 forming the differential pair, and the performance of the p-type transistor 158 is higher than that of the p-type transistor 156 In this case, in a stable state in which the same current flows, the gate-source voltage of the p-type transistor 158 may be lower than the gate-source voltage of the p-type transistor 156. However, when the outputs of the first and second differential amplifier circuits 130 and 150 are short-circuited, both the gate-source voltages of the p-type transistors 156 and 158 become equal. Therefore, the same current flows through p-type transistors 156 and 158, although p-type transistor 158 has the ability to flow more current. In this case, the gate potentials of the n-type transistors 152 and 154 decrease, and as a result, the potential of the second signal SS2 decreases. This means that the voltage between the gate and the source of the n-type transistor 162 decreases, and the current flowing through the n-type transistor 162 can be reduced.

  As described above, the outputs of the first differential amplifier circuit 130 as the p-type differential amplifier circuit and the second differential amplifier circuit 150 as the n-type differential amplifier circuit that operate based on the common input are short-circuited. Thus, the differential pair is configured by transistors having different capabilities, so that current consumption can be reduced.

<When the output potential level is higher than the stable state>
When the output potential level is higher than the stable state, the gate voltages of the n-type transistor 138 and the p-type transistor 158 become higher than the voltage in the original stable state.

In the first differential amplifier circuit 130, since the constant current source 140 flows through the constant current source 140 and the gate voltage of the n-type transistor 138 rises, the current I ₁₃₈ flowing through the n-type transistor 138 increases, and n The current I ₁₃₆ flowing through the type transistor 136 decreases.

  As a result, in the first differential amplifier circuit 130, the voltage of the first signal SS1 increases, and the current flowing through the p-type transistor 142 decreases.

On the other hand, in the second differential amplifier circuit 150, the current I ₁₅₈ flowing through the p-type transistor 158 decreases due to the increase in the gate voltage of the p-type transistor 158 as described above, and the current I ₁₅₈ flows accordingly through the p-type transistor 156. The current I ₁₅₆ increases.

  As a result, in the second differential amplifier circuit 150, the voltage of the second signal SS2 increases, and the current flowing through the n-type transistor 162 increases.

  Thus, the output potential level V2 of the operational amplifier circuit 78 decreases toward a stable state.

Here, the current I ₁₅₆ flowing through the p-type transistor of the second differential amplifier circuit 150 increases, so that the second signal SS2 whose voltage has increased increases the gate of the n-type transistor 144 of the first differential amplifier circuit 130. Applied to the electrodes. As a result, the current I ₁₄₄ flowing through the n-type transistor 144 increases, and the current flowing through the differential pair of the first differential amplifier circuit 130 and the current mirror circuit increases. That is, this corresponds to a case where the constant current value for driving the differential amplifier circuit increases, and as a result, the operation of the p-type transistor 142 can be hastened.

On the other hand, when the first signal SS1 rises in the first differential amplifier circuit 130, the current _I164 flowing through the p-type transistor 164 of the second differential amplifier circuit 150 decreases. At this time, the second signal SS2, which is the gate voltage of the n-type transistor 162, is determined by the current flowing through the constant current source 160.

  As described above, the time required for lowering the output potential level V2 of the operational amplifier circuit 78 to transition to the stable state is shortened.

  Also in this case, as described above, the outputs of the first and second differential amplifier circuits 130 and 150 that operate based on the common input are short-circuited to form a differential pair using transistors having different capabilities. Therefore, current consumption can be reduced.

  FIG. 11 shows an example of the operation of the operational amplifier circuit 78 shown in FIG.

As described above, when the output potential level V2 of the operational amplifier circuit 78 changes from the stable potential level to the positive side, the current _I144 flowing through the n-type transistor 144 of the first differential amplifier circuit 130 increases, Output potential level V2 is returned to a stable state. When the output potential level V2 changes from the stable state to the negative side, the current _I164 flowing through the p-type transistor 164 of the second differential amplifier circuit increases, and the output potential level V2 returns to the stable state.

This is because the consumption current of the operational amplifier circuit 78 is only the sum of the currents I ₁₄₀ and I ₁₆₀ by the constant current sources ₁₄₀ and _{160 in} the steady state, but when returning from the unstable state to the stable state, the n-type current is consumed. added current I ₁₆₄ by the current I _144, p-type transistor 164 by the transistor 144, a transition to a stable state is advanced. At this time, as I ₁₄₀ and I ₁₆₀ in the steady state are smaller, the current consumption of the operational amplifier circuit 78 can be reduced as a whole.

  As described above, the power supply circuit according to the present embodiment sets the potential regulated from the first boosted potential level VOUT obtained by increasing the power supply potential level on the basis of the ground level VSS as the center potential VC, and sets a plurality of levels of potentials. Since the regulator circuit is generated, the regulator circuit as the potential adjusting means does not need to have high withstand voltage, and an inexpensive process can be used. Further, when a twin-well process capable of reducing the cost is used, only the potential level on the positive side of the ground level VSS can be generated. In addition to realizing a low cost, it is possible to avoid problems in mounting.

3. First Modification The multi-value potential generation circuit applied to the power supply circuit according to the present embodiment is not limited to the one shown in FIG.

  FIG. 12 shows an outline of a configuration of a multi-level potential generation circuit according to a first modification.

  However, the same portions as those of the multi-level potential generation circuit 18 in the present embodiment shown in FIG.

  In the multi-level potential generation circuit 200 according to the first modification, the voltage follower-type operational amplifier circuit 202 shown in FIG. 10 is connected to the resistance division points of the resistance elements 74 and 76 set so as to satisfy Expression (7). 204 is connected.

  The output terminal of the operational amplifier circuit 202 is connected to the second liquid crystal drive potential supply line 32 that supplies the potential level V2 as it is. The output terminal of the operational amplifier circuit 204 is connected to the fifth liquid crystal driving potential supply line 38 that supplies the potential level MV2 as it is.

  Further, in the multi-level potential generation circuit 200 according to the first modification, the center potential supply line 30 and the fifth liquid crystal drive potential supply are provided between the center potential supply line 30 and the second liquid crystal drive potential supply line 32. Step-down circuits 210 and 212 are provided between the line 38 and the line 38, respectively.

That is, the step-down circuit 210 includes _{ninth to twelfth} switch circuits 42 _{9 to} 42 ₁₂ connected in series between the second liquid crystal driving potential supply line 32 and the center potential supply line 30, To a twelfth switch circuit 42 _{9 to} 42 ₁₂ .

Assuming that connection points of the _{ninth to} twelfth switch circuits 42 _{9 to} 42 ₁₂ are ND ₇ to ND ₉ , respectively, the step-down circuit 210 includes a capacitor 214 connected between ND ₇ and ND ₉ and a second It includes a capacitor 216 ₁ connected between the liquid crystal driving potential supply line 32 and ND _8, and a capacitor 216 ₂ connected between ND ₈ and the center potential supply line 30.

Incidentally, ND ₈ is connected to a third liquid crystal driving potential supply line 34 to the potential level V1 is supplied.

The switch drive circuit (not shown) is configured such that a period in which the ninth and eleventh switch circuits 42 ₉ and 42 ₁₁ are turned on and a period in which the tenth and twelfth switch circuits 42 ₁₀ and 42 ₁₂ are turned on are alternately repeated. Then, the _{ninth to twelfth} switch circuits 42 _{9 to} 42 ₁₂ are driven.

Such _{ninth to} twelfth switch circuits 42 _{9 to} 42 ₁₂ can be constituted by p-type (first conductivity type) MOS transistors, but can also be constituted by n-type MOS transistors. Any circuit having a switch function can be applied.

  Each switch drive signal of the step-down circuit 210 is similar to each switch drive signal generated by the first switch drive circuit 44 shown in FIG.

In such a step-down circuit 210, the first timing and the second timing are alternately repeated, so that the capacitors 214, 216 ₁ , and 216 ₂ have the same voltage applied to both ends of each of the capacitors 214, 216 ₁ , and 162 _2. , 216 ₁ and 216 ₂ are stabilized. As a result, the potential at the intermediate point between the capacitors 216 ₁ and 216 ₂ , that is, the potential level V 1 is converged to an intermediate potential between the potential level V ₂ of the first liquid crystal driving potential supply line 32 and the center potential VC.

Similarly, the step-down circuit 212 includes _{thirteenth to sixteenth} switch circuits 42 _{13 to} 42 ₁₆ connected in series between the center potential supply line 30 and the fifth liquid crystal drive potential supply line 38, To a sixteenth switch circuit 42 _{13 to} 42 ₁₆ .

Assuming that the connection points of the _{thirteenth to} sixteenth switch circuits 42 _{13 to} 42 ₁₆ are ND ₁₀ to ND ₁₂ , respectively, the step-down circuit 212 includes a capacitor 218 connected between ND ₁₀ and ND ₁₂ and a center potential supply. It includes a capacitor 220 ₁ connected between the line 30 and the ND _11, and a capacitor 220 ₂ connected between the ND ₁₁ and the second liquid crystal driving potential supply line 32.

The ND ₁₁ is connected to a fourth liquid crystal drive potential supply line 36 to which the potential level MV1 is supplied.

The switch drive circuit (not shown) is configured such that a period in which the thirteenth and fifteenth switch circuits 42 ₁₃ and 42 ₁₅ are turned on and a period in which the twelfth and sixteenth switch circuits 42 ₁₂ and 42 ₁₆ are turned on are alternately repeated. Then, the _{thirteenth to sixteenth} switch circuits 42 _{13 to} 42 ₁₆ are driven.

Such _{thirteenth to} sixteenth switch circuits 42 _{13 to} 42 ₁₆ can be constituted by p-type (first conductivity type) MOS transistors, but can also be constituted by n-type MOS transistors. Any circuit having a switch function can be applied.

  The respective switch drive signals of the step-down circuit 212 are the same as the respective switch drive signals generated by the first switch drive circuit 44 shown in FIG.

In such a step-down circuit 212, the first timing and the second timing are alternately repeated so that the capacitors 218, 220 ₁ , and 220 ₂ have the same voltage applied to both ends thereof. , 220 ₁ and 220 ₂ are stabilized. As a result, the potential at the intermediate point between the capacitors 220 ₁ and 220 ₂ , that is, the potential level MV 1 is converged to an intermediate potential between the center potential VC and the potential level MV 2 of the fifth liquid crystal driving potential supply line 38.

  With such a step-down circuit, the current flowing through the capacitor is eliminated, and only the current used for the switching operation is used, so that the current consumption can be reduced. Further, even when the capacitance value of the capacitor varies, the intermediate potential can be generated with high accuracy. Further, the number of operational amplifier circuits can be reduced.

4. Second Modification FIG. 13 shows an outline of a configuration of a multi-level potential generation circuit according to a second modification.

  However, the same portions as those of the multi-level potential generation circuit 18 of the present embodiment shown in FIG. 8 and the multi-level potential generation circuit 200 of the first modification shown in FIG.

  In the multi-level potential generation circuit 300 according to the second modification, the voltage follower-type operational amplifier circuit 302 shown in FIG. 10 is connected to the resistance dividing point of the resistance element 76 set so as to satisfy the expression (7). You. Note that the potential difference between the potential level V2 and the center potential VC is equivalent to the potential difference between the potential level MV2 and the center potential VC.

  The output terminal of the operational amplifier circuit 302 is connected to a fifth liquid crystal driving potential supply line 38 that supplies the potential level MV2 as it is.

  The multi-level potential generation circuit 300 according to the second modification performs the double boosting shown in FIG. 5 based on the potential level MV2 supplied to the fifth liquid crystal driving potential supply line 38, and Includes a step-up circuit 304 and step-down circuits 210 and 212 that generate V2.

  Boosting circuit 304 doubles the potential difference between center potential VC and potential level MV2 to generate potential level V2. Step-down circuit 210 generates an intermediate potential of a potential difference between potential level V2 and center potential VC as potential level V1. Step-down circuit 212 generates an intermediate potential of a potential difference between potential level MV2 and center potential VC as potential level MV1.

More specifically, the booster circuit 304 includes a seventeenth to a twentieth switch circuit connected in series between the second liquid crystal driving potential supply line 32 and the fifth liquid crystal driving potential supply line 38. 42 _{17 to} 42 _20, and a switch drive circuit (not shown) for driving the seventeenth to twentieth switch circuits 42 _{17 to} 42 ₂₀ on / off.

Assuming that the connection points of the seventeenth to twentieth switch circuits 42 _{17 to} 42 ₂₀ are ND ₁₃ to ND ₁₅ , respectively, the booster circuit 304 includes a capacitor 306 connected between ND ₁₃ and ND ₁₅ , It includes a capacitor 308 ₁ connected between the liquid crystal driving voltage supply line 32 and the ND _14, the ND ₁₄ and a capacitor 308 ₂ connected between the second liquid crystal driving voltage supply line 32.

The ND ₁₄ is connected to the center potential supply line 30 to which the center potential VC is supplied.

The switch drive circuit (not shown) is configured such that a period for turning on the seventeenth and nineteenth switch circuits 42 ₁₇ and 42 ₁₉ and a period for turning on the eighteenth and twentieth switch circuits 42 ₁₈ and 42 ₂₀ are alternately repeated. to drive the switching circuit 42 _{17-42 20} 17th 20th.

Such seventeenth to twentieth switch circuits 42 _{17 to} 42 ₂₀ can be constituted by p-type (first conductivity type) MOS transistors, but can also be constituted by n-type MOS transistors. Any circuit having a switch function can be applied.

  Each switch drive signal of the booster circuit 304 is the same as each switch drive signal generated by the first switch drive circuit 44 shown in FIG.

In such step-up circuit 304, by repeating the first timing and the second timing alternately, so that the voltage applied to both ends of the capacitor 306, 308 _1, 308 ₂ equal, capacitor 306 , 308 _1, 308 ₂ are charges accumulated in is stabilized. As a result, the potential level V2 which is determined by the voltage across capacitor _3081, so the voltage across capacitor 308 _2, the potential of the potential level V2 is converged.

  Such a booster circuit can similarly generate seven power supply levels. In this case, in addition to the effects of the first modification, it is possible to further reduce the number of voltage follower type operational amplifier circuits.

  In the second modification, a resistance element 76 is provided between the center potential supply line 30 and the ground potential supply line 22, and the voltage obtained by dividing the resistance is output as MV2 by the voltage follower type operational amplifier circuit 302. But not limited to this. For example, a resistance element is provided between the center potential supply line 30 and the first liquid crystal drive potential supply line 28, and a voltage obtained by dividing the resistance is output as V2 by a voltage follower-type operational amplifier circuit. It is also possible to generate the level MV2 and generate the potential levels V1 and MV1 in the step-down circuits 210 and 212.

  The present invention is not limited to the above-described embodiment and the first and second modifications, and various modifications can be made within the scope of the present invention.

  Further, in the present embodiment, the first and second modified examples have been described as generating seven power supply levels, but the number of power supply levels is not limited to this. For example, only one level corresponding to the center potential VC may be generated from the power supply level VDD and the ground level VSS. A level may be generated. Alternatively, eight or more power supply levels may be generated.

  Further, the power supply circuit having the above-described configuration can be applied to electronic devices including a liquid crystal device, for example, various electronic devices such as a mobile phone, a game device, and a personal computer.

FIG. 1 is a schematic explanatory diagram illustrating a main part of a configuration of a liquid crystal device to which a power supply circuit according to an embodiment is applied. FIG. 2 is a waveform chart showing an example of a driving waveform in the liquid crystal panel shown in FIG. 1. FIG. 1 is a configuration diagram illustrating an outline of a configuration of a power supply circuit according to an embodiment. FIG. 3 is an explanatory diagram schematically showing the operation of the power supply circuit in the embodiment. FIG. 2 is a configuration diagram illustrating an example of a configuration of a first booster circuit according to the present embodiment. FIG. 4 is a waveform chart illustrating an example of each switch drive signal generated by a first switch drive circuit according to the embodiment. FIG. 2 is a circuit diagram illustrating an example of a configuration of a regulator circuit according to the embodiment. FIG. 3 is a configuration diagram illustrating an example of a configuration of a second booster circuit and a multi-level potential generation circuit according to the embodiment. FIG. 3 is a cross-sectional view illustrating an example of a cross-sectional structure of a charge pump circuit according to the present embodiment formed on a substrate. FIG. 2 is a circuit diagram illustrating a configuration example of a voltage-follower-connected operational amplifier circuit according to the embodiment. 11 is an explanatory diagram illustrating an example of an operation of the operational amplifier circuit illustrated in FIG. FIG. 9 is a circuit diagram illustrating an outline of a configuration of a multi-level potential generation circuit according to a first modification. FIG. 15 is a circuit diagram illustrating an outline of a configuration of a multi-level potential generation circuit according to a second modification.

Explanation of reference numerals

2 liquid crystal device, 4 liquid crystal panel, 6 scan electrode drive circuit (common driver),
8 signal electrode drive circuit (segment driver), 9 drive control circuit,
10 power supply circuit, 12 first booster circuit, 14 regulator circuit,
16, second booster circuit, 18, 200, 300 multi-level potential generation circuit,
20 power supply potential supply line, 22 ground potential supply line, 24 first potential supply line,
26 a second potential supply line; 28 a first liquid crystal drive potential supply line;
30 a center potential supply line, 32 a second liquid crystal drive potential supply line,
34 a third liquid crystal drive potential supply line; 36 a fourth liquid crystal drive potential supply line;
38 5th liquid crystal drive potential supply line, 42 _{1 to} 42 ₂₀ 1st to 20th switch circuits,
44 a first switch driving circuit,
46,48 _1, 48 _2, 62,72,214,216 _1, 216 _2, 218, 220 _1, 220 _2, 306, 308 _1, 308 ₂ capacitors,
50, 52, 60, 132, 134, 142, 144, 156, 158, 164 p-type (first conductivity type) MOS transistors,
54, 56, 58, 64, 136, 138, 152, 154, 162 n-type (second conductivity type) MOS transistors,
66, 74, 76 resistance element, 70 second switch drive circuit,
78, 80, 82, 84, 202, 204, 302 (voltage follower type) operational amplifier circuit, 90 p-type substrate,
92, 106, 108, 114, 116, 122, 124 high concentration p ⁺ diffusion region,
94, 96, 110, 118, 126 high concentration n ⁺ diffusion regions,
98, 112, 120, 128 gate electrode,
100, 102, 104 n-well region, 130 first differential amplifier circuit,
140, 160 constant current source, 146 first current control circuit,
150 second differential amplifier circuit, 166 second current control circuit,
210, 212 step-down circuit, 304 step-up circuit, C0-Cm scan electrode,
ND ₁ to ND ₁₅ connection point, S0 to Sn signal electrodes,
V1, V2, V3, MV1, MV2, MV3 potential level,
VC center potential, VDD power supply level, VOUT first boosted potential level,
Vref reference potential level, VSS ground level

Claims (14)

A power supply circuit for generating a plurality of potentials,
A third potential, which is connected to first and second power supply lines for supplying first and second potentials and is boosted based on a difference between the first and second potentials, is supplied to the third power supply line. A first booster circuit;
A potential adjustment circuit connected to the first and third power supply lines and supplying a fourth potential, which is a constant potential generated based on a difference between the first and third potentials, to a fourth power supply line;
A second booster circuit connected to the first and fourth power supply lines and supplying a fifth potential boosted based on a difference between the first and fourth potentials to a fifth power supply line;
A multi-level potential generation circuit connected to the first, fourth, and fifth power supply lines and configured to generate a plurality of potentials based on a difference between the first, fourth, and fifth potentials;
A power supply circuit comprising: In claim 1,
The power supply circuit, wherein the multi-level potential generation circuit supplies the fourth potential as a center potential of a plurality of potentials supplied to a liquid crystal device. In claim 1 or 2,
At least one of the first and second booster circuits includes:
A first to fourth switch circuits connected in series between a boosted power supply line to which a boosted potential is supplied, and a power supply line on a lower potential side of the two connected power supply lines;
The second switch circuit is connected to a first switch circuit connected to the boost power supply line, the third switch circuit is connected to the second switch circuit, and the third switch circuit is connected to the low switch circuit. A capacitor connected in parallel with the second and third switch circuits when the fourth switch circuit is connected to a power supply line that supplies a potential;
The first and third switch circuits and a timing signal generation circuit that generates drive signals for the first to fourth switch circuits so that the second and fourth switch circuits are turned on alternately. A power supply circuit characterized by including a charge pump circuit. In claim 3,
The first to fourth switch circuits are twin wells each including a first conductivity type well connected to the first power supply line, and a second conductivity type well connected to the fifth power supply line. A power supply circuit having a structure. In any one of claims 1 to 4,
The multi-value potential generation circuit includes:
A first voltage dividing circuit for dividing the difference between the first and fourth potentials by resistance;
A second voltage divider for dividing the difference between the fourth and fifth potentials by resistance;
A voltage-follower-connected first operational amplifier circuit connected to the potential divided by the first voltage divider circuit;
A voltage-follower-connected second operational amplifier circuit connected to the potential divided by the second voltage divider circuit;
A power supply circuit comprising: In any one of claims 1 to 4,
The multi-value potential generation circuit includes:
A first operational amplifier circuit in which a difference between the first and fourth potentials is connected to a resistance-divided potential, and a voltage-follower-connected first operational amplifier circuit for supplying a sixth potential;
A voltage-follower-connected second operational amplifier circuit that is connected to a potential obtained by dividing the difference between the fourth and fifth potentials and that supplies a seventh potential;
A first step-down circuit for generating an eighth potential stepped down based on a difference between the fourth and sixth potentials;
A second step-down circuit that generates a ninth potential that is stepped down based on the difference between the fourth and seventh potentials. In any one of claims 1 to 4,
The multi-value potential generation circuit includes:
A difference between the first and fourth potentials or a difference between the fourth and fifth potentials is connected to a resistance-divided potential, and a voltage-follower-connected first operational amplifier circuit for supplying a sixth potential; ,
A third booster circuit that generates a seventh potential boosted in the fourth potential direction based on the difference between the fourth and sixth potentials;
A first step-down circuit for generating an eighth potential stepped down based on a difference between the fourth and sixth potentials;
A second step-down circuit that generates a ninth potential that is stepped down based on the difference between the fourth and seventh potentials. In any one of claims 5 to 7,
The first or second operational amplifier circuit includes:
A first conductivity type transistor having a gate supplied with a first differential output and a source supplied with the second potential;
A second conductivity type transistor having a gate supplied with a second differential output, a source supplied with the first potential, and a drain connected to the drain of the first conductivity type transistor;
A first conductivity type differential amplifier circuit that generates the first differential output based on a potential difference between the resistance-divided potential and a potential of a drain of the first or second conductivity type transistor;
A second conductivity type differential amplifier circuit that generates the second differential output based on a potential difference between the resistance-divided potential and a potential of a drain of the first or second conductivity type transistor;
A first current control circuit that controls a constant current value of the differential amplifier circuit of the first conductivity type based on the second differential output;
A second current control circuit that controls a constant current value of the second conductivity type differential amplifier circuit based on the first differential output;
A power supply circuit comprising: In claim 8,
The first and second conductivity type differential amplifier circuits are characterized in that the resistance-divided potential and the drain potential of the first or second conductivity type transistor are supplied to the gates of transistors having different capacities. Power circuit. A first conductivity type transistor having a gate supplied with a first differential output and a source supplied with a second potential;
A second conductivity type transistor having a gate supplied with a second differential output, a source supplied with a first potential, and a drain connected to the drain of the first conductivity type transistor;
A first conductivity type differential amplifier circuit for generating the first differential output based on a potential difference between a given differential input potential and a potential of a drain of the first or second conductivity type transistor;
A second conductive type differential amplifier circuit for generating the second differential output based on a potential difference between a given differential input potential and a potential of a drain of the first or second conductive type transistor;
A first current control circuit that controls a constant current value of the differential amplifier circuit of the first conductivity type based on the second differential output;
A second current control circuit that controls a constant current value of the second conductivity type differential amplifier circuit based on the first differential output;
An operational amplifier circuit comprising: In claim 10,
In the first and second conductivity type differential amplifier circuits, the given differential input potential and the drain potential of the first or second conductivity type transistor are supplied to the gates of transistors having different capabilities. An operational amplifier circuit characterized by the following. A voltage dividing circuit for dividing a given potential;
The operational amplifier circuit according to claim 10 or 11, wherein the potential divided by the voltage divider circuit is supplied as the given differential input potential.
A power supply circuit comprising: A power supply circuit according to any one of claims 1 to 9 and 12,
A liquid crystal panel in which a plurality of scanning electrodes and a plurality of signal electrodes are arranged to intersect,
A scan electrode drive circuit that receives power supply from the power supply circuit and drives the scan electrodes;
A signal electrode drive circuit that receives power from the power supply circuit and drives the signal electrode;
A liquid crystal device comprising:   An electronic apparatus comprising the liquid crystal device according to claim 13.

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