JP2000106530A - Error correction method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fast detect and correct errors by detecting the error of a line that undergone the second correction of error after the second correction of error of another line set in the 1st direction and simultaneously with the second correction of error of the next line. SOLUTION: The 1st error correction is carried out in a certain error correction block by an ECC(error correction code) circuit 5 in the direction of an inside code parity PI. In other words, the errors of information symbols are successively corrected by the parity PI on every line in the PI direction. After these errors are corrected, the error correction is carried out by the circuit 5 in the direction of an outside code parity PO. After the error correction is over in the PO direction, the second error correction is carried out by the circuit 5 in the Pi direction. An EDC(error detection code) circuit 6 detects the errors in the PI direction in parallel to the 2nd error correction of the PI direction. That is, the errors of information symbols are successively checked on every line in the PI direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction method and an apparatus therefor, and more particularly, to an error correction method using a Reed-Solomon code and an apparatus therefor.

[0002]

2. Description of the Related Art CD (Compact Disc), DVD (Digita
l In digital data transmission processing environments such as optical disc recording / reproducing devices such as Video Disc) and MO (Magneto Optic), digital transmission systems, and computer peripheral devices, data errors such as random errors and burst errors are reduced. In general, an error correction code ECC (Error Correction Code) and an error detection code ED
Add redundant data such as C (Error Detection Code)
Error correction is being performed. Especially recently, along with the improvement of the data processing capability on the receiving side of digital data,
An error correction code having a high correction capability has been used. A representative example of such an error correction code is a long distance Reed-Solomon code having a large code length.

An error correction method using Reed-Solomon codes uses an error correction block in which an error correction code is added to digital data (information symbols) that are product-coded. More specifically, the error correction block has an outer code parity (PO) added in the vertical direction of the information symbol and an inner code parity (PI) added in the horizontal direction of the information symbol. .

[0004]

A conventional error correction device is a DRAM which stores error correction blocks as described above.
(Dynamic Random Access Memory) is accessed in block units. That is, the conventional error correction device first reads the data of the error correction block from the DRAM and corrects the error.
Writing back to RAM (ECC process). After the ECC processing, the error correction device reads out the data of the error correction block from the DRAM again, detects the presence or absence of an error, and simultaneously descrambles the data, and writes the data back to the DRAM (EDC / descramble processing). As described above, the conventional error correction device has a large number of accesses to the DRAM, and has been a bottleneck for improving the real-time property.

The present invention has been made to solve such a problem, and an object of the present invention is to provide an error correction method and apparatus for performing error correction and error detection at high speed.

Another object of the present invention is to provide an error correction method and an error correction method in which the number of accesses to a memory is small.

[0007]

According to one aspect of the present invention, first and second error correction codes are added to product-coded information symbols in first and second directions, respectively. An error correction method using an error correction block comprises the steps of: performing error correction for each line in a first direction; and performing error correction for each line in a second direction after correcting the error in the first direction. Performing error correction again for each line in the first direction after error correction in the second direction, and simultaneously performing error correction for one line in the first direction and re-error correction for the next line at the same time. Detecting an error in one line after the re-error correction.

In this error correction method, when the error correction of one line is completed, the error detection of the corrected line is performed in parallel with the error correction of the next line. Therefore, error correction and error detection are performed at high speed, and the number of accesses to the memory storing the correction block is reduced.

According to another aspect of the present invention, an error correction block obtained by adding first and second error correction codes to product-coded information symbols in first and second directions, respectively, is provided. The error correction device connected to the stored memory includes an error correction circuit and an error detection circuit. The error correction circuit performs error correction for each line in the first direction, performs error correction in the first direction, performs error correction for each second line, performs error correction in the second direction, and again performs first error correction. Error correction is performed for each line in the direction of. The error detection circuit detects the error of one line after the re-error correction, simultaneously with the re-error correction of one line in the first direction by the error correction circuit.

Preferably, the error correction circuit supplies the results of the error correction in the first and second directions to the memory, and supplies the result of the re-error correction in the first direction to the error detection circuit.

In this error correction device, when the error correction of one line is completed by the error correction circuit, the error of the corrected line is detected by the error detection circuit in parallel with the error correction of the next line. Therefore, error correction and error detection are performed at high speed. Further, since the error correction circuit directly supplies the result of the re-error correction to the error detection circuit without passing through the memory, the number of accesses to the memory is reduced.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an error correction device according to an embodiment of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

FIG. 1 is a block diagram showing an entire configuration of an error correction device according to an embodiment of the present invention.

Referring to FIG. 1, error correction LSI 1 has a D
Connected to RAM2 and CPU3. Error correction LSI
1 is a demodulation circuit 4, an ECC circuit 5, and an EDC circuit 6.
, A descramble circuit 7, a host interface 8, and an access controller 9 for correcting errors in data read from a recording medium, and supplying the corrected data to an AV decoder or the like. When this error correction device is used for digital communication, an error correction LSI 1
Performs error correction of data transmitted from the network and supplies the corrected data to a personal computer or the like.

The demodulation circuit 4 demodulates data read from the recording medium, and writes product code data to the DRAM 2 via the access controller 9. The ECC circuit 5
After reading data from the AM 2 via the access controller 9 and performing error correction, only the corrected data is written back to the DRAM 2 via the access controller 9. The ECC circuit 5 supplies the data corrected in the second PI direction to the EDC circuit 6 and the descrambling circuit 7 as described later. The EDC circuit 6 detects an error in the data supplied from the ECC circuit 5. After descrambling the data supplied from the ECC circuit 5, the descrambling circuit 7 writes the descrambled data back to the DRAM 2 via the access controller 9. The host interface 8 reads data from the DRAM 2 via the access controller 9 and supplies the data to an AV decoder or the like. The access controller 9 performs arbitration (arbitration) for access requests from the demodulation circuit 4, the ECC circuit 5, the descrambling circuit 7, and the host interface 8, and performs access to the DRAM 2 according to a predetermined priority. To give permission.

The DRAM 2 can store error correction blocks as described later. The CPU 3 controls the error correction LSI 1 to perform the above operation.

FIG. 2 shows the configuration of the error correction block stored in the DRAM 2. Referring to FIG. 2, an outer code parity PO is added in the vertical direction to the product-coded m × n information symbol, and an inner code parity PI is added in the horizontal direction of the information symbol and the PO parity. You. The PI parity is obtained by a calculation in the horizontal (PI) direction, and the PO parity is obtained by a calculation in the vertical (PO) direction. PI
Is information length = n, inspection length = k (where code length (n +
k) is a Reed-Solomon code of 255 or less). P
O is information length = m, inspection length = 1 (where code length (m +
l) is a Reed-Solomon code of 255 or less).

The relationship between ECC and EDC is based on CD-ROM
In the case of format, one series of EDC for one sector
, And an ECC operation of one block is performed on it. Generally, the sector size is 512
Since the code length becomes / 1024/2048 bytes, if the code efficiency of the Reed-Solomon code is increased, that is, if the code length is increased, the size of m × n in the configuration of FIG. 2 is increased, and as shown in FIG. A plurality of sectors can be included in a block. The configuration of each sector is the same as in the above-described CD-ROM format.
As shown in FIG. 4, a synchronization signal, a sector address, user data (512/1024/2048 bytes), EDC
/ ECC etc. Here, the EDC is formed in sector units, and therefore, a plurality of EDCs exist in one ECC block.

For example, if m = 192 and m × n information symbols are divided into 16 sectors, each sector has 12 sectors.
Consists of lines. Therefore, 16 EDCs exist in one error correction block.

Next, the operation of the error correction device configured as described above will be described. FIG. 5 is a time chart showing a pipeline operation of the error correction device. FIG.
(A) shows ECC processing and EDC processing for one error correction block. FIG. 5B shows PI
ECC processing in the second direction and EDC parallel to this
The details of the process are shown with the data input stage (IN) and the data output stage.

First, in the data input stage, input data is demodulated by the demodulation circuit 4 and the access controller 9
Is written to the DRAM 2 via the. As a result, DRA
The error correction block shown in FIG. 2 is stored in M2 for each line.

Subsequently, in the ECC stage, error correction is performed on the error correction block stored in the DRAM 2 line by line.

As shown in FIG. 5A, for one error correction block, first, the PI
The first error correction is performed in the direction. That is, PI
The error of the information symbol is sequentially corrected by the PI parity for each line in the direction. After error correction in PI direction, EC
Error correction is performed in the PO direction by the C circuit 5. That is, the error of the information symbol is sequentially corrected by the PO parity for each line in the PO direction. After the error correction in the PO direction, the ECC circuit 5 performs the second error correction in the PI direction again. In parallel with the second error correction in the PI direction, the EDC circuit 6 performs error detection in the PI direction. That is, the information symbols are sequentially checked for errors in each line in the PI direction. As described above, the ECC process performs error correction in the order of PI direction → PO direction → PI direction, and the EDC process is performed in parallel with the second ECC process in the PI direction.

More specifically, the ECC processing in any direction is composed of a syndrome operation stage, a polynomial operation stage, a Chien search stage, and an error correction stage, as shown in FIG. . However, PI
During the second ECC processing in the direction, the EDC / descrambling stage exists as shown in FIG.
EDC during the first ECC processing in the PO direction and the ECC processing in the PO direction
/ There is no descramble stage.

The ECC circuit 5 first reads one line of data in the PI direction from the DRAM 2 and calculates a coefficient _Sj of a syndrome polynomial S (x) defined by the following equation.

[0026]

(Equation 1)

Here, equation (1) represents the coefficient S _j of the syndrome polynomial, and equation (2) represents the syndrome polynomial S
(X) itself is displayed. Hi in equation (1)
Is the code length, α is the element of the Galois field GF (2 ⁸ ), _Bi is the code symbol, and t is the minimum distance.

Next, based on the coefficients S ₀ , S ₁ ,..., S _2t-1 of the syndrome polynomial S (x), the ECC circuit 5 _calculates an error location polynomial σ (x ) And the coefficient of the error numerical polynomial ω (x).

[0029]

(Equation 2)

Here, equations (3) and (4) represent the error locator polynomial σ (x), and equations (5) and (6) represent the error numerical polynomial ω (x). j _i (i = 1,..., t−
1) indicates an error location.

[0031]

(Equation 3)

Here, as a method for calculating the coefficients of the error position polynomial and the error numerical polynomial from the coefficients (S _2t−1 , S _2t-2 ,..., S ₀ ) of the syndrome polynomial, , Euclidean algorithm or the like, but any method may be used.

Next, the ECC circuit 5 calculates an error pattern. J _i that satisfies the expressions (3) and (4) represents the i-th error position. By calculating the expression (7) for the j _i , the error pattern e _i is obtained. The method of determining whether or not σ (x) = 0 holds to determine j _i is known as the Chien search method.

On the other hand, σ ′ (x) in the equation (8) is
Represents the formal derivative of (x) and is defined by:

[0035]

(Equation 4)

The elements listed in the following equations in the above equations (6), (7) and (8) are generated by the ECC circuit 5.

[0037]

(Equation 5)

The error pattern e _{i in} equation (9) is also EC
Generated by the C circuit 5. Then, only when the equation (7) holds, the information symbol is corrected.

In the second ECC processing in the PI direction, more specifically, after the ECC circuit 5 corrects the error in the first line in the PI direction according to the above-described procedure, the EDC circuit 6
Immediately perform the EDC processing on the corrected first line in the PI direction. The EDC processing of this first line
This is performed simultaneously with the error correction in the ECC processing of the second line.

Similarly, the ECC circuit 5 sets the EC of the second line to
After performing the C processing, the EDC circuit 6 immediately performs the EDC processing on the corrected second line.

As described above, the EDC circuit 6 has 11 lines of E lines.
By performing DC processing, one ED for one sector
C can be determined. Thus, the EDC circuit 6
Obtains 16 EDCs, thereby completing the EDC processing for one error correction block.

Here, the ECC circuit 5 performs the first operation in the PI direction.
For the second ECC process and the PO direction ECC process, data is read from the DRAM 2 line by line, or data is written to the DRAM 2 line by line, but after the second ECC process in the PI direction. Data is not supplied to the DRAM 2 and the EDC
Supply to circuit 6. Therefore, the EDC circuit 6
Instead of reading data from AM2, EDC processing is performed on data after ECC processing supplied for each line from ECC circuit 5.

It should be noted that 1 is sent from the ECC circuit 5 to the EDC circuit 6.
The data after the second ECC process in the PI direction supplied for each line is also supplied to the descramble circuit 7. Accordingly, the descrambling circuit 7 descrambles the data supplied line by line from the ECC circuit 5 in parallel with the EDC circuit 6, and writes the data into the DRAM 2.

As described above, according to the embodiment of the present invention, since the EDC process is multiplexed with the second ECC process in the PI direction, the EDC process is performed after the end of the second ECC process in the PI direction. Error correction and error detection can be performed at a higher speed than in the conventional method.

Further, the data after the second ECC processing in the PI direction is directly supplied from the ECC circuit 5 to the EDC circuit 6 without passing through the DRAM 2, so that the number of accesses to the DRAM 2 can be reduced. As a result, ECC
Access to the DRAM 2 from other than the circuit 5 and the descramble circuit 7 is easily permitted, and higher-speed real-time processing can be performed. Further, since the number of accesses to the DRAM 2 is reduced, power consumption can be reduced.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0047]

As described above, according to the present invention, after the re-error correction of one line in the first direction, the re-error correction of the next line and the error of the line after the re-error correction are detected simultaneously. Therefore, error correction and error detection can be performed at high speed, and the number of accesses to the memory can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an error correction device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an error correction block stored in a DRAM in FIG. 1;

FIG. 3 is a diagram showing a configuration of a sector in an m × n information symbol in FIG. 2;

FIG. 4 is a diagram showing a format of each sector in FIG. 3;

FIG. 5 is a time chart showing a pipeline operation of the error correction device shown in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Error correction LSI 2 DRAM 5 ECC circuit 6 EDC circuit

Claims (3)

[Claims] 1. An error correction method using an error correction block obtained by adding first and second error correction codes to a product-coded information symbol in first and second directions, respectively. Performing error correction for each line in the first direction; performing error correction for each line in the second direction after correcting the error in the first direction; After the correction, performing the error correction again for each line in the first direction, and after the re-error correction of one line in the first direction, simultaneously with the re-error correction of the next line, The last one
Detecting an error in two lines. 2. An error connected to a memory storing an error correction block obtained by adding first and second error correction codes to a product-coded information symbol in first and second directions, respectively. A correction device for performing error correction for each line in the first direction, performing error correction for each line in the second direction after correcting the error in the first direction, and performing error correction for each line in the second direction. An error correction circuit for performing error correction again for each line in the first direction after the error correction, and a re-error for the next line after the error correction circuit corrects one line in the first direction again by the error correction circuit. And an error detection circuit for detecting an error of one line after the re-error correction at the same time as the correction. 3. The error correction circuit supplies a result of the error correction in the first and second directions to the memory, and supplies a result of the re-error correction in the first direction to the error detection circuit. The error correction device according to claim 2, wherein