JPS63255876A - Method for detecting code error - Google Patents

Abstract

PURPOSE:To attain the high speed of an error detecting processing and the error detection of data before the transfer of the data from a buffer memory to a host computer by using the read-solomon code of a byte unit as a CRC code for detecting an error and executing the CRC processing in parallel to the error correction of data. CONSTITUTION:As the error detecting code of a recording and reproducing device equipped with an optical disk, a read-solomon code for detecting the error of a byte unit is used, the (m) pieces of data of the B area of a buffer memory 5 and a parity for detecting the error of the P pieces of byte units of the A area of the buffer memory 5 are divided with a generating function specified beforehand and the error is detected according to the fact whether a remainder is zero or non-zero. Thus, simultaneously when the error correction is completed, CRC (Cyclic Redundancy Check) checking is completed, the error can be detected at high speed and the error detection checking can be executed before the data are transferred from the buffer memory to the host computer.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an apparatus for detecting code errors in data on an optical disc.

2. Description of the Related Art In recent years, optical disk devices have been actively developed, and code error correction technology has been used to keep the actual error rate of reproduced data sufficiently low.

In this case, a Reedon-Romon code is often used as the error correction code. Although this code can detect and correct errors, it is known that erroneous detection and correction of errors occur with a certain probability.

Therefore, in order to improve reliability against data errors, an error detection code is added to the entire data (excluding error correction parity) in addition to the above error correction.

FIG. 3 shows a block diagram of a portion related to conventional data error detection and correction. In FIG. 3, 21 is a host computer, 22 is an interface, 23 is a false detection code generator and checker, 24 is a buffer memory, and 26
26 is an error correction circuit, 26 is a digital modulation/demodulation circuit, and 27 is a recording medium.

Next, FIG. 2 shows the data arrangement of the data portion of the sector of the optical disc. In FIG. 2, Di2. is byte data, ``ik'' is an error correction code, and 00 to C3 are error detection codes.

An overview of signal processing will be explained using FIGS. 2 and 3.

First, when recording data, data DO, 103, Dl, 103 . D2,1
03, """ ID4.., D5.. are stored in the buffer memory 24 through the interface 22, and in parallel, the error detection code C is generated by the error detection code generator 23.
8 to C3 are calculated and similarly stored in the buffer memory 24.

Next, data D regarding each horizontal row in FIG. 2 is stored in the buffer memory 24. 1゜3D0,1o2...,D
DO, 0, 1, 103°... D... DDl, 102
+1.0. +5,103.5,102.
”'..., D5.., D6,1゜3, D6.1
゜2. ...ID6,1. C3'...

D9,103, D9,102, """t D9
,1,co error correction code EO,15,E
O, 14, “”” l EO, 0, El, 16. El
, 14°..., El,. ,...T E
5,15. E5,14. ......, E6. . .

E6,15. E6,14. ......, E6. . ,
・・・・・・T E9,15. E9,14°...
..., E9° are respectively calculated by the error correction circuit 25,
Similarly, it is stored in the buffer memory 24.

These data are Eiji-DO, 103, Dl, 103
．． D2,103゜””” + D9,103, DO,
102, Dl, 102. D2,102. ””” ID
9,102. """l EO,0,Ej ,O,E2
,0. """l E9,0 are recorded on the recording medium 27 (disc) through the digital modulation circuit 26.

On the other hand, during reproduction, the data reproduced from the recording medium 27 is passed through the digital demodulation circuit 2e and sent to the buffer memory 2.
It is stored at the same address as when recording 4. Next, the error correction circuit 25 executes error correction processing on the data in each horizontal row in FIG. 2, and finally all the data DO, 103, D1
, 103. D2,103. ``''''tDDD and the error detection codes C0 to C3 are 3.0. 4, 0. 5.0, and an error check is performed by the error 9 detection code checker 23. Here, error correction processing for each horizontal row is performed. On the other hand, an error check is performed when the correction capacity is exceeded, or when the correction process is executed but incorrect detection or correction is made.As an error detection code, a 16th or 32nd order binary type code is used. cyclic redundancy check code (
(generally called CRC) is often used.

Problems to be Solved by the Invention However, in the method described above, it is necessary to perform a CRC check after all error correction processing is completed, which impedes high-speed processing and prevents data transfer from the buffer memory to the host after error correction. Since a CRC check is performed when transferring the notator to the computer, error detection results can only be obtained after the data has been transferred to the host computer, and depending on the interface, no error detection information is sent to the host computer. It had the disadvantage that it could not be informed.

In view of the above drawbacks, the present invention provides C
The present invention provides a code error detection method that performs an RC check to speed up processing, and also enables data error detection before data transfer from a buffer memory to a host computer.

Means for Solving the Problems In order to achieve this object, the present invention uses a Reed-Solomon code for detecting errors in bytes as an error detecting code for a recording/reproducing apparatus using an optical disk. All data is stored in one buffer memory.

Store in area A.

(11) For continuous n data, read m data at the first n data intervals from area A of the buffer memory, input it to the error correction circuit, and read out m data from another m address of the buffer memory. Store it in area B of .

(11D) The error correction circuit determines the magnitude and position of the error, and corrects the data corresponding to the error position in the A area and B area of the buffer memory.

1iv) Read m pieces of data in a second n data space different from the above from the A area of the buffer memory, input it to the error correction circuit, and read it from the B area of the buffer memory.
Read data from area.

XOR addition of the data in area A and each 2 data i
This is repeated m times, and the data is stored again at the original address in area B of the buffer memory.

(v) m of the second n data in the H error correction circuit.
Find the magnitude and position of the error regarding the second data of the buffer memory, and calculate the data corresponding to the error position of the data in the A area and the data in the B area of the buffer memory regarding the m data in the second every n data of the buffer memory. correct.

(I) Repeat the above processes (1) to (■).

With these, B of the buffer memory finally obtained
The m data in the area and the P byte-based error detection parity 'f in the A area of the buffer memory are divided by a predetermined generator polynomial, and errors are detected based on whether the remainder is zero or non-zero. It is something.

Operation This method allows the CR represented by the precomputed multi-symbol XOR cumulative addition in parallel with the error correction
By correcting the C calculation data and performing a CRC check on only the corrected CRC calculation data after completion, the CRC check is completed at the same time as the error correction is completed, allowing for high-speed error detection and buffer storage. A false 9 detection check can be performed before data is transferred from the memory to the host computer.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of an error detection device that implements an error detection method according to an embodiment of the present invention. 1st
In the figure, 1 is a host computer, 2 is an interface, 3 is a digital modulation circuit, 4 is a digital demodulation circuit, 5 is a buffer memory, 6 is an n-symbol XOR cumulative addition circuit for CRC calculation, 7 is a CRC code generator/checker, and 8 is an error correction circuit, 9 is a binary XOR addition circuit,
1 o.

11 is an encode/decode changeover switch, 12 is a data bus, and 13 is a recording medium.

Hereinafter, in order to simplify the explanation, the explanation will be based on the data arrangement diagram of the sector format shown in FIG.

First, during recording, data in bytes is sent from the host computer 1 to the interface 2. Data bus 12tjM
and go to buffer memory 5. , 103.

Dl, 103. D2,103. """D9,103
．． DO, 102, Dl, 102°D2.102,”
"" l D9,102, """ I DO,1, D
I, 1, D2.1.

""'l D9,1 ,DO,0,DI ,O,D2,
0. D3,0. D4,0. They are stored in the order of D5 and 0.

At the same time, the signal is input to the cumulative addition circuit 6 which performs XOR cumulative addition for CRC calculation, and the XOR cumulative addition shown in the following equation is executed.

Engineering 103=Do, 103■D1,103■D2.103
■°°゛”°eD9103 =i”@Di, 103
102 l=o z, 102 I,=i mi. Di, 1 1o=i too. Di,.

This is Lano Engineering 103. Engineering 102. ``Track 1'' is input to the CRC generator, error detection parities C8 to C3 are calculated, and the results are stored in the buffer memory 6.

Next, buffer memory 5. The data in each horizontal row related to "+" for each i of l, Dl, is read out and sent to the error correction circuit 8.
The error correction parity Eik is calculated and stored in the buffer memory 6.

Finally, the data in the buffer memory 5 is D. , 1°3;
Dl, 103.2, 103. """ T D9,10
3. DO, 102, Dl, 102°D2.102,
'"°°°°A D9,102,"""l DO,1
, Dl ,1 , D2.1 .

”'”' D9+ ' rDo+○lD1 IQ I
D21or"'""D5+O+03"2'C1,C
Qfu also, 15. El, 15. E2,15. ”°“
” l E9, 15.EO, 14°El, 14.E
2,14. """lE9,14."'"°°ツ"0,0
．． El, ○.

The signals are read out in the order of E2o, E9°, input to the digital modulation circuit 3, added with necessary signals such as a synchronization signal, and recorded on the recording medium 13.

On the other hand, during reproduction, the data read from the recording medium 13 is demodulated by the digital demodulation circuit \4, and is stored in the buffer memory 5 so that it corresponds to the same address as when it was recorded and forms a sector format as shown in Fig. 2. is stored in

Next, first, the data in the uppermost horizontal row in FIG. At the same time, the data is stored in the monthly address for storing data for CRC calculation in the memory 5. The error correction circuit 8 calculates the size of the error and the position of the error, reads out the error data from the address of the buffer memory 6 corresponding to this error position, and
The magnitude of the previous error 9 is XOR-added in the error correction circuit 8, and the error is corrected by being stored again at the original address. After this, the CRC calculation data storage address corresponding to the previous error position and the same error 9 data as above are read out from the buffer memory 5, and the error correction circuit 8 reads out the same error size as above. The data is XOR-added and stored again at another address at the source.

Next, the data is input to the data error correction circuit 8 in the second row from the top in FIG. In parallel with this, the data in a horizontal row is first inputted to the binary XOR addition 1.103 arithmetic circuit 9, and then the corrected Do, 103 is read out from the CRC calculation data storage address, and the same is done. to 2
The value is input to each 9 of the value X0R7 + Moroki J. Here, engineering 10
3 = DO, 103eD1103 is calculated and stored again in the original CRC calculation data address. These additions are performed by the binary XOR addition circuit 9 in the error correction circuit 8. (EI D1',. is calculated and the original CR
Stored in the C calculation data storage address. Thereafter, the error correction circuit 8 calculates the magnitude and position of the error regarding the data and parity in the second horizontal row, and reads out the error data from the address of the buffer memory 6 corresponding to this error position. In addition, the magnitude of the previous error is XOR-added in the error correction circuit 8, and the result is stored again at the original address, thereby executing error correction for the second horizontal row. After that, the code corresponding to the previous error position is read from the CRC calculation data address of the buffer memory 6, and the error size is XORed with this in the error correction circuit 8.
As a result, the CRC calculation data is modified and stored again at the original address. From then on.

The same process is repeated from the 3rd stage to the 10th stage.

Here, D, j, and E represent playback data, and Di, j
represents data after error correction. Moreover, Ia represents the XOR cumulative addition data after error correction. As a result, the CRC calculation data I6 in the buffer memory 5 is as follows at the time when the error correction process for the 10th horizontal row and the modification process to the CRC calculation data are completed.

■. = Self. Di,.

Finally, all data D of the conventional method. , 103,...
..., C3° There is much less data compared to C2, C1, and C0.

From buffer memory 5, II ...... Engineering 1
03' 102+ 1 1'I0. C3, C2
, C1, and C0, and input to the CRC checker 7 to check for errors. This results in
After the error correction process is completed, the CRC check is completed in a shorter time than in the conventional method. Based on this result, the contents of the buffer memory 5 are transferred to the host computer 1 through the data bus 12 and the interface 2, or are prohibited, or the CRC check result is transferred together with the data.

In this case, the CRC parity generation polynomial uses a Reed-Solomon code for detecting false errors in bytes. For example, G(3) is also d (X+cti) l20 Here, it is the primitive light of a finite field that satisfies the modulus polynomial of the 8th degree blur.

Effects of the Invention As described above, according to the present invention, by using a byte-based Readon-Romon code as a CRC code for error detection and executing CRC processing in parallel with data error correction, error detection processing can be speeded up. This makes it possible to detect errors in data before data is transferred from the buffer and memory to the host computer, and is compatible with any interface.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an error detection device that implements an error detection method according to an embodiment of the present invention, FIG. 2 is a data arrangement diagram of a sector format of an optical disk, and FIG. 3 is a block diagram of a conventional error detection device. It is. 1.21...Host computer, 2.22.
...Interface, 3...Digital modulation circuit, 4...Digital demodulation circuit, 5,2
4... Buffer memory, 6... Cumulative addition circuit, 7.23... CRC generator, checker, 8, 25... Error correction circuit, 9.・・・
...XOR adder circuit, 10.11...changeover switch, 12...data bus, 13゜2a...
...Recording medium, 26...Digital modulation/demodulation circuit.

Claims (1)

[Claims] A Reed-Solomon code for byte-based error detection is used as an error detection code for a recording/reproducing device using an optical disk.
(b) Store all the reproduced data in area A of the buffer memory, and (b) Store m pieces of data every second n data for consecutive n pieces of data in area A of the buffer memory.
(c) The error correction circuit determines the size and position of the error, and the data is read from the area A of the buffer memory. , correct the data corresponding to the error position in area B, and (d) read a second m data set every n data, which is different from the above (b), from area A of the buffer memory, and correct the error. While inputting the data to the circuit, data is read from the B area of the buffer memory, XOR addition of each two data with the data of the A area is performed m times, and again, the data is read from the B area of the buffer memory.
(e) The error correction circuit calculates the size and position of the error regarding the m pieces of data in the second every n data, and stores the data in the second every n data in the buffer memory. Correct the data corresponding to the error position of the data in area A of the buffer memory and the data in area B regarding m pieces of data, respectively, and (f) perform the steps (b) to (b) above.
By repeating the process (e), the finally obtained m pieces of data in area B of the buffer memory and P pieces of error detection parity in units of bytes of area A of the buffer memory are determined by a predetermined generating polynomial. A code error detection method characterized by dividing by , and detecting an error based on whether the remainder is zero or non-zero.