JPH05218883A - Decoder circuit - Google Patents

Abstract

PURPOSE:To provide a decoder which can execute processing at high speed. CONSTITUTION:In the decoder circuit to obtain corrected data by providing an error correcting circuit 10 to correct error by inputting a data part DATA and a redundant part ECC and a first CRC check circuit 20 to detect error correction in respect to the result of the error correcting means, a buffer memory 40 is provided to store the data part DATA, a second CRC check circuit 50 is provided to detect the error of the data part DATA, and a selecting circuit 60 is provided to select either the output of the first CRC check circuit 20 or the output of the buffer memory 40 and to output it as the corrected data. When the second CRC check circuit 50 judges there is no error in the data part DATA, the selecting circuit 60 selects the output of the buffer memory 40 as the corrected data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding circuit for obtaining corrected data by performing error correction processing on a signal read by an optical information recording / reproducing apparatus or the like.

[0002]

2. Description of the Related Art In an optical information reproducing apparatus such as an optical disk, a Read Solomon (RS) code is generally used to correct an error in read data. Such a Read Solomon code is a kind of byte error correction code. For error correction, 1 word is made to correspond to the element of the Galois field r bits, and the correction processing is performed in units of this word.

In this Read Solomon code, the syndrome is calculated based on the read data from the recording medium regardless of whether or not there is an error at the time of decoding. Such a syndrome can be represented by the following formula.

[Equation 1]

When this syndrome is 0, there is no error, and when it is not 0, an error has occurred. Therefore, error correction processing is performed when the syndrome is not zero. Here, FIG. 2 is a block diagram showing a configuration of a conventional decoding circuit. As shown in the figure, this decoding circuit comprises an error correction circuit 10 and a CRC check circuit 20 '.

In the error correction circuit 10, the syndrome calculation circuit 11 calculates the above-mentioned syndrome. Then, when the calculated syndrome is not 0, the error position detection circuit 12 uses the calculated syndrome from the calculated syndrome.
Error location polynomial σ (Z)
And an error numerical polynomial η (Z). Further, the error position detection circuit 12 detects an error position by using a chain search. Finally, the error correction execution circuit 13 finds and corrects the error size at the error position estimated from the error position polynomial and the error number polynomial.

Further, the output of the error correction circuit 10 is CRC.
An error correction is detected by the check circuit 20 '.

[0007]

However, the above conventional decoding device has the following problems. It is said that it takes a lot of time to calculate the syndrome in the processing of the decoding device. It is of course necessary to calculate such a syndrome when an error has occurred, but it is not necessary to perform it when there is no error. Therefore, when there is no error, the decoding speed cannot be increased.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a decoding device capable of high-speed processing.

[0009]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides an error correction means for inputting predetermined data and a redundant part to correct an error in the data, and an error correction means. Equipped with an erroneous correction detection means for detecting erroneous correction for the result
In a decoding circuit for obtaining corrected data from predetermined data, storage means for storing the predetermined data, error detection means for detecting an error with respect to the predetermined data, and erroneous correction And a selecting means for selecting and outputting either the output of the detecting means or the output of the storing means as the corrected data, and the selecting means has no error in the predetermined data by the error detecting means. When it is determined that the output of the storage means is selected as corrected data.

[0010]

According to the present invention, the decoding device is constructed as described above, the error detecting means judges whether or not an error has occurred, and if the error does not occur, the data stored in the storage means is corrected. Since the data is output as the completed data, the data
If there is no error in the data, the processing speed can be increased.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a decoding circuit according to the present invention. In the figure, 10 is an error correction circuit, 20 is a first CRC check circuit, 30 is a switch, 40 is a buffer memory, 50 is a second CRC check circuit, and 60 is a selection circuit. The error correction circuit 10 is similar to that of the conventional decoding device, and the first CRC check circuit 2
The configuration of 0 is the same as that of the CRC check circuit 20 'of the conventional example, and the description thereof will be omitted.

As shown in the figure, the read data read from the recording medium or the like is output to the error correction circuit 10 and the switch 30. Here, FIG. 3 shows the read data.
It is a figure for explaining the data. As shown in the figure, the read data comprises a data part DATA and a redundant part ECC.
Data block DATA is sync code SB1-SB3, re-sync code RS
1 to RSm, byte data D0 to Dn, CRC code CRC1 to
CRC4 is added. The redundant ECC is E1.1, E1.
2, ... E2.1, E2.2 ,. The correction direction of this read data is perpendicular to the recording direction, and error correction is performed for each of the interleaves 100-1 to 100-5.

All the read data, that is, the data portion DATA and the redundant portion ECC, are output to the error correction circuit 10 and the switch 30, and the read portion of the read data is the data.
The switch 30 is turned on only when the data DATA is output. Therefore, the second CRC check circuit 5
Only the data portion DATA of the read data is output to 0 and the buffer memory 40.

The buffer memory 40 stores the data portion DATA sent from the switch 30. Also, the second CR
The C check circuit 50 detects an error by checking the CRC code of the data part DATA.

Further, in the error correction circuit 10 to which the data part DATA and the redundancy part ECC are inputted, the error correction processing is carried out as in the conventional decoding circuit.

When it is determined by the second CRC check circuit 50 that the data part DATA has no error,
The second CRC check circuit 50 outputs the control signal to the selection circuit 60. In such a case, the selection circuit 60 selects the output of the buffer memory 40 as the corrected data. Therefore, the data in the buffer memory 40 is output as the corrected data at a predetermined timing.

On the other hand, when the second CRC check circuit 50 determines that there is an error in the data part DATA, the selection circuit 60 uses the control signal to
The output of the first CRC check circuit 20 is selected as corrected data. Therefore, the error is corrected by the error correction circuit 10, and the first CRC check circuit 2
The data passing 0 is output as corrected data at a predetermined timing.

Comparing the timing when the error detection in the second CRC check circuit 50 ends with the timing when the error correction in the error correction circuit 10 and the first CRC check circuit 20 ends, only the error detection by the CRC code is detected. Since the completion of the processing in the second CRC check circuit 50 to be performed is obviously earlier, when the data portion DATA has no error, the corrected data is output earlier than when the error correction is performed. To be done. In addition, the data unit DA
Even if an error occurs in the TA, the error correction processing is performed in the error correction circuit 10, so that the corrected data can be obtained at the same timing as the conventional decoding device. For example, when considering read data from an optical disk, the error occurrence rate of the read data is as low as 1/10 ⁴ to 1/10 ^6, and error correction is often unnecessary.

In this embodiment, for example, 5.25
When the read data from the optical disk device for reproducing an inch optical disk is used, the total read data per sector is 610 bytes, of which 530 bytes for the data part DATA and 80 bytes for the redundant part ECC. is there. Therefore, in such a case, the buffer memory 40 needs to have a storage capacity capable of storing at least 530 bytes or more.

[0020]

As described above, according to the present invention, the following excellent effects can be obtained. Whether or not an error has occurred is determined at high speed by the second CRC check circuit, and if no error has occurred, the data in the buffer memory is output as corrected data. It is possible to speed up the processing when there is no error.

Further, even if there is an error in the read data, error correction is performed in the error correction circuit, so decoding is possible even in such a case.
The processing time is also the same as that of the conventional decoding device. Therefore, the overall processing time is shortened in consideration of the case where there is no error.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a decoding circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional decoding circuit.

FIG. 3 is a diagram for explaining read data.

[Explanation of symbols]

 10 error correction circuit 20 first CRC check circuit 30 switch 40 buffer memory 50 second CRC check circuit 60 selection circuit

Claims (1)

[Claims] 1. An error correction means for inputting predetermined data and a redundant portion to correct an error in the data, and an error correction detection means for detecting an error correction in a result of the error correction means. A decoding circuit which obtains corrected data from the predetermined data, storage means for storing the predetermined data, and error detection for detecting an error with respect to the predetermined data. Means, and a selecting means for selecting and outputting either the output of the erroneous correction detecting means or the output of the storing means as corrected data, the selecting means comprising: A decoding circuit, wherein when it is determined that the predetermined data has no error, the output of the storage means is selected as corrected data.