FR2762920A1 - Data transferral method for optical disk mass storage system - Google Patents

Abstract

The method involves retrieving a data string from an optical storage disk and converting it to a form compatible with storage in digital memory. The data string is stored within buffer memory while providing it to an error detection circuit. An error detection operation is performed on the data string to determine errors, with a portion being performed while the string is being stored in the buffer. The retrieved data string is transferred to a host computer system if no errors are present. If errors are detected, an error correction operation is performed prior to transferring the data to the host computer.

Description

DATA TRANSFER PROCESS

  BETWEEN AN OPTICAL DISC MASS MEMORY

AND A COMPUTER

  The present invention relates to the transfer of data from

  mass storage positive to host computer systems. The invention relates more particularly to improved error processing

  which can be used to increase data transfer rates

  born from a mass memory device such as a memory

  dead to optical disc, to a data bus of a personal computer

net host.

  Optical mass storage devices, such as compact disc (or CD-ROM) read only memory devices are used for the storage and distribution of programs and memory structures.

  data, especially when programs and data structures

  are too large to be conveniently distributed to users.

  computers or other small computer systems.

  CD-ROM devices and similar mass storage devices

  res currently have data access speeds considerably lower than those of integrated circuit memories as

  magnetic hard drive storage. Therefore, forms of reaction

  conventional small computer systems limit the number

  access to optical mass storage devices that are performed

  you are. For example, program data is transferred from a device

  than CD-ROM type storage to the magnetic hard drive of the small computer system to install and configure the program. Once

  that the program data has been loaded onto the hard disk

  genetic of the small computer, it is common that we no longer access

  the optical drive during future uses of the program.

  Some programs contain data structures

  audio video or other that is not transferred to the hard drive ma-

  genetic for permanent storage; instead, we access these data

  born on the CD-ROM while the program is running. In part-

  especially for such programs, but also for other applications.

  tions that use CD-ROM mass memory, we want to conti-

  increase the speed at which data can be accessed from the CD-ROM and supplied to the data buses of the system

  computer science. Historically, the main bottleneck

  cipal for transferring data from memory to CD-ROM has been

  the speed at which data is read from the CD-ROM disc itself

  same, rather than the controller who assembles the data in a certain format and which performs the detection and correction of errors and the like

  data transfer operations. To tackle this foreign bottleneck

  We have also increased the speed of rotation of CD-ROMs to a

  value a large number of times greater than the nominal speed of rotation

  which is fixed by CD-ROM standards. Therefore,

  data is read from the CD-ROM disc at increased speeds, up to

  that to the point at which operations of the data transfer controller now limit, or may limit in the short term, the data transfer rates. Technologies are now being introduced using higher density data recording discs, and further refinements which are under development will provide data recording densities

  even higher. The data is read in these meta systems.

  mass of higher density at even higher rates

  which will place even greater demands on control.

their data transfer.

  It is necessary to perform a variety of operations on the data that is read from the CD-ROM disc before the data

  can be supplied to the data buses of the host computer system.

  These operations are generally familiar to those skilled in the art and include descrambling, reorganization, registration

  in buffer, error correction and error detection. We can find

  see additional information regarding the classic operations

  which are performed in the transfer of data from a meta

  CD-ROM disk drive to a data bus of a computer system

  as a host in the U.S. patent No. 4,680,764 issued to Suzuki et al., in the U.S. Patent. No. 4,802,152 issued to Markvoort et al., and in the U.S. Patent. No. 5,581,715 issued to Verinsky et al. FIG. 1 illustrates aspects of the CD-ROM controller described in the patent of

  Verinsky, which could be used to order data transfer

  from a CD-ROM memory disc to the IDE bus of a computer

  host host. Data is read from the CD-ROM disc when reflected.

  sant laser light on the surface of a rotating disc and detecting

  both the modulations that are introduced into the laser light reflected by optical variations on the surface of the disc. An analog-to-digital converter converts the detected modulations into digital signals which are supplied in the form of a serial bit stream 10, to be applied to the CD-ROM controller. CD-ROM discs store data that is typically less random

  than would be optimal, which means that data can accidentally

  so much present timing signals or other control signals. Therefore, the data recorded on the CD-ROM disc is scrambled. The data which is extracted from the reflected light is therefore applied to a descrambling circuit 12 and is

  descrambled before further processing. An organizational system

  Data 14 reorganizes the descrambled serial data bit stream into bytes and stores the data in a buffer memory 16. The data is saved on a CD-ROM in sectors

  approximately 2 KB and data is transferred from disk to computer

  host by sector. An entire data sector is therefore

  stored in the buffer before error correction and the

error detection does not begin.

  Once a 2K data sector from the dis-

  that CD-ROM is saved in buffer 16, the correction

  errors and error detection are performed on the recorded data

  registered. Error correction and error detection for CD-ROM mass storage systems are largely required by ISO / IEC-10149 for recording data on CD-ROM discs . Conventional error protection, error correction, and detection coding operations

  errors for CD-ROM mass storage systems are resolved

  written in the U.S. patent No. 4,413,340 issued to Odaka et al., and in the U.S. Patent. n 4,680,764 issued to Suzuki et al. Integrity

  data is maintained during data transfer from CD-

  ROM to the host computer by three sets of error correction data, which are appended to the user data in the sector:

  one hundred and seventy-two bytes of P parity error correction, one hundred and forty

  three Q parity error correction bytes and four error detection code (or EDC) bytes. The incorporation of the P parity and Q parity data incorporates into the CD-ROM data a double interlaced Reed-Solomon code. The data within the sector can be grouped into two data planes, namely a least significant bit plan, or LSB, and a most significant bit plan, or MSB,

  each data plane having an error correction matrix

  trelacé, like that which is represented on figure 2. The matrix represents

  shown in Figure 2 has forty-three P vectors consisting of twenty-four bytes of user data, in combination with two P parity bytes, to form Reed-Solomon code words

  (26, 24) on GF (28). Twenty-six Q vectors extend along the diagona-

  those in the matrix and consist of forty-three bytes of user data

  reader and two Q parity bytes formed by Reed- code words

  Solomon (45, 43) on GF (28). Data is read from the buffer memory 16 (FIG. 1) in the form of P vectors and Q vectors,

  error correction calculations are performed by a correction logic

  error 18 to identify errors in the data, and when

  errors are found, the error equations are solved to cor-

  correct errors. When errors are found in the P vectors and the Q vectors, the data in the buffer 16 is corrected by replacing the erroneous bytes of data in the buffer

  by corrected data bytes.

  After all the data correction operations have been carried out, it is usual to detect if errors remain in the

  corrected data, or if errors have been introduced by the operators

  corrections. Error detection is performed using a cyclic redundancy check (or CRC) circuit, in which the entire data block (-2000 bytes x 8 bits) is treated as a long binary number which is divided by a polynomial of control. In accordance with ISO / IEC-10149, the error control polynomial is P (x) = (x16 + x15 + x2 + 1). (X16 + x2 + x + 1). The data recorded on the CD-ROM contains four bytes of error detection code (EDC)

  added so that the long binary number including the data in-

  recorded on the CD-ROM is fully divisible by the error control polynomial. If the long binary number of the data that is

  transferred from CD-ROM is fully divisible by poly-

  error checking, it is assumed that there are no more errors

  in the corrected data. If a non-zero remainder results from the error checking division, then there are still errors in

  corrected data, and an additional error correction was born

  stop. Alternatively, the data can simply be retrieved

  read on the CD-ROM and the process of correction and detection of er-

  reurs can be repeated. Material embodiments of the divi-

  Error checking, of the characteristic type, are simple, and con-

  exist in shift registers with feedback connections and an OR-EXCLUSIVE gate network (E). Error detection requires that the entire data block be read into the buffer by the logic of

  error detection 20 and be shifted in series through the circuit

  check by cyclic redundancy 22. As long as the error correction and error detection operations produce a remainder equal to zero, the data can be transferred from the buffer memory 16 to the data bus of the computer system, under the shape of a

  outgoing sector 24 having been the subject of an error check.

  Correction and error detection are aspects that take

  a lot of time in transferring data from mete devices

  CD-ROM to computer data buses. However, some sort of error correction is necessary in reading data from an optical memory disc, due to the nature of the data reading operation and the processing required to place

  data in a format suitable for a computer. In addition, some

  some aspects of error correction are imposed by the standards

  for CD-ROMs and other optical mass storage systems.

  An object of the present invention is therefore to provide an ar-

  architecture for the correction of data errors which are read in a mass storage device, which allows higher data rates of

data transfer.

  One aspect of the present invention provides a method for transferring data between a mass storage system to disk.

  optical and a host computer. A data string is read from the device.

  that of optical memory and it is converted into a compatible form

  with recording in digital memory. The donation chain

  which is read is stored in a buffer for

  that it is supplied to an error detection circuit. An er-

  rors is performed on the read data string, to determine if errors are present in the read data string, and at least part of the error detection operation is performed while the read data string is stored in the buffer. The data string read is transferred to the host computer system if the error detection operation determines that no error is present in the data string read. On the contrary, if the error detection operation determines that errors are present in the

  data string read, an error correction operation is performed

  killed on the read data string, before the read data string

  is transferred to the host computer.

  Another aspect of the present invention provides a method for transferring data between an optical disk mass storage system and a host computer, by reading a data string from the optical memory disk and by buffering the string of data that is read. The data string read is applied to a first error detection circuit, and the first circuit

  error detection performs a first error detection operation

  errors on the data string read, to determine if errors exist

  attempt in the data string read, and to determine a first value

  error detection which is characteristic of errors present in the data string read. An error correction operation is

  performed on the data string read, to identify a first er-

  error in the data string read and to determine an error configuration for the first error. The first error is then corrected in the read data string, and a second error detection operation is performed to determine if errors remain in the

corrected data string.

  In a preferred embodiment of this second aspect of the

  present invention, the step of performing a second operation

  error detection tion includes the calculation of a correction to be made

  at the first error detection value, based on the configuration

  error that is determined for the first error.

  Other characteristics and advantages of the invention will be

  better understood on reading the following description of modes of

  embodiment, given by way of nonlimiting examples. The rest of the

  description refers to the accompanying drawings, in which:

  Figure 1 shows a typical embodiment of a con-

  CD-ROM data transfer monitor.

  Figure 2 shows the standard error correction matrix for data stored in memory disks

mass CD-ROM.

  Figure 3 shows a disk mass storage system

  optics according to a preferred embodiment of the present invention

  tion. Figure 4 shows the structure of data recorded in

  a sector of a mode 1 CD-ROM disc.

  Figure 5 shows a cyclic redundancy control circuit

  that can be used with the structure of Figure 5.

  Figure 6 shows a CD-ROM controller conforming to a

  preferred embodiment of the present invention.

  Figure 7 shows an error detection processor

form to the present invention.

  Figure 8 shows a counter that can be used in combination

  ciation with preferred embodiments of the present invention.

  FIG. 9 shows another embodiment of a process

  error detection device according to the present invention.

  Preferred embodiments of the present invention

  allow error correction and error correction operations

  faster error detection, without compromising compliance levels

  trust in the data that is read from the CD-ROM and supplied to the host computer. These embodiments of the invention can be

  implemented while maintaining compatibility with industrial standards

  trielles for CD-ROM memory devices. In accordance with one aspect of the present invention, data is read from a mass storage unit and the serial data stream is applied in parallel to both a buffer memory and an error detection circuit. The error detection circuit, which could be a control circuit by

  classic cyclic redundancy, performs an er-

  rors on the data which are read from the mass storage unit, preferably at the same time as the data stream is recorded in

  the buffer. For example, the error detection operation could

  ple consist in dividing by the error control polynomial the serial data stream which constitutes a data block, and in determining the remainder of the division operation. If the error detection operation produces a result in accordance with the absence of errors in the data block, the

  block of data that is stored in the buffer can be di-

  correctly transferred to the data bus of the host computer system, by not performing any data correction operation on the

data that is read.

  This aspect of the present invention provides several advantages.

  with respect to conventional error correction and error detection operations which are performed in conventional data transfer operations between CD-ROM memory devices and the data buses of host computer systems. We can give

  system a configuration such as data correction operations

  data are only performed when there is reason to believe that data correction is necessary. Eliminating unnecessary data correction operations increases the speed at which data can be transferred. There is obviously a small probability that an erroneous block of data can be entirely divisible by the control polynomial, and it is conceivable that it may be desirable not to rely exclusively on the zero remainder which is produced by l error detection operation. In such a case, the data transfer system could perform data correction operations in a characteristic manner after a zero remainder has been obtained, but it could keep track of whether any data has been corrected or not. in error correction operations. If no error correction is made after the initial indication of no error in the error detection operation, then the error detection operation would not be performed following

  the data correction operation. Although corrective operations

  tion of errors are performed in this variant, the detection operation

  Error handling is always performed only during the initial reading of data from the mass storage system. Since it is not necessary to read the data in the buffer memory and supply it in series to the error detection circuits, following the operation of

  error correction, this variant is even considerably more

  pide than the conventional embodiment for correction and detection

  tion of errors. In such embodiments, it is not necessary to wait for the completion of the error detection operation before starting the error correction operations. Therefore, the

  error correction operations can be started immediately-

  after the data has been stored in the

pon.

  These aspects of the invention are very advantageous for systems

  subjects in which there are few errors in reading data from a CD-ROM memory disc, or in assembling the data read, to place them in a format suitable for use by a computer system, or in the application of data to the data bus of the host computer system. Convenient systems can have considerably higher error rates, especially when

  new technologies are introduced into stock systems-

  optical age. Optical disk storage systems that use

  higher density discs with smaller element sizes

  data, such as the digital video disc (DVD) system,

  may have increased error rates. In addition, metal disks

  single write and multiple read optical moire (or "write once / read many") and optical discs with rewrite capability typically have information modulation techniques that are less robust than those of CD-ROM discs, which means that systems using such discs of new technology can also be affected by error rates

  higher than those observed for CD-

ROM.

  Other aspects of the present invention find application.

  tion in more realistic systems in which er-

  rors appear during the reading of data in systems

  mass memory. Certain embodiments of the invention read data from a mass memory unit and they provide in parallel to a buffer memory and to an error detection circuit.

  the serial bit stream that is read. The data read is organized in oc-

  tets and they are saved in the buffer. At the same time,

  the error detection circuit performs an error detection operation

  errors on the serial data stream which is read in the mass memory unit. Here again, the error detection operation could consist in dividing by the error control polynomial a segment of the serial data stream corresponding to a data block, and in determining the remainder of the division operation. The rest of this division operation

  error error is recorded, unlike conventional EDC systems

  who reject the data. An error correction is then made

  carried out on the data which are recorded in the buffer memory, by using for example a code of the kind produced by Reed-Solomon, in the conventional manner. Here again, the error correction operations can be started as soon as the data is assembled in the buffer memory, without waiting for the completion of the detection operation.

  errors. When erroneous bytes are identified by the cor-

  error correction, the error equations are solved to determine the

  corresponding error configuration, and erroneous bytes are replaced

  these are in the buffer. The locations of the wrong bytes in

  the serial data stream, as well as the error configurations of the oc-

  tets, are then used to calculate corrections to the rest of the error detection code (EDC), which results from the initial error division by the read error control polynomial in the data stream. The rest corresponding to the error detection code (EDC) is corrected in accordance with the particular location and the confi-

  guration of particular error of each of the corrected bytes. The rest cor-

  corresponding to the error detection code is tested after the correction of each erroneous byte, to determine whether the remainder corresponding to the

  error detection code is different from zero, and if the rest correspond to

  responding to the error detection code is different from zero, it is recorded

  registered and error correction operations are continued. This is quite separate from the classic error correction technique, which rejects the error configuration and the error location

  after bad bytes have been corrected in the buffer.

  Error correction continues until the remainder corresponding to the error detection code is reduced to a value of zero. At this point, it is assumed that all errors have been corrected and that the data stored in the buffer memory is supplied to the bus.

  host computer data. If the rest corresponding to the code of de-

  error correction does not reach zero, the entire error correction process can be repeated on the data already corrected once, which are in the buffer. More preferably, the data sector is read again on the CD-ROM and all the processes of

  error detection code and error correction code of the pre-

sente invention is repeated.

  As with the embodiments described above,

  this aspect of the invention also provides transmission rates.

  higher data due to the fact that data is never read from the buffer to be supplied bit by bit to a circuit

  error detection. In addition, by interrupting correction operations

  tion of errors and transferring the data block after the rest of the error division has been reduced to zero, at least some operations of

  correction of unnecessary errors are avoided, which further improves

  the rate of data transfer. We will now present

  a more detailed description of the present invention, starting

  by a description of the general environment in which at least

  certain preferred embodiments of the present invention are used.

  his. Figure 3 shows an optical disc mass storage system which can be a CD-ROM mass storage device. The data transfer system which is shown operates under the

  control of a microcontroller 40, which may be of the 8051 type, function-

  according to a control program which is stored in a non-volatile memory 42. Information is recorded from

  optically on the memory disk 50 in the form of regions sur-

  raised or lowered on the surface of a reflective disc, or below the

  form of local variations in the optical properties of the disc. The informa-

  tion is read on the disc by directing on the surface of the disc 50 a

  laser beam coming from an optical reading head 52, and collecting the light which is reflected by the disc. A detector which is incorporated in the optical read head 52 receives the reflected light and generates an analog electrical signal representing the recorded information, and provides this signal to the analog signal processor 54. The analog signal processor 54 receives the signal of information that comes from the

  optical read head 52 and it receives the servo information

  coming from the plate or from the motor which rotates the memory disk 50.

  The analog signal processor processes the information signal and provides the information signal in a format suitable for the digital signal processor 56. The digital signal processor 56 provides at its output a digitized information signal which is directed to the controller

  CD-ROM 58 or to a digital-analog converter 60. The con-

  digital-to-analog converter is capable of converting the digital information signal from the digital signal processor 56 to an analog signal. This analog signal is supplied to the output terminal

* audio 62, constituting an audio output from the CD-ROM drive. The sub-

  system comprising the analog-digital converter 60 and the output

  tie audio 62 is typically incorporated into a small computer system to allow audio compact discs to be reproduced,

  without going through the digital data transfer circuit of the

  CD-ROM thrower. Data to be transferred to the data bus 64,

- ---------- ---

  which is illustrated as an IDE data bus, are transmitted by the CD-ROM controller 58 which operates in communication with

  a buffer memory 66 for defining the format of the data and for ef-

  perform error correction and error detection on data

  before supplying the data to the IDE 64 bus. Figure 3 shows a mass memory system for reading

  data that is recorded on CD-ROM discs. The organiza-

  tion of data in CD-ROM sectors is defined by ISO / IEC-10149: Information Technology-Data Interchange on Read-Only

  120mm Optical Data Disks (CD-ROM) (Information Technology -

  Data exchange on 120 mm Optical Data Discs (Read Only). This standard imposes the major part of the structure of the data which is recorded on the CD-ROM disc, but different variants are possible within the framework of this overall structure. There are three different sector modes in the standard, so that the data recorded on the CD-ROM 50 of Figure 3 could be presented in any of the three modes: mode 0, mode 1 and mode 2 Thus, the circuit of Figure 3 must be able to accept the different data structures that are associated with the different modes, in response to the data byte of

  mode which is included in the CD-ROM data itself. This as-

  pect of data transfer from CD-ROM type devices is

  well known. The remaining explanation is presented mainly in con-

  staggering mode 1 data transfer from a CD-ROM disc.

  Figure 4 shows the structure of the data that is recorded

  very in a mode 1 sector, as defined by the standard. The sector is subdivided into a certain number of fields comprising a twelve-byte synchronization configuration which identifies the start of a sector for the reading of the data by the optical read head and the initial data processing circuit of FIG. 3. A header to

  four bytes contains the absolute address of the sector, in minutes, second-

  and and frames (1 second = 75 frames), and a mode byte which indicates in which of the three possible modes the data in the sector is

  saved. Mode 1 sectors contain 2048 bytes of data.

  user data, which constitute bytes 16 to 2068 of the

  mode 1, which are followed by four bytes of detection code data

  error message (EDC), eight intermediate bytes, one hundred and seventy-two oc-

  parity heads P and one hundred and four bytes of parity Q. As envisaged above

  above, the parity bytes P and the parity bytes Q constitute the error correction code (ECC). The error detection code (EDC) and the error correction code (ECC) constitute the two complementary error protection mechanisms for each sector of

  CD-ROM. The EDC field, which is part of a redundancy control code

  thirty-two bit cyclic dance (CRC) which contains its data fields

  protected, is used to detect if there are errors in a sector. The ECC field, which includes the P parity field at 172 bytes and the Q parity field at 104 bytes, is a ReedSolomon Product Type Code (or RSPC for "Reed-Solomon Product-like Code") which

  is used to detect and correct errors in a sector. By con-

  sequential, the EDC code provides a check to determine if errors

  are present in a sector which is read, and the ECC code allows the cor-

  correction of errors in the data transferred. Conventionally, as shown in Figure 1, there has been an implicit presumption of

  the presence of errors in the data which is read on the CD-disc

  ROM, which means that all possible ECC operations are performed

  before any EDC operation is performed. This strategy

  gie is capable of correcting errors in transferred data sectors, without using control circuits to assess whether

  whether or not it is necessary to perform a particular error operation.

  On the other hand, data transfer operations will be slowed down by the completion of error correction operations on data which either did not initially contain errors, or have been corrected.

  so that no additional errors remain in the data.

  It is important to note that while industry standards for

  recording and playback of data recorded on CD-

  ROMs require both error correction and error detection, the particular structure which is illustrated in Figure 1 is not imposed

by standards.

  For CD-mode mode 1 sectors, the code word EDC consists of bytes 0 to 2067 of a sector, while for sectors

  mode 2, form I of CD-ROM XA, the code word EDC consists of oc-

  tets 16 to 2075 in the sector. In EDC calculations, the least significant bit (or LSB) of a data byte is used first, so that the bytes of a sector can be designated by Bi, i = 0 to 2351, and one bit of the data byte is Bij, j = 7 (MSB) to 0 (LSB), the LSB symbol designating the least significant bit. The EDC codeword for a mode I sector of CD-ROM is the 16,544-bit number: B0o0o B0o1 Bo, 2 B0o3 Bo, 4 Bo, 5 Bo, 6 BO, 7 B1,0 B1,1 ... B2066 , 6 B2066,7

  B2067.1 B2067.2 B2067.3 B2067.4 B2067.5 B2067.6 B2067 7,

or in polynomial notation:

16543 16542 16541 16540

0.1 ".6543

  Bx 16 + Bo, 1x16542 + Bo, 2x16541 + Bo, 3x16540 + B2067,4X3 + B2067,5x2 + B2067,6x + B2067,7 For a mode 2 sector, form 1 of CD-ROM XA, the code word EDC is the 16480 bit number:

  B16.0 B16.1 B16.2 B16.3 B16.4 B16.5 B16.6 B16.7 B17.0 ...

  B2074.7 B2075.0 B2075.1 B2075.2 B2075.3 B2075.4 B2075.5 B2075.6 B2075.7

  or, in polynomial notation: 6B16 479 + B16,1x16478 + B16,2x16477 + B163x16476 + B16,0x + B16'1 1, X + B63 B2075,4x3 + B2075,5x2 + B2075,6x + B2075,7

  For mode 1 data, the EDC code protects the syn-

  chronization, header, user data and EDC. The four-byte EDC field, in combination with its protected data fields

  including synchronization, header, user data fields

  sator and EDC, for mode 1 data, form the codeword

EDC.

  In accordance with ISO / IEC-10149, the code word EDC

  which is recorded on the CD-ROM disc is made divisible in-

  third by the control polynomial: P (X) = (X16 + x15 + X2 + 1) (x16 + x2 + x + 1) (1) OR P (X) = X32 + X31 + x16 + x15 + X4 + x3 + X +1 by choosing the appropriate value for the four EDC bytes which are

  appended to the synchronization, header and user data fields

  sator. By dividing by the control polynomial the code word EDC which

  is read on the CD-ROM, and determining if the rest of the division is different

  being zero, you can use the EDC code rule to check whether or not errors are present in the data that is read. The EDC rule can be implemented by means of a cyclic code decoder such as that shown in FIG. 5. The circuit could for example be produced in the form of a series of synchronous DQ flip-flops, with

  a reaction established via connected EXCLUSIVE gates

  tees between successive Q outputs and D inputs. Such circuits

  are well known. Pass the entire EDC codeword through

  to the cyclic code decoder, in the form of a serial bit stream.

  After the last bit is entered in the cyclic code decoder, the bits of the CRC register are checked, for example by summing the thirty-two bits of the CRC register. If all the bits in the CRC register are equal to zero, the code word EDC is assumed to be correct, since the EDC rule has not identified any errors in the protected data fields. If the division returns a non-zero value, it must

  then there will be errors in the protected data fields. However

  However, the EDC rule cannot tell which bits are wrong in the

EDC code word.

  Data correction is accomplished in the transfer of

  data from a CD-ROM memory disc by the correction code

  tion of errors (ECC), which is preferably a Reed-Solomon Product Type Code (RSPC), applied in a manner similar to that described in US patents. No. 4,413,340, issued to Odaka et al., and No. 4,680,764, issued to Suzuki et al., mentioned above. Bytes 12 to 2075 of each data sector in the Mode 1 CD-ROM are protected by the double interleaved RPSC code. The protected data bytes of the data sector being read are arranged in a pair of matrices of the type shown in Figure 2. The columns of the matrix are called vectors P, and these are Reed-Solomon code words ( 26, 24) on GF (28). The diagonals of the matrix are vectors Q, which are Reed-Solomon code words (45, 43) on

  GF (28). The sector includes 86 P vectors and 52 Q vectors divided into-

  three data planes, one for the least significant bytes, and the other

  be for the most significant bytes. The P vectors and the Q vectors are the basic units for the application of the error correction mechanism. Each vector P consists of 26 bytes, comprising 2 bytes of parity. We can develop a set of error equations for each of the

  vectors P. If there is an error in a vector P, we can obtain the em-

  error placement (i.e. the particular byte of the vector which is erro-

  born) and the error configuration (i.e. the configuration of bit erro-

  born in the wrong byte) by solving the set of error equations which is

  imposed by the application of Reed- type product code rules

  Solomon. If there are no errors in the vector, the error equations have the trivial solution of an error configuration of zero. Otherwise, the error equations will provide an error location and an error configuration which are then used to generate a corrected byte of data which then replaces the erroneous data in the user data. The vectors Q have a length of forty-five bytes, including the two bytes of parity Q. The Reed-Solomon error decoding for the vectors Q is similar to that which is carried out on the vectors P. Consequently, equations errors for each

  vector Q are established and resolved so as to identify erro- bytes

  born in Q vectors, and to determine the location and configuration

  error for erroneous bytes. The erroneous bytes are then replaced by the correct data configuration which is obtained by

error equations.

  Error correction itself may not be robust enough to preserve the integrity of the data that is transferred to

  from the mass storage device. ER detection processing

  additional reurs is necessary after the correction process

  errors, because the ECC logic has only a limited cor-

  error correction. For each Reed-Solomon P or Q vector, only one error can be detected and corrected. Therefore, if there is more than one error in a codeword, the ECC logic is unable to perform the correct resolution to find the error location and the error configuration. The result will be that ECC logic will not be able to find a true error location or "correct"

  incorrectly a byte that actually contains no errors.

  Therefore, the data processed by ECC logic may not be free from errors, and may in fact contain new ones.

  errors introduced by the error correction logic. Some for-

  my ECC logic realization can correct two errors per word

  code, with the error location information provided by the process

  digital signal generator, but these rules cannot provide an additional benefit sufficient to justify the additional burden of the possibility of more complex error correction. It is desirable to incorporate both ECC logic and EDC logic to provide possibilities for redundant error checking, since the

  error detection logic uses a different approach to logic

  than error correction to detect errors in a sector.

  The application of EDC logic after the er-

  Error in the conventional CD-ROM memory system is a complementary process which more surely guarantees that the sector which has been the subject of error correction is free from errors. Of course, this data protection technique still has limitations, insofar as only the fields protected by the ECC codes and by the

EDC code code are protected.

  We will now describe the functional subsets of a CD-ROM controller in accordance with the present invention, with reference to FIG. 6 which presents a different and more detailed illustration of the

  CD-ROM controller 58 and buffer 68 which are shown

  felt in Figure 3. Referring now to Figure 6, it is noted that the CD-ROM controller receives input data in the form of a serial data bit stream 70 from the digital signal processor 56 (figure 3). The descrambler 72 receives the sector data converted to serial from the digital signal processor and begins descrambling the serial bit stream after the synchronization configuration has passed. The descrambler 72 recovers the CD-ROM sector fields (header, user data, EDC, ECC, etc.) which follow the synchronization field. The data

  scrambled are supplied to the data organization circuit 74 and to the

  cyclic redundant code generator (CRC) 78. The organization circuit

  Data 74 converts descrambled serial data to multi-

  plets, typically in bytes, and it stores the data bytes in appropriate positions in a buffer 76,

  for subsequent error correction operations and a secure transfer

  nal to the host computer. Buffer 76 is typically selected with a capacity large enough to easily store one or more sectors of data during transfer operations. The buffer memory 76 can be a dynamic random access memory

  (or DRAM), or, if higher speeds are desirable, a me-

  static RAM (or SRAM). An advantage of the present invention is that its faster operation makes it possible to use a slower memory, and therefore less expensive, as a buffer memory for

  the data transfer system.

  The data bit stream which is transmitted by the descrambler 72 is supplied not only to the data organization circuit, for recording the data in the buffer memory, but also to the CRC generator 78. The CRC generator 78 is preferably a thirty-two bit cyclic redundancy control circuit which implements the error control polynomial indicated in relation (1), such as the CRC circuit which is illustrated in FIG. 5. The generator CRC receives the incoming data stream, when the data is initially descrambled by descrambler 72 of the CD-ROM controller. The CRC generator 79 performs an initial error detection operation on the data of the incoming bit stream, while the data is still being descrambled and stored in memory, by dividing the incoming bit stream by the error control polynomial. The output information of the CRC generator is an initial remainder configuration designated by CRC0o, which is the thirty-two bit remainder word which results from the application of EDC logic of the type illustrated in FIG. 5 to a train. of uncorrected EDC code word bits. This value CRC0 is supplied to a remainder register in an error detection processor 82, after the bit stream corresponding to the entire EDC code word of the data sector has passed through the CRC generator entirely. If the error detection processor detects that the initial error control remainder CRC0 has a value equal to zero, for example by performing a NOR operation on the bits of the word CRCo, the EDC logic concludes that errors do not are

  not present in the incoming data word. In such a case, the pro-

  error detection stopper 82 can immediately transmit to the data bus of the host computer the data which is stored in the buffer memory 76. In preferred embodiments of the invention, the data of the incoming sector does not effect not a new cycle through the CRC generator 78 and do not cycle through another CRC generator and are not otherwise subjected to a

  classical EDC logic processing. Because EDC logic classi-

  that most of the data in a sector passes in series through a thirty-two bit serial register, conventional EDC logic can be slow. The CD-ROM controller which is illustrated in FIG. 6 allows the incoming sector data to pass once through the EDC logic, and this EDC operation is performed at the same time as the incoming data bit stream is descrambled, organized in bytes and stored in the buffer. Therefore, the time that is consumed by EDC operations is significantly reduced in the mode.

Figure 6.

  In typical embodiments of the CD-ROM controller of Figure 6, error correction in accordance with Reed-Solomon Product Type Codes (RSPC) is performed on the data that is stored in the buffer, by the error correction logic 80, in the conventional manner, except that the error location and error configuration data is

  retained after the wrong bytes have been replaced in the me-

  buffer memory 76. Once the data of the transferred sector has been

  stored in buffer 76, error correction begins.

  The error correction logic 80 takes the RSPC code words from the buffer, determines if there are errors in the various P and Q code words, and, as appropriate, solves the error equations to determine an error location and an error configuration for the wrong data bytes. The error location is a twelve-bit binary number that is generated by error correction logic to designate the byte of a sector that is wrong, and the error configuration is a binary number to 8 bit which is generated by error correction logic to indicate which are

  the bits of a byte that need to be corrected. In embodiments

  tion preferred by the controller of Figure 6, the error location is simply the address of a wrong byte. Error configurations are

  used in association with their associated error locations during

  during the error correction process. For example, if the configuration

  error is 010010102 and if the error location is 12341o, then byte 123410 of the sector data is wrong. In addition, if the original value of byte 12341o is 110101012, then the value of byte 123410 is corrected to become 110101012 @ 010010102 = 100111112,

  ie: correct value = original data configuration Ed con-

  error representation, the $ symbol designating the OR-EXCLUSIVE operator. ECC 80 logic performs error correction on P code words

  and Q respectively, by calculating the corrected data byte (corrected data

  tes = erroneous data (E error configuration), and it also replaces

  following the wrong data byte by the corrected data byte in the

buffer 76.

  In preferred embodiments of the present invention

  error location and error configuration are not re-

  discarded after the wrong byte has been corrected. Instead, the error location and error configuration are saved in a register

  in error correction logic 80 or, more characteristically

  that in the error detection processor 82. This data is used

  taken to calculate a correction to be made to the rest of the ER control

  initial value CRC0, or to calculate an additional correction to ap-

  bring to a previously corrected error control remainder, Ri. After each correction which is made to the data recorded in the buffer memory, the value of the error control remainder Ri is checked to determine whether it is equal to zero. If a value of zero is present at the last iteration of the remainder Ri, the error detection processor 82 can conclude that all the errors in the sector have been corrected and that the data are ready to be transferred from the buffer memory 76

  to the IDE bus or another bus on the host computer. When we do

  In this way operate the CD-ROM controller in Figure 6, the function

  error correction logic 80 is interrupted after

  that a value equal to zero has been returned for the remainder of ER control

laughs Ri.

  The error detection processor 82 indirectly applies

  the error detection code rule of the present invention to data

  which are stored in the buffer, applying the

  EDC code of the invention based on the er location information

  error and configuration error that is generated by the operation of the lo-

  error correction on the initial CRC remainder value or a subsequent value (CRC0o or Ri), to produce an updated CRC remainder value (Ri + 1). For each erroneous byte that is corrected by the error correction logic 80, the error correction logic 80 transmits the error location and error configuration information to the error detection logic 82 The error detection logic 82 recalculates the rest of CRC, R, which comes from the polynomial division.

  control, calculating a correction to be made to the rest, and adding

  both this correction to the rest recorded previously (Ri). Calculating

  a correction to be made to the rest of CRC, the er-

  reurs does not need to divide by the control polynomial the long binary number constituted by all the bits of the sector data which are protected by the EDC code, to calculate the remainder of CRC. After the error detection processor 82 has corrected the remainder Ri in accordance with the error location and error configuration of the most recently corrected byte by the error correction logic 80, the new

  value of the error detection register R is checked. If R is different

  rent from zero, errors remain to be corrected in the data for this sector, and the error correction process continues. If R is

  equal to zero, the error detection processor considers preferably

  rence that all errors in the sector have been corrected, and the pro-

  error correction is preferably stopped and the data is transferred. A new sector is read from the CDROM memory disc, and the processes described above are repeated for the next sector. If after all the vectors P and the vectors Q of a sector

  have been processed, R remains different from zero, the er-

  may be repeated again or, more preferably, the data

  from the sector are read from the disc again.

  We can understand how the processor

  error detection of the present invention with reference to a simplified example based on a 15-bit code word: C (x) = X14 + x11 + x8 + x6 + x5 + X4 + X3 + X, OR c (x ) = (100100101111010), which has the control polynomial: p (x) = x4 + X + 1 The division of c (x) by p (x) gives the quotient q (x) = (10001011001), with a remainder r (x) = (0001), as follows 10001011001 q (x) p (x) 10011) 100100101111010 c (x) ooo0001 remains

  This represents a classic application of er-

  to verify the integrity of the codeword c (x) using the error control polynomial p (x), which could be accomplished initially by the CRC generator 78 in Figure 6. Of course, the word of EDC code which is used in the CRC generator 78 has more than sixteen thousand bits

  in length, and the error controller polynomial is the one that is indi-

  as in expression (1) above. This example also illustrates the simplicity of the division operation of a conventional CRC operation, since it is accomplished in modulo 2 arithmetic and can be performed in serial shift registers in combination with OR gates -EXCLUSIVE. Because the remainder r (x) is different from zero in the above example, the EDC operation indicates that there is an error in the

  code word c (x). You can then perform some form of operation.

  error correction tion which determines that the erroneous bits of the code word c (x) are x10 and x5, so that the error configuration for c (x) is e (x) = (000010000100000). The corrected code word c '(x) is then

  given by c '(x) = c (x) @ e (x) = (1001101010011010).

  It can be demonstrated that c '(x) is correct by the application of classical EDC logic after the error correction operation, in the manner which is implemented by the classical correction circuit

  Figure 1 error and error detection as shown

  below: 10000010110 q (x) p (x) ioi) oioooii C (X p (x) 10011) 100110101011010 c '(x) 0000 remains As previously considered, although this classic EDC procedure (CRC after the completion of the ECC operation) has the advantage of the simplicity of the hardware, it can be a slow process when applied to the EDC codeword at sixteen thousand bits which is usually

  used in storing data on CD-ROM discs.

  Preferred embodiments of the invention correct the remainder of error checking based on the error configuration, and they

  test the rest corrected to determine when it reaches zero.

  As illustrated in the following calculation, the method gives results if-

  milaries to the classic process: 1001111 q (x) p (x) 10011) 10000100001 e (x) + r (x) 0000 remain The error detection processor present incrementally tracks the corrections made to the rest of the error control , it decrements the remainder value according to the corrections and determines when the rest of the error check is reduced to zero. Consequently, the remainder is fully corrected by subtracting from the remainder of the original error check one or more numbers whose sum is equal to the remainder of the original error check. Equivalently, the sum of the original remainder configuration and the error configurations of each of the corrections that are made to the sector data is divisible

  entirely by the error control polynomial, in the il-

  glossy in the previous example. So the er-

  The present invention provides control of the integrity of the data.

  born which is similar to that of classic EDC logic based on the

  CRC control, but the implementation of this er-

  is very different from the logic of error detection

  classic, based on CRC control.

  In the example above, the error configurations consisted

  were in single bits to be placed in specific locations

  ques in the code word. On the contrary, when the detection processor

  tion of errors of the present invention is implemented in a con-

  CD-ROM thrower, the error configuration is a byte and the location-

  error is a twelve bit number that identifies the location of

  the wrong byte among the more than two thousand bytes in the sector. For calcu-

  In order to correct the error check rest, it is necessary to compensate for the error position both on the basis of the error configuration and the error location. Mathema-

  Tically, the error detection processor 82 of the embodiment

  tion of Figure 6 performs the following calculation to correct the most recent error control remainder: Ri + 1 = Ri E {(e.x8X) modulo P (x)} (2) In this expression, R is the error detection result, e is the

  error configuration, X is a number that is obtained from the em-

  error placement e and P (x) is the control polynomial which is indicated in expression (1). In practice, the number Ri Ed (e.x8x) can be long, which means that the modulo P (x) operation can take time. The calculation is however faster than the conventional CRC calculation performed on an entire EDC word. In addition, this error detection processing is performed in parallel with the error correction processing, so that the entire process of error correction and error detection is

  carried out overall more quickly than in the classic circuit represented

feel in figure 1.

  FIG. 7 schematically illustrates a detection processor

  possible error 82 which performs the calculation of relation (2) in the

  Figure 6 CD-ROM controller.

  reurs 82 comprises an error detection processor control unit 100 which is an automaton intended to control the sequence of steps which are included in the calculation of a correction to be made to the remainder of error control. An error location converter 102, or ELC, in Figure 7, converts the error location e to give the 12-bit number. which is then used in the calculation of corrections to be made to the value R. A correction calculation circuit 104 calculates the value e. mod P (x) and it outputs the correction of the remainder. The register

  R 106 records the rest of the error checking, which is initial-

  ment CRC0, and which during the following iterations is the remainder value

  corrected Ri. The error configuration e (eight bits) and the location of er-

  errors are generated by error correction logic 80 when it successfully solves a set of error equations. The error correction logic 80 outputs the error configuration e and the error location e to the error detection processor 82, on respective lines 108 and 110. At the same time, the logic error correction

  outputs a start pulse on a line 112 which

  triggers the operation of the error detection processor, i.e.

  say that the controller which is controlled by the pro-

  error detection stop 100 starts going step by step through

  error detection processing steps.

  The other input information from the ER detection processor

  reurs 82 is the initial CRC0 value which is calculated by the general circuit

  CRC 78 rator of the controller circuit of Figure 6. This value

  Initial CRCo is typically provided to the processor

  error detection by the CRC generator before triggering the error correction processing, or simultaneously with it, and it is

  recorded in the register R 106. The value of the remainder of control of er-

  rC initial CRCo is checked to determine if it is zero.

  If the initial value is zero, preferred embodiments

  of the present invention do not perform any er-

  subsequent laughter. In the event that the initial EDC operation by the CRC generator indicates that there are one or more errors in the data which

  are read, the value CRCo remains in the remainder R 106 until the value

  error correction them triggers the operation of the error detection processor 82. Under the effect of the triggering by the starting pulse, the error location converter 102 converts the error location e to give the twelve-bit number A, which is then supplied to the correction calculation circuit 104. The correction calculation circuit also receives the error configuration e, and from this data the correction calculation circuit 104 calculates a correction to bring to the initial remainder value. OUEXCLUSIF gates 114 sum the thirty-two bit error control remainder word with the correction value, and the sum is then recorded in register R. As a result of the generation of a corrected remainder , the value of the remainder is tested, for example by a NOR operation applied to

  all bits of the remainder word. If the remainder is zero, then we pre-

  assumes that all errors are corrected and the data that is recorded

  stored in the buffer can be transferred immediately-

  or they can be transferred later at the request of the host computer. After error correction operations have successfully corrected data from a sector, a new sector is read

  in the mass memory unit, and the error correction processing

  error and error detection starts again. If, on the contrary,

  remains corrected remains different from zero, the error correction processing

* reurs continues. If all the error correction vectors have been processed once, it is possible to continue the correction processing

  of errors by repeating the decoding of the P and Q vectors decoded previously

  demment. It is however more preferable to read again on the dis-

  that sector data and start the whole process over again

  correction and error detection.

  The CRC generator generates the initial CRC value, i.e.

  say CRC0, by dividing the EDC codeword of a sector by P (x) before error correction operations begin. For a mode 1 CD-ROM sector whose data bytes are Bi, i = 0 to 2351, we have: (B0, ox16543 + B0,1x16542 + ... B2067,6x + B2067,7) - P ( x) = Q0 (x) + CRCo (x) by designating by P (x) the control polynomial and by Q0 (x) the quotient. Error correction logic performs resolution to determine

  an error configuration e and an error location e of the byte erro-

  born, and then she fixes the code word. The corrected EDC code word becomes: Boox16543 ... + (Bg, 0x7 + Bg1x6 + Be2x5 + Bg3x4 + B, 4x3 + Be, 5x + Bg6x + Bg, 7) X8 (2067-) + ... + B2067, 7 + (e0x7 e1x6 + e2x5 + e3x + e4x3 + e5x2 + e6x + e7) x8 (2067'g)

  by designating by ej, with i = 7 (MSB) at 0 (LSB), the bits of the configuration

  error tion e. By dividing by P (x) the code word EDC above, we obtain the remainder R (x) = CRC0 (x) + r (x), with: r (x) = (eox7 + e1x6 + e2x5 + e3x4 + e4x3 + e5x2 + e6x + e7) x (2067 - ') modulo P (x) The correction calculation circuit 104 which is represented in FIG. 7 performs the calculation of r (x) above. Since it is possible to correct more than one error during the error correction process, this calculation can be performed as many times as errors are corrected by the

  error correction logic 80. With the exception of the very first cor-

  rection made to the rest, which works on the initial value CRC0, all the iterations of the error detection processor work on an R (x) which is determined by: R (x) (new value) = R (X) (old value) + r (x) Note that the relations indicated above can be applied

  to mode 2 sectors, form 1 of CD-ROM XA, with modifications

  minor tions. Thus, the error detection processor 82 detects errors by calculating new R values in accordance with the formula R (X) new = R (X) old + {(e.x8 (Le)) modulo P (x)} ,

  with the following notations: e is the error configuration, e is the em-

  error placement and L = 2067 for CD-ROM mode 1 sectors,

  or 2075 for mode 2 sectors, form I of CD-ROM XA.

  Since e is a 12-bit number, a direct calculation of e. x8 (L'É) modulo P (x) will be frequently undesirable, since it requires too much material to be devoted to it, and therefore too high an area on the surface of a chip. It is therefore preferable to decompose the calculation into a number of smaller multiplication operations. We can thus write the calculation of the remainder in the form: R (X) new = R (X) old + {(e. X8X) modulo P (x)}, with A = (L-e). The 12-bit number A can then be broken down into three 4-bit parts, i.e. A = X8.28 +. 4.24 + -0, as shown

  on figure 8. With this transformation, the calculation of configuration of er-

  reur becomes the following: e. x8x = e. X8 (256X '+ 16; .4 + .o) = e. X2048ka + 128k.4 + 8kb - e. (X2048Xa x x128x4 x X8o) So, e.x8kmodulo P (x) = e. (x2048xs x X12814 x x8Xo) .modulo P (x) We can develop this equation using the rule: (A x B) modulo N = {A modulo N) x B} modulo N

  for a representation in the form of a complete product of the cor-

  rection of remainder. The remainder correction calculation e.x8Xmodulo P (x) can be performed by applying. 8 times the operator. X2048 modulo P (x) (multiplication by x2048, then division by P (x) to obtain the rest),. 4

  times the operator.x128 modulo P (x), and .0 times the operator.x8 modulo P (x).

  In a particularly preferred embodiment of an error detection processor according to the present invention, which is shown in FIG. 9, the remainder correction calculations are carried out with a 3-stage polynomial multiplier, 104, having floors 150, 152 and 154

and a counter of À, 136.

  The error detection circuit is in many respects if-

  milaire to the embodiment which is illustrated in FIG. 7. We have therefore limited an additional examination of elements already described. As with the embodiment of FIG. 7, the error detection processor of FIG. 9 stores the remainder of initial error control CRC0, at thirty-two bits, coming directly from the CRC generator 78 (FIG. 6) , in the form of an initial value in the register R 106. In this initial state, the multiplexer 120 is maintained in a state which selects the output of the CRC generator. Whenever the correction logic

  80 finds an error and successfully solves the equations of er-

  appropriate rors, to generate an eight-bit error configuration, e,

  and a twelve bit error location, U, the error correction logic

  reurs applies a start pulse to the control unit

  error detection processor 100. At this time, the cor- rection logic

  error correction also provides the error configuration e and the location

  identify error e in the error detection processor. On receipt of the start pulse, the error configuration input value is transmitted by the multiplexer 140 and it is stored in the register.

  temporary 142, for later calculations.

  Also upon receipt of the start pulse, the

  of the error detection processor of FIG. 9 which correspond to the ELC circuit 102 of the embodiment of FIG. 7 convert the twelve bit input error address, 130, to a value B, and they record the value in the X register 136. X is determined based on both the mode of the CD-ROM sector in which the data is

  saved, which determines the length of the EDC codeword, and the em-

  placing the wrong byte inside the EDC codeword. The mode

  which is read on the CD-ROM disc commands to the multiplexer 132 from four-

  set as output one or other of the EDC code word lengths (2067, 2075) which is appropriate for the different modes, in the form of a twelve bit binary word. If the mode byte which is read is equal to 1, the sector is recorded in the form of mode I data of CD-ROM, so that the multiplexer 132 selects a quantity to be subtracted equal to 2067. In the case on the contrary, a quantity to be subtracted equal to 2075 is selected in correspondence with mode 2, form 1 sectors of CD-ROM XA. A twelve-bit subtractor 134 subtracts the twelve-bit error address from the twelve-bit EDC code word length and provides the result to register A 136. The register A 136 consists of three 4-bit counters X8 , 14 and -o, shown in more detail in Figure 8, which generate three signals y, 13 and a: a = (X0 7 0), p = (X4 * 0), and y = (-8; 0 ) a, p and y respectively control the stages ".x8 modulo P (x)",

  ".x128 modulo P (x)" and ".x2 48 modulo P (x)".

  The three-stage multiplier 104 calculates the remainder correction

  e.x8X modulo P (x) by the following algorithm which is accomplished on the confi-

  error correction previously recorded in the temporary register when (I? 0) temp = {{{temp.x8a modulo P (x)}. x2048 modulo P (x)}. x128p modulo P (x)}; if (i8> 0) then -8 = X8 - 1; if (.4> 0) then 4 = X4 - 1; if (i0> 0) then -o = Xo - 1; } The total number of cycles required is the maximum of (A8, 14, -0), and the result of the multiplication is supplied via the multiplexer

  140 in the temporary register 142. It will be noted here that the order of the three operations

  multiplication / modulo which are carried out by the three stages, 152 and 154 has no effect on the final result which is produced by the

  correction calculation circuit and which is recorded in the time register

  poraire 142, but the configuration which is illustrated optimizes the characteristics

  hardware, this includes reducing the chip area that is consumed by multiplier / modulo circuits and therefore represents a preferred aspect of the present invention. After the multiplier 104 has completed the required number of cycles, the temporary register 142 contains the value of the remainder correction e. x8k modulo P (x). The remainder value is

  then added, using doors EXCLUSIVE 114, to the value

  their (CRC0 or Ri) which is recorded in the register R 106. The multi-

  plexer 120 selects the output of the EXCLUSIVE gates 114 for all error correction operations after the processor

  error detection has been initialized.

  The state of the corrected remainder R can be obtained from the output R = 0. Depending on the value of the corrected remainder, as envisaged above

  in relation to the embodiment of FIG. 7, data se-

  will be transferred, or additional error correction operations

will be accomplished.

  It goes without saying that many modifications can be made.

  brought to the process described and shown, without departing from the scope of the invention

tion.

Claims (20)

  1. Method for transferring data between a   optical disc mass memory (50) and a host computer,   se in that it comprises the following stages: one reads a data chain   born (70) on the optical memory disk (50) and the data string read is converted into a form compatible with recording in a digital memory; the read data string (70) is stored in a buffer memory (76) while supplying the read data string to a first error detection circuit (78); we perform a first   error detection operation on the data string read, to de-   terminate if there are errors in the read data string, at least part of the error detection operation being performed during   that the data string read is being saved in the memory   buffer memory (76); we transfer the data string read to the system   host computer if the first error detection operation determines that no error is present in the data string read; and we perform an error correction operation on the chain   data read (70) if the first error detection operation deter-   mine that there are errors in the data string read,   before transferring the read data string to the host computer.   2. The method according to claim 1, characterized in that it further comprises the following steps, when the error correction operation is carried out: an error is corrected in the data chain read (70); a second error detection operation is carried out for   determine if additional errors remain in the data chain   born read, the second error detection operation generates an error-free signal if the second error detection operation indicates that no uncorrected error remains in the read data string (70); and providing the corrected data string to the host computer,   response to the no error signal which is generated by the second operation error detection ration.   3. Method according to claim 2, characterized in that   the step which consists in carrying out the first er detection operation   reurs produces a first error detection value which is characteristic   ristics of the errors present in the data string read (70), the   first error detection value being recorded.   4. Method according to claim 3, characterized in that   the step which consists in carrying out the second er detection operation   reurs includes the steps of calculating a correction for the first error detection value, correcting the first value of   error detection and to determine if the error detection value cor- rigée is different from zero.   5. Method according to claim 4, characterized in that the first error detection operation comprises dividing the received data chain (70) by an error control polynomial, and in that the first detection value error is a remainder which is calculated by dividing the data string read by the error control polynomial. 6. Method according to claim 5, characterized in that the   second error detection operation is performed under the   dance of an error configuration and an error location which are   determined by the error correction operation.   7. Method according to claim 1, characterized in that the step of converting the read data string (70) comprises operations which are carried out by a digital signal processor   (56) and operations which are carried out by a descrambler (72).   8. Method according to claim 7, characterized in that the descrambler (72) supplies data to the first detection circuit   errors (78) and a data organization circuit (74) which records   be in the buffer memory (76) the received data string.   9. Method according to claim 8, characterized in that the received data chain (70) is coded with a Reed-Solomon code double interlaced.   10. Method for transferring data between a   optical disc mass memory (50) and a host computer,   se in that it comprises the following stages: one reads a data chain   born (70) on the optical memory disk (50) and the data string read is recorded in a buffer memory (76); providing the read data string (70) to a first error detection circuit (78); an initial error detection operation is carried out on the data chain read (70), to determine whether there are errors in the chain   of data read, and a first error detection value is determined   rors characteristic of the errors which are present in the data string read; performing an error correction operation on the read data string (70), identifying a first error in the read data string, and determining an error configuration for the first error; correcting the first error in the read data string (70); and we perform a second error detection operation   to determine if there are any errors in the correct data string aged.   11. Method according to claim 10, characterized in that   the step which consists in carrying out a second error detection operation   reurs includes the calculation of a correction to be made to the first error detection value, based on the error configuration which is   determined for the first error.   12. Method according to claim 11, characterized in that it further comprises the steps which consist in correcting the first error detection value and in recording the first detection value   corrected error, in the form of a second error detection value   errors, and then determining if the second error detection value is different from zero.   13. Method according to claim 12, characterized in that the   second error detection value is determined by a second cir-   error detection circuit, separate from the first error detection circuit laughter.   14. The method of claim 12, characterized in that it further comprises the step of providing the corrected data string to the host computer, after the error correction operation Has been done.   15. Method according to claim 10, characterized in that the read data chain (70) is applied to the first detection circuit   errors (78) while the data string being read is being saved   storage in the buffer memory (76).   16. Method according to claim 10, characterized in that it   further includes the step of transferring to the gold system   host host the data string read, if the first operation of   error detection determines that no errors are present in the read data string (70).   17. The method of claim 10, characterized in that-   an error correction operation is not performed until the   first error detection value is recorded.   18. The method of claim 10, characterized in that the first error detection operation comprises dividing the received data chain (70) by an error control polynomial, and in that the first detection value error is a remainder which is calculated by dividing the data string read by the error control polynomial. 19. The method of claim 18, characterized in that the   second error detection operation is performed under the   dance of an error configuration and an error location which are   determined by the error correction operation.   20. Method according to claim 10, characterized in that the   read data string is coded with a Reed-Solomon code between- double laced.