JP3519684B2 - Data processing device using error correction code - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to recording video data, audio data, computer data, etc. on a medium (for example, an optical disk, a magnetic disk, etc.) or reproducing the data recorded on the medium. The present invention relates to a data processing device using an effective error correction code generation processing method.

The present invention also relates to a data processing apparatus using an error correction code generation processing method which is effective when transmitting or receiving the above-mentioned video data or the like.

Furthermore, the present invention relates to a recording device, a reproducing device, a transmitting device, which adopts the above-mentioned error correction code processing method,
Effective for receiving devices.

In particular, the present invention is characterized by a method of performing error correction processing using a buffer memory when performing error correction code processing.

[0005]

2. Description of the Related Art When video data, audio data, computer data, etc. are recorded on, for example, an optical disk or a magnetic disk, an error correction code is added to a data block. In the error correction code addition processing, the data block is temporarily stored in the memory, and the error correction code for the row and column of the data block is generated.

The error correction code added to a row is usually called inner parity and abbreviated as PI, and the error correction code added to a column is usually called outer parity and abbreviated as PO.

[0007]

In the process of adding the error correction code, when the data block is temporarily stored in the memory before the error correction code is generated, the data on the memory is partially damaged (error occurs). There is. This is considered to be due to the data pattern and the mounting state of the memory. Also, sudden noise from the outside may be affecting.

The error generated at this time is called a memory error. In such a case, an error correction code for a data block in which a memory error has occurred (hereinafter referred to as a modified data block) is generated, and this error correction code is added to the modified data block and recorded on a recording medium. .

During reproduction of the recording medium, the error correction processing circuit executes error correction processing on the modified data block using the error correction code. That is, the modified data block is correctly reproduced. This means that the data block containing the memory error has been correctly reproduced. However, the memory error is an error that is unnecessary for the original data. Therefore, when the above memory error occurs, it is impossible to restore the original correct data.

Therefore, in the present invention, even if a data error (memory error) occurs in the memory, it is possible to restore the original correct data and devise a method of using the memory. An object of the present invention is to provide a data processing device that obtains operational reliability.

[0011]

The basic idea of the error correction code processing method of the present invention is as follows.

That is, according to the present invention, in a transmission or recording system, an error correction code PI is generated for each row of a data block having a matrix structure, and the error correction code PI and the data block are stored together in a memory. Next, when the information data block to which the error correction code PI is added is read from the memory, an error correction process using the error correction code PI is performed on the row of the information data block. Characterize.

When an uncorrectable case is detected during the error correction process using the error correction code PI, the area of the memory in which the row or the information data block is stored is changed. In this way, the memory error can be avoided. Also, the area where the memory error has occurred is learned, and the area is not used thereafter.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

First, referring to FIGS. 1 to 8, the structure of an error correction code addition circuit and an error correction circuit in a data storage / reproduction device will be described using an example of a DVD (digital versatile disk).

First, referring to FIGS. 1 to 6, the DV
The structure of the recording data of D will be described.

FIG. 1 is a diagram showing a data processing sequence for obtaining a physical sector in a DVD. Sectors are “data sectors”, “recording sectors”, according to the stage of signal processing.
And called the "physical sector". In the data sector,
As shown in FIG. 2, the main data is 2048 bytes, the identification data (ID) is 4 bytes, and the ID error detection code (IE
D) (code for detecting ID error) is 2 bytes, copyright management information (CPR 6 bytes of MAI) and 4 bytes of an error detection signal (EDC) (a signal for detecting an error in this data sector). The process of adding ID, IDE, CPR_MAI, and EDC is steps A1 to A3 in FIG. Step A
At 1, an ID is added to the main data. Step A2
Then, IED is added. Furthermore, C in step A3
PR_MAI is added.

Next, the EDC for the main data is calculated, and this EDC is added to the main data. next,
The scrambled data is the main data (2
048 bytes) (steps A4, A5, A
6). After that, 16 scrambled data sectors are collected, and a crossed Reed-Solomon error correction code is generated and added to these 16 data sectors (step A6). The recording sector is a sector after the ECC is added, and is a data sector to which the error correction code PI and the error correction code PO are added (step A).
7). The physical sector is a sector after 8/16 modulation in which a synchronization code (SYNC code) is added to the beginning of every 91 bytes of the recording sector (step A8).

Next, the structure of the data sector of the DVD will be further described with reference to FIG.

The data sector is 2064 bytes including 2048 bytes of main data, that is, 172 bytes × 1.
It consists of two lines. That is, in the data sector, main data is 2048 bytes, identification data (ID) is 4 bytes, and I
D error detection code (IED) is 2 bytes, copyright management information (CPR 6 bytes of MAI) and 4 bytes of error detection code (EDC) are included.

FIG. 3 shows a feedback shift register for generating scramble data Sk for scrambling main data (2048 bytes) in step A4. As the initial value for generating the scrambled data Sk, for example, a part of the data of the data sector ID is used. The scramble data Sk scrambles the main data (2048 bytes) Dk of the data sector. As a result, the main data Dk 'after scrambled
Is the result of exclusive OR processing of Sk (k = 0 to 2047) with respect to Dk.

The structure of the ECC block will be described with reference to FIG.

The data block is formed as 172 columns × 192 rows in which 16 data sectors of 172 bytes × 12 rows are gathered. A Reed-Solomon error correction code is generated and added to this 172 columns × 192 rows. First, a 16-byte error correction code PO is generated and added to each of the 172 columns. Each row of PO series has 19
It consists of 2 bytes + 16 bytes, that is, 208 bytes. Next, the error correction code PI of 10 bytes is generated and added to all the 208 rows including the row of the error correction code PO. One ECC block is 182 columns × 208 rows to which the error correction codes PI and PO are added. The same code pattern can be obtained by reversing the order of generation of PO and PI.

One column in the vertical direction of the ECC block is PO
A series and one row in the horizontal direction are called a PI series. One PO series is composed of 192 bytes + 16 bytes, that is, 208 bytes, and error correction of maximum 8 bytes is possible within one series. One PI sequence is composed of 172 bytes + 10 bytes, that is, 182 bytes, and error correction of up to 5 bytes is possible within one sequence.

Next, the structure of the recording sector will be described with reference to FIGS.

With respect to the ECC block having 208 rows × 182 columns, 16 rows forming the error correction code PO are separated for each row. Then, the separated lines are inserted one by one between every 12 lines of the data section of 192 lines, and are rearranged as shown in FIG. This is called PO line interleaving. Therefore, the ECC block after row interleaving is 13 rows x 182 bytes (= data with PI (12 rows) + PO (1 row))
The 16 parts are gathered together.

One recording sector is, as shown in FIG.
A sector composed of data (12 lines) plus PO (1 line), that is, (13 lines x 182 bytes) added with PI, and 16 ECC blocks after row interleaving are shown in Fig. 6. It means that it is composed of recording sectors of.

The physical sector is a recording sector (2366 bytes) of 13 rows × 182 bytes, with a sync (SYNC) code added to the beginning of every 91 bytes of each row, and sequentially modulated row by row from 0. Is. The 91-byte data with the SYNC code added to the beginning is called a SYNC frame. Therefore, the physical sector is 16 sets x 2 SYN
It is composed of C frames.

Next, the error correction code adding circuit in the data recording device will be described with reference to FIGS. 7 and 8.

In FIG. 7, the user data transmitted from the host is sequentially stored in the buffer memory 2. When the stored user data is taken out from the buffer memory 201, it is processed by the sector information addition means 202, EDC generation and addition means 203, and scramble means 204. This processing is performed for each 2048-byte main data and converted into one data sector.

The sector information adding means 202 adds identification data (ID) of 4 bytes, ID error detection code (IED) of 2 bytes, and copyright management information (CPR_MAI) of 6 bytes to the main data. EDC generation and addition means 203
Generates and adds 4 bytes of error detection code (EDC) to a total of 2060 bytes of data to generate a total of 2064 bytes of data sector. Scramble means 204
Scrambles the main data in the data sector.

The scrambled data sector is EC
Sequentially stored in the C memory 205. This ECC memory 2
There are 1 data sector of 172 bytes x 12 rows in 05.
A data block of 172 columns × 192 rows is formed by collecting 6 pieces. An error correction code is generated and added to the data block of 172 columns × 192 rows by the PI generation / addition means 206 and the PO generation / addition means 207. As a result, one ECC block is formed.

As described above, the ECC block is row-interleaved and then transmitted to the modulation / synchronization adding means 208. The modulation / synchronization adding means 208 converts 8-bit input data into a 16-bit code word for the input row-interleaved ECC block. That is, 8/16 modulation is applied. Next, the SYNC code is added to the beginning of every 91 bytes of the input data to form a physical sector. The formed physical sector is transmitted as recording data and recorded on the medium.

Here, the effect of the error correction code will be described.

A data reproducing system including error detecting and correcting means reproduces recorded data. In the reproducing process, when an error occurs in the reproduced physical sector data, error correction is performed on the ECC block including the error using an error correction code. The error detection and correction means can restore an ECC block that does not include an original error within the range of its correction capability.

Next, an error correction code generation processing system on the data reproducing side will be described with reference to FIG. The reproduction data read from the recording medium is separated from the sync code by the sync separation / demodulation means 221 and then demodulated for the 8/16 modulated data. As a result, the recording sector is taken out. However, when recording and reproducing the recorded data, an error (reproduction signal error) occurs due to a defect, noise, jitter, crosstalk, etc. of the disc, and thus the reproduction data includes an error.

The recording sectors taken out are sequentially stored in the ECC memory 205, and each recording sector is composed of 16 recording sectors.
An ECC block of 82 columns × 208 rows is constructed. Error correction is performed on the ECC block of 182 columns × 208 rows by the PO correction unit 222 and the PI correction unit 223, and the error of the reproduction signal is restored.

The PI correction means 223 calculates the error pattern detection value syndrome for each row of the ECC block and corrects the error when an error is detected. The syndrome becomes 0 when the original data is reproduced without error. When a data error occurs during signal recording or transmission, the syndrome has a value determined by an error position indicating the position where the error occurred and an error pattern indicating the error state.

The PO correction means 222 is a PO series 208.
The byte data is taken out from the memory 205 and a predetermined calculation is performed. By this calculation, if the syndrome is not 0, the PO series is error-corrected. In this error correction processing, the error correction code PO of 16 bytes enables error correction of up to 8 bytes in the series. When error correction is performed on the data to be corrected and the data at the time of generating the error correction code is restored, the syndrome becomes 0. The above operation is performed for all 182 columns of the ECC block.

When an error of 8 bytes or more exists for one PO series, it becomes impossible for the PO correction means 222 to correct the error. However, even in this case, the PI correction means 223 causes a maximum of 5 for the PI sequence.
Since byte error correction is possible, if the error contained in one PI sequence is within 5 bytes when the PO correction is performed on the 182 column, the error can be corrected.

Further, by repeating the PO correction and the PI correction, there is a possibility that an error that could not be corrected by one PO correction and PI correction can be corrected. When all the syndromes become 0, the error correction of the ECC block ends.

The error-corrected ECC block is transmitted to the descrambling means 224. The descrambler 224 adds the scrambled data to the 2048 bytes of the main data of the scrambled data sector (exclusive OR operation), descrambles the main data, and stores it in the buffer memory 201.

The EDC error detection means 225 detects an error in the data sector based on the 4 bytes of the error detection code (EDC) included in the data sector, and if an error is detected, the sector is replayed. The data sectors stored in the buffer memory 201 are sequentially transmitted to the host.

By the way, the buffer memories 205 and 201
As for the DRAM (Dynami
c-RAM) is used. However, due to the structure of the DRAM, the data on the memory may be rarely damaged (memory error) depending on the data pattern and the mounting state of the memory. When some of the data on the memory is damaged (memory error) and the data block is modified and error correction codes PI and PO are generated and added,
The error correction codes PI and PO are correct error correction codes for the data modified by the memory error.
If the ECC block having the error correction code generated for this modified data is recorded and reproduced as it is, the modified data will be restored even if error correction processing is performed after the reproduction.

Here, referring to FIG. 9, 172 bytes ×
A case where a memory error 32 occurs in a part of the data block 36 of 192 rows and the data block is modified will be described.

First, the error correction code PO is generated and added to each of the 172 columns by the PO generation and addition means 9, but the error correction code PO33 (16 bytes) of the column 31 is modified by the memory error 32. It is generated based on the created data.

Next, for all the 208 lines including the error correction code PO, the PI generation / addition circuit 8 sets 1
A 0-byte error correction code PI is generated and added. The error correction code PI 36 (10 bytes) generated for the row 34 is generated based on the data modified by the memory error 32.

Further, the error correction code PI 37 generated for the 16 lines of the error correction code PO is the memory error 32.
It is generated based on the data including the error correction code PO33 generated based on the data modified by.

As a result, a normal error correction code is added to the data block modified by the memory error 32. At this time, the error pattern detection value syndromes of the PI series for the 208 row in which the error 32 exists and the PO series for the 182 column are all 0, and EC
The C block is regarded as having no error. Actually, the original data is modified by the memory error 32.

Here, an ECC block generated based on the modified data block is recorded on a recording medium,
Consider the reproduction data when reproduced from this recording medium.

The reproduced data is subjected to error correction processing using an error correction code. Here, the error that has occurred in the reproduced data is corrected within the range of the correction capability, and the reproduced data is restored. However, the memory error contained before recording cannot be corrected. That is, even if the error correction code PO33 is used to correct the error in the PO series 31, the error correction is normally completed after the data including the memory error 32 is reproduced, and the original user data cannot be restored. Will be.

On the reproducing side, when a memory error occurs in the data on the buffer memory, the data including the memory error may be transmitted to the host as user data.

(Points to which the present invention focuses) As described above, when the data on the memory is damaged (error occurs),
Since an error correction code is generated based on the data modified by the memory error and recorded on the recording medium, the data modified by the error is restored even if this data is read during reproduction and error correction processing is performed. However, it is impossible to restore the original correct data.

When data on the memory after error correction is damaged (error occurs) during reproduction, there is a possibility that erroneous data will be transmitted to the host.

In order to prevent data corruption (error occurrence) on the memory, it is necessary to realize the memory for storing the data with a memory having a structure that does not cause data corruption, for example, S-RAM. It is not preferable in terms of cost.

Therefore, according to the present invention, there is provided an error correction code generation processing method, an apparatus, and a method thereof, which enable error correction code generation processing without loss of original data even when an error occurs in a memory. Recording device used,
A reproducing device, a transmitting device, and a receiving device are provided.

(Basic Concept of the Present Invention) The basic idea of the error correction code generation processing in the present invention is to generate and add an error correction code PI to each row for data of a plurality of rows. Means, a buffer memory for storing the data added with the PI error correction code obtained by the PI generation and addition means, and the error correction code PI added to each row by reading the data from the buffer memory.
PI error correction means for performing error correction on each line using
Memory control means for determining a defective area of the buffer memory based on the result of error correction performed by the PI error correction means and replacing this area with another area is provided.

That is, the error correction code PI is generated and added to the data before being stored in the buffer memory, the data to which the error correction code PI is added is stored in the memory, and stored in the buffer memory. The error correction code PO is generated and added to the read data, and the error correction code P is added to the data read from the buffer memory.
The error correction process using I is performed.

In the error correction process using the error correction PI, when a repeated memory error occurs, the error occurrence area of the buffer memory is replaced with another area.

As a criterion for the repeated occurrence of the memory error, it is repeatedly determined whether or not the memory error occurs at a specific position (address).
Also, it is determined whether or not the number of uncorrectable memory errors repeatedly occurs in a specific area. There is also a method of repeatedly determining whether or not a memory error has occurred at the position where the error correction code PO exists.

When replacing the error occurrence area with another area, the line in which the memory error has occurred is replaced with another area. In other words, there is a method of performing replacement processing in units of lines. There is also a method of performing replacement processing in data block units.

Specific examples of the characteristic portions of the present invention will be described below in detail with reference to the drawings.

First, the error correction code addition circuit in the data recording apparatus according to the first embodiment of the present invention will be described with reference to FIG.

User data from the host computer is converted by the sector information adding means 5 into one data sector for each 2048-byte main data.

The sector information adding means 5 adds identification data (ID) 4 bytes, ID error detection code (IED) 2 bytes, and copyright management information (CPR_MAI) 6 bytes to the main data (2048 bytes). . EDC
The generation and addition means 6 uses ID, IED, CPR_MAI
The error detection code (EDC) 4 bytes is generated and added to the total data of 2060 bytes including, and a total data sector of 2064 bytes is generated. The scramble means 7 is
The scrambled data is the main data (2048 bytes)
Is added (exclusive OR operation) to scramble the main data.

The PI generation / addition means 8 applies the error correction code PI (10 bytes) to each row (172 bytes) of the scrambled data sector (or data block) (172 bytes × 12 rows = 2064 bytes). To generate. Then, the generated error correction code PI is sequentially stored in the buffer memory 2 via the memory control means 20. Also, the corresponding data of 172 bytes × 12 rows is sequentially stored in the buffer memory 2 via the memory control means 20. As a result, data (information data block) to which PI of 182 bytes × 12 rows is added is generated. Such data processing is continued, and 16 information data blocks to which the error correction code PI is added are constructed in the buffer memory 2. That is, in the buffer memory 2, the data sector (PI additional data) of 182 bytes × 12 rows is 16
Individually collected, a set PI additional data (or set information data block) of 182 bytes × 192 rows is constructed.

Error correction code PI generated by the above processing
Is a normal error correction code PI whose original data is the original data.

Here, the PO generation / addition means 9 has the set information data block (18) stored in the buffer memory 2.
An error correction code PO (16 bytes) is generated and added to each column (192 bytes) of 2 bytes × 192 rows. As a result, the ECC block to which the error correction codes PI and PO are added is constructed with respect to the set information data block stored in the buffer memory 2.

Since the buffer memory 2 has a function of accumulating the data transmitted from the host computer until it is recorded on the recording medium, it has a sufficient capacity to store a plurality of ECC blocks and is composed of, for example, a DRAM. There is. In the DRAM, the data on the memory may be rarely damaged depending on the data pattern and the mounting state of the memory. A so-called memory error may occur. Further, when the previous error correction code PO is generated in such a state, this error correction code PO becomes an error correction code whose original data is data including a memory error.

The ECC block in the buffer memory 2 is
Each row (182 bytes) is read out and stored in the row memory 3. The PI correction means 10 uses the row memory 3 to set P
Perform I correction processing. Here, the previous memory error is corrected, and the original data (normal ECC block) is recovered. The row memory 3 is, for example, SRAM (Static-RAM)
And has a capacity capable of storing one row (182 bytes) of the PI series.

The row data output from the row memory 3 is sequentially sent to the modulation / synchronization adding means 4, where the 8/16 modulation and the synchronization code are added, and the data is output as the recording data on the recording medium.

FIG. 11 shows a state in which an error (the above-mentioned memory error or the error 42 caused by an external noise or the like) occurs in a part of the data of the ECC block output from the buffer memory 2.

In the present invention, the error correction code PI is generated and added before the data is stored in the buffer memory 2.
The means 8 uses the sector memory to generate the error correction code PI. Therefore, the error correction code PI is the error correction code based on the original data over the entire 192 rows including the row 45. That is, the error correction code P of FIG.
I is an error correction code created for data in which the error 42 does not exist.

On the other hand, the PO generation / addition means 9 cooperates with the buffer memory 2 to generate the error correction code PO based on the data of each column (192 bytes). Therefore, column 41
The error correction code PO44 (16 bytes) regarding the error correction code PO44 is an error correction code created based on the data including the memory error 42.

In the product code, the part 48 of the error correction code corresponding to the error correction code generates the code PI first and then adds the code PI, and then generates and adds the code PO.
Even if O is generated and added and then the code PI is generated and added, the same code pattern can be obtained.

The error correction code PI is a correct error correction code added to the original data before the error occurred. Therefore, it can be said that the error correction code PO generated and added to the block of the error correction code PI is a correct error correction code based on the original data. In addition, FIG.
Other columns than the column 41 out of the 172 columns shown in (171)
It can be said that the error correction code PO added to is also a correct error correction code.

When such an ECC block is read from the buffer memory 2 in row order and subjected to PI correction processing in the row memory 3, the error 42 in the row 45 is easily PI-corrected. That is, the row 45 of correct data is restored.
In addition, the P created for the data including the error 42
By performing PI correction on each line of O series,
Corrected to the correct PO system. That is, PI for line 46
By performing the correction, one byte 43 is corrected. Similarly, the correction is performed on the other rows (the positions indicated by the triangles in the figure) to generate the correct PO system.

The above processing is performed by using the row memory 3 and EC
It has been described that the PI correction process is performed on all the rows of the C block. However, the present invention is not limited to this, and the PI correction process may be performed only on each line at the position of the triangular mark in the figure in order to shorten the processing time. This is because if the PO system at the position indicated by the triangle in the figure is a correct error correction code, memory error 4
2 is because it can be easily corrected later.

In the above description, an ECC block in which PO blocks are not distributed row by row in the aggregate data block has been used. However, in the actual ECC block, the error correction code PO is as described in FIGS.
It is distributed row by row in the aggregate data block. That is, the error correction code PO is applied to the aggregate data block of 12 rows.
The error correction code PO is dispersed so that there is one row of.

Although the reproduction system is also shown in FIG. 10 described above, this will be described later.

Next, the function of the memory control means 20 will be described. The memory control means 20 requests the storage or retrieval of data from the PI generation / addition means 8, the sync separation / demodulation means 11, the PO generation / addition means 9, the PO correction means 9, the PI correction means 10, and the row memory 3. box office. In response to this request, the memory control means 20 causes the buffer memory 2
Data is written to or read from the buffer memory 2. In this case, the memory control means 2
0 can control the data storage position so that the defective memory area of the buffer memory 2 is not used.

It is assumed that the PI correction means 10 requests the memory control means 20 to take out data and one row of data is stored in the row memory 3. Next, it is assumed that the PI correction means 10 performs error correction processing on the data in the row memory 3. When an error is detected at this time, the PI correction means 10 sends error information indicating the position of the error to the memory control means 20.

The memory control means 20 registers in the error address register 21 the address in which the error data was stored. In the error address register 21,
When an error occurs at the same address, the number of times is also registered. Here, if the memory error occurs repeatedly at the same address twice, for example, the memory control means 20 determines that address as a defective address. Then, the memory control means 20 registers the defective address information in the defective address register 22. The criterion for registering the defective address information in the defective address register 22 may be repeated three times or more.

The defective address information registered in the defective address register 22 is referred to by the data write address and read address control section 23, and the defective address is not used.

For example, it is assumed that the address (A + J) is registered in the defective address register when the data strings (B0,0) to (B207,181) of the ECC block in FIG. 12A are stored from the address A. Then Fig. 12
As shown in (B), (B0, J) is the address (A +
J) is skipped and stored at the address (A + J + 1).
At this time, may be stored in the alternate area in advance prepared (B0, J). Further, when managing the defective memory area, it may be managed not only on a byte basis but also on a line basis.

Next, the reprocessing of data when the PI correction fails (when it is impossible) will be described.

If 6 or more memory errors occur in one line, PI correction cannot be performed. Also, 1 ECC
If 6 or more memory errors occur in the block data, the PI correction for PO (16 rows) may fail.

When the PI correction process is performed and it is detected that the number of errors exceeds the correctable number, the memory area to be used is changed and the process is performed again. At the time of reprocessing, the host computer is requested to retransmit the data. Then, the data to which the error correction code PI is added again is stored in the buffer memory 20 via the memory control means 20. At this time, the memory area used is an area in which the error area in which the error has occurred is replaced, or an empty area different from the error area.

In each row of the area where the error correction code PO is stored, if the number of errors exceeds the correctable number of errors, reprocessing can be performed by the following method.

When performing the reprocessing, the set information data block (including the error correction code PI) of 192 rows × 182 bytes stored in the first storage area of the buffer memory 2 is stored in the second storage area of the buffer memory 2. Move to the storage area of. Then, after performing PI correction processing for each row, P is again used by using the second storage area in the buffer memory 2.
O generation and addition processing is performed. In this case, the reprocessing can be performed inside the device without requesting the host computer to retransmit the data.

FIG. 13 is a diagram for explaining the movement of data on the buffer memory 2.

The ECC block (n) stored from the address A0 is moved by the data moving means 24 to a free area starting from the address A3. At this time, the moved data includes memory errors included in the area of address A0, but these memory errors are repaired by performing PI correction processing on each row. The PO generation and addition processing is executed using the data after the PI correction processing is executed. If the number of memory errors occurring at this time is 5 or less, the generated error correction code PO can be corrected by PI correction processing.

Returning to FIG. 10, the operation during data reproduction will be described.

The reproduction data read by the optical head from the recording medium is introduced into the sync separation / demodulation means 11.
In the sync separation / demodulation means 11, sync detection and separation from the reproduced data and demodulation of 8/16 modulation are performed. As a result, the recording sector is obtained. However, when data is recorded on or reproduced from a recording medium, an error occurs in the data due to a scratch or noise on the disc, and thus the data in the recording sector may include the error.

The recording sector taken out is stored in the memory means 20.
Are sequentially stored in the buffer memory 2 via 16 and 16 recording sectors are collected, and 208 rows × 1 in the buffer memory 2
82 columns of ECC blocks are formed. This 208 lines x
PO correction means 1 for the ECC block of 182 columns
4. The PI correction means 10 performs error correction.

The error-corrected ECC block is read from the buffer memory 2 row by row (172 bytes) in the order of data transmission and stored in the row memory 3. Here, the PI correction means 10 uses the row memory 3 to perform PI correction on 172 bytes of each row. As a result, even if a memory error occurs in the scrambled data sector in the buffer memory 2, it is repaired by PI correction.

Next, the scramble canceling means 13 converts the scrambled data to the main data (2048 bytes) of the scrambled data sector (exclusive OR operation) to generate the data sector before scramble. Further, the EDC error detection means 12 detects an error in the data sector by using 4 bytes of the error detection code (EDC) included in the data sector. When it is detected that the data sector is error free, the data sector is sent to the host.

As described above, the present invention is effective for a signal transmission / recording / reproducing apparatus capable of performing error correction code generation processing without loss of original data even when an error occurs in a memory. Further, according to the present invention, instead of simplifying the defect inspection of the buffer memory and increasing the yield, even if the occurrence rate of the memory error is increased, it is possible to perform the recording on the recording medium without losing the original data, which is inexpensive. It is effective when used in various signal transmission / recording and reproducing devices. The transmission / reception system can be applied to various devices in the digital communication field. Radios like mobile phones,
It is a transmission / reception terminal between computers, a television transmission / reception device, and the like. In the field of recording / reproducing system, the present invention is
It is effective when used in a DVD device, a CD device, and a memory device having a communication function.

[0099]

As described above, according to the present invention, even when a data error (memory error) occurs in the memory, the data using the error correction code that can restore the original correct data is used. It is possible to provide a processing method, a recording system or a reproducing system, a transmission system and a receiving system that employ this method.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a data processing procedure for obtaining a physical sector in a DVD.

FIG. 2 is an explanatory diagram showing the structure of a data sector in a DVD.

FIG. 3 is an explanatory diagram of a feedback shift register that generates scrambled data.

FIG. 4 is an explanatory diagram showing an ECC block.

FIG. 5 is an explanatory diagram showing recording sectors.

FIG. 6 is an EC in which the error correction code PO is interleaved.
Explanatory drawing which shows C block.

FIG. 7 is a block diagram shown for explaining an error correction code generation method in a recording system of a conventional recording / reproducing apparatus.

FIG. 8 is a block diagram shown for explaining an error correction processing method in a reproducing system of a conventional recording / reproducing apparatus.

FIG. 9 is a diagram for explaining an error correction code when a DRAM memory error occurs in the conventional recording / reproducing apparatus.

FIG. 10 is a block diagram of a recording system and a reproducing system shown for explaining an embodiment of an error correction code generation method according to the present invention.

FIG. 11 is an explanatory diagram shown for explaining an example of error correction processing by the error correction code generation method according to the present invention when a memory error occurs.

FIG. 12 is an explanatory diagram shown for explaining an example of processing an ECC block by the error correction code generation method according to the present invention when a memory error occurs.

FIG. 13 is an explanatory diagram shown for explaining another example of processing an ECC block by the error correction code generation method according to the present invention when a memory error occurs.

[Explanation of symbols]

1 ... Sector memory, 2 ... Buffer memory, 3 ... Row memory, 4 ... Modulation / synchronization addition means, 5 ... Sector information addition means, 6 ... EDC generation and addition means, 7 ... Scramble means, 8 ... PI generation and addition means , 9 ... PO generation / addition means, 10 ... PI correction means, 11 ... Sync separation / demodulation means, 12 ... EDC error detection means, 13 ... Scramble deactivation means, 14 ... PO correction means.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI G11B 20/18 532 G11B 20/18 532B 544 544A H03M 13/29 H03M 13/29 (56) Reference JP-A-11-3290 ( JP, A) JP 4-205133 (JP, A) JP 10-229344 (JP, A) JP 2002-185335 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB) Name) G06F 12/16 G06F 11/10 G11B 20/18 H03M 13/29

Claims (5)

(57) [Claims] 1. PI generation and addition means for generating and adding an error correction code PI (P bytes) to each row for a plurality of rows of data, each row of which is N bytes, and the PI generation and addition. The buffer memory for storing the data added with the PI error correction code, in which one row obtained by the means is composed of N + P bytes, and (M × (N + P)) bytes of M rows × (N + P) columns
Information data block added with error correction code PI
(K × (M × (N + P)))
And a buffer memory
Error correction to each column of the set information data block using
Error correction product code generated and added with S byte of plus sign PO
Generation and addition as PO block (ECC block)
Means and PI error correction means for performing error correction on each row by using the error correction code PI added to each row while using the row memory before reading and transmitting the data from the buffer memory; When the error is corrected by the correction means,
A memory that stores information of a memory area of the buffer memory in which data in which an error is detected is stored and replaces the memory area of the buffer memory in which data in which an error is repeatedly detected is stored with another memory area A data processing device using an error correction code, comprising: a control means. 2. A 1 sent from a host computer
PI generation and addition means for generating and adding an error correction code PI (P bytes) to each row with respect to a plurality of rows of data each having N bytes, and 1 obtained by the PI generation and addition means A buffer memory that stores data to which a PI error correction code is added, in which rows are composed of N + P bytes, and an error correction code PI, which is composed of (M × (N + P)) bytes in M rows × (N + P) columns, is added. The collected information data blocks are aggregated into a set of (K × (M × (N + P))) bytes, and the error correction code PO is added to each column of the aggregate information data block by using the buffer memory. PO generation and addition means that is an error correction product code block (ECC block) in which S bytes are generated and added, and before reading and transmitting the data from the buffer memory, When the PI error correcting means for performing error correction of each line with the added error correction code PI, which in this PI error correcting means error correction was performed,
When it is detected that the number of errors that can be corrected is exceeded, new data before the addition of the error correction code PI is requested to the host computer again, and the PI is generated and added to the new data. It generates again the data which the error correction code PI is added using means, this again
To store the data in the buffer memory, error correction code, characterized by comprising a control means for specifying a different second storage area from the first storage area storing the last of the data Data processing device using. 3. PI generation and addition means for generating and adding an error correction code PI (P bytes) to each row with respect to a plurality of rows of data, each row of which is N bytes, and the PI generation and addition. One row obtained by the means is a buffer memory for storing the data added with the PI error correction code composed of N + P bytes, and (M × (N + P)) bytes of M rows × (N + P) columns. K pieces of information data blocks to which the error correction code PI is added are aggregated to form (K × (M × (N + P))) bytes of aggregate information data blocks, and each of the aggregate information data blocks is formed by using the buffer memory. PO generation and addition means for generating an error correction product code block (ECC block) in which S bytes of the error correction code PO are generated and added to the column, and the data is read from the buffer memory and transmitted. Before that, the PI error correction means for correcting the error in each row using the error correction code PI added to each row, and the error correction for the row in which the error correction code PO exists is performed by this PI error correction means. When it is detected that the number of errors that can be corrected is exceeded, the (K × (M × (N +) stored in the first area of the buffer memory is detected.
P))) bytes of aggregate information data block are moved to a second area of the buffer memory, and the (K × (M × (N +)) in the second area.
P))) For the byte aggregate information data block, an error correction code P is added to each column through the PO generation and addition means.
O data processing apparatus using an error correction code, characterized by comprising a control means for generating and adding an S byte. 4. An error correction code PI is added (K × M ×
(N + P))) bytes of aggregate information data block,
When an error correction code PO block of (S × (N + P)) bytes is sent from the transmission means or the recording medium (however, the set information data block is M rows × N columns (M × N)). A P-byte of the error correction code PI is added to each row of a data block of a set of (K × (M × N)) bytes in which K data blocks each composed of bytes are aggregated. A block is one in which S bytes of the error correction code PO are generated in each column of the set data block and the block of the error correction code PI.) Using the buffer memory, the set data is generated by the error correction code PI and PO. First means for performing a first error correction process on an error data byte of a block; and for data after performing the first error correction process,
Further, using a small memory having a smaller capacity than the buffer memory, the second means for performing the second error correction processing on the row again by the error correction code PI, and the PI system error correction by the second means. When the error is detected, the information in the memory area of the buffer memory in which the data in which the error is detected is stored is stored and repeated.
And a memory control means for replacing the memory area of the buffer memory in which the data in which the error is detected is stored with another memory area. 5. When an error correction product code block (ECC block) is sent from a transmission means or a recording medium, (wherein the ECC block is M rows × N columns (M × X)).
A P-byte of the error correction code PI is generated and added to each row of a data block composed of N) bytes, and M rows x (N
A set information data block of (K × (M × (N + P))) bytes, which is a set of (M × (N + P)) bytes of + P columns and which has K information data blocks added with the error correction code PI. Then, (S = K × Q) bytes of the error correction code PO are generated and added to each column of the set information data block, and the error correction code PI is added every Q bytes of the error correction code PO. By distributively arranging each of the K information data blocks, each information data block is configured to have a constant value (M + Q) × (N + P) bytes, which is composed of information data and an error correction code. Block), using the buffer memory, the error correction codes PI and PO
According to the first means for performing the first error correction processing of the error data byte of the data block, and for the data after performing the first error correction processing,
Further, using a small memory having a capacity smaller than that of the buffer memory, the second means for performing the second error correction process on the row by the error correction code PI again, and the PI correction by the second means. Occasionally, when it is detected that has exceeded the error correctable error count, the new data before the error correction code PI is added to request again to the host computer, the relative new data, the PI using the generated and adding means generates again the data which the error correction code PI is added, this re
When storing the degree data in the buffer memory,
Data processing apparatus using an error correction code, characterized by comprising a control means for specifying a different second storage area from the first storage area storing the last of the data.