JP2000105994A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device loaded with a DRAM macro which is capable of setting a data bit width configuration in accordance with the use purpose of the semiconductor device by specification of an external input. SOLUTION: This semiconductor storage device is constituted to make the read/write bit width variable by selecting the read line of a read circuit 21 and a write line of a write circuit 20 by a read line selector 23 and a write line selector 22 in accordance with a read/write bit width set signal. At least partial data buses of plural parallel data busses of an interface circuit 14 are selectively conducted by a byte length set signal by means of an input/output pass selector 24, whereby the number of bytes of the input/output data busses of the interface circuit is controlled to a desired byte length. Further, when access to an defective memory array exists, the access is switched to a redundant array by a redundant line selector 25, which is in an activated state, thereby reducing the delay time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a configuration of a data input / output bus of a dynamic random access memory (hereinafter abbreviated as DRAM), and more particularly to a bus configuration and redundancy effective for a DRAM macro mixed with a logic circuit. It relates to a relief circuit configuration and a layout configuration.

[0002]

2. Description of the Related Art In recent years, as a method of realizing a semiconductor device, a DRAM macro is mounted on one chip by a CPU or an A / D.
Attention has been paid to a method of mounting the logic circuit together with a logic circuit such as an SIC. The advantages of this hybrid system are that a high data transfer rate between semiconductor modules and low power consumption can be realized. DRAM embedded according to the intended use of the chip
The required data bit width configuration varies from 8 to 256 bits. Conventionally, in order to realize various data bit width configurations, a method of redesigning a new DRAM macro according to each, or simply arranging a plurality of identical DRAM macros in parallel to achieve a desired data bit width. And the like.

On the other hand, a redundancy repair circuit is widely used for the purpose of improving the yield of chips on which DRAM macros are mounted. In the wafer inspection process, a defective address is detected, and a redundancy repair address is recorded by means such as laser trimming. In the conventional redundancy repair method, an address that is accessed and activated is compared with this redundancy repair address, and when they match, the redundancy repair circuit is preferentially activated to replace the defective DRAM in place of the defective DRAM. The redundant relief circuit was used.

Further, conventionally, general-purpose DRAMs have been mainly used.
In order to reduce cost and design, the wiring layer is designed using one or two layers of metal. The input / output data line group sent from the inside of the circuit to the external pins is laid out in a parallel straight line on the uppermost layer.

[0005]

In the conventional method of designing a semiconductor device according to the data bit width configuration, it is necessary to redesign the semiconductor device, which requires extra design man-hours and is disadvantageous in terms of cost. There is simply the same DR
In the design method of arranging a plurality of AM macros in parallel, a plurality of sharable circuits must be arranged, which causes a problem of increasing the chip area.

On the other hand, in a conventional semiconductor device design method using a redundancy repair circuit, after comparing addresses, a procedure of activating the redundancy repair circuit at a location where a defect has occurred is taken. There is a problem that the operation speed is limited by the above.

Further, in the case of the embedded DRAM, there are cases where three to five layers of multi-layer wirings are used in the same manner as in the logic circuit portion. Since the bit width is wide, a large number of input / output data lines run on the uppermost layer. As described above, since the uppermost layer wiring is complicated, it is difficult to connect the element arranged in the lower layer and the uppermost layer wiring, and there is a problem that necessary connection between the wirings cannot be secured.

The present invention solves the above-mentioned conventional problems. A data bit width configuration can be set according to the purpose of use of a semiconductor device by designating an external input.
It is an object to provide a semiconductor device equipped with an AM macro. Another object of the present invention is to provide a semiconductor device equipped with a redundancy repair circuit that can speed up access of a redundancy repair circuit unit, which has been a bottleneck in the operation speed of a conventional semiconductor device. It is another object of the present invention to provide a semiconductor device having an arrangement of an input / output data bus effective for reducing the chip size of an embedded DRAM macro having a wide bit width.

[0009]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises: a plurality of memory array blocks each including a memory cell arranged in a matrix;
A plurality of main bit lines connected to the memory array block; a latch circuit connected to the main bit line for latching data on the main bit line; a latch circuit connected to the latch circuit for outputting latch data of the latch circuit In a semiconductor memory device having a read circuit for performing
A read line selection unit that selects a read line of output data of the read circuit and changes a read bit width; and a read line connected to the read line selection unit, which reads data of the read line selected by the read line selection unit. An interface circuit for outputting to a bus is provided, and a read bit width of output data is made variable.

With this configuration, it is possible to output only the data of the selected read line.
The read bit width can be made variable by setting. Next, the read line selecting unit includes a read line switching unit that selectively turns on at least a part of a plurality of parallel read line lines of the read circuit, and a read line that is turned on by selecting the read line switching unit. It is preferable that the number of line lines in the line line group be the read bit width of the output data.

The read line switching section may select a group of read line lines to be turned on in accordance with a read bit width setting signal which is an external input signal, and externally designate a read bit width of output data. preferable.

According to this structure, the read line width setting signal from the outside makes it possible to finely set the continuity of the read line switching unit and set the read bit width according to the purpose of use.

Next, it is preferable that the semiconductor memory device is formed on the same semiconductor substrate as a logic circuit, and the read bit width setting signal is changed according to an operation mode of the logic circuit.

With this configuration, it is possible to dynamically change the read bit width according to the operating mode during operation without fixing the read bit width. Further, in order to achieve the above object, a semiconductor memory device of the present invention includes a read line selecting unit that selects a read line of output data of the read circuit and changes a read bit width,
An interface circuit connected to the read line selection unit for outputting data of the read line selected by the read line selection unit to a data bus; and selecting an output bus for output data of the interface circuit to change a read byte length. An output bus selection unit,
The read byte length of the output data is variable.

With this configuration, only the data of the selected read line connected to the predetermined output bus can be output, and the read byte length can be made variable by setting according to the purpose of use.

Next, the output bus selecting section includes an output bus switching section for selectively conducting at least a part of the plurality of parallel data buses of the interface circuit, and selecting the output bus switching section. It is preferable that the number of bytes of the data bus to be conducted by the data bus is the byte length of the output data.

It is preferable that the output bus switching section selects a data bus to be turned on in accordance with a read byte length setting signal which is an external input signal, and can specify the byte length of read data from outside.

According to this configuration, the continuity of the output bus switching unit can be finely set by an external read byte length setting signal, and the read byte length can be set according to the purpose of use.

Next, it is preferable that the semiconductor memory device is formed on the same semiconductor substrate as a logic circuit, and the read byte length setting signal is changed according to a mode of operation of the logic circuit.

With this configuration, the read byte length can be dynamically changed according to the operating mode during operation without fixing the read byte length. Next, it is preferable that the read byte length setting signal is taken in at a rising edge of a row address strobe cycle start clock.

With this configuration, a signal for setting the read byte length can be taken in the read cycle, and the read byte length can be dynamically set for each read cycle.

In order to achieve the above object, a semiconductor memory device according to the present invention comprises: a read line selecting section for selecting a read line of output data of a read circuit to vary a read bit width; And an interface circuit connected to the read line selection unit and outputting the data of the read line selected by the read line selection unit to a data bus, and selecting a part of the data buses from a plurality of parallel data buses connected to the interface circuit. An output bus selection unit for providing output data by selectively outputting output data from only some of the plurality of parallel data buses.

With this configuration, the data of the selected read line can be written only to the predetermined output bus, and the output bus can be set according to the purpose of use. Next, it is preferable that the output bus selection unit can select an output bus to which output data is applied according to a byte address setting signal which is an external input signal, and can specify an output bus to output output data from outside.

With this configuration, the continuity of the output bus switching unit can be finely set by an external byte address setting signal, and the output bus can be set according to the purpose of use.

Next, it is preferable that the semiconductor memory device is formed on the same semiconductor substrate as a logic circuit, and the byte address signal is changed according to a mode of operation of the logic circuit.

With this configuration, it is possible to dynamically change the output bus according to the operating mode in operation without fixing the output bus to be written. Next, it is preferable that the byte address signal is taken in at a rising edge of a column address strobe cycle start clock.

With this configuration, a signal for setting an output bus can be taken in a read cycle, and an output bus can be dynamically set for each read cycle. Next, in order to achieve the above object, a semiconductor memory device according to the present invention comprises: a read line selecting unit that selects a read line of output data of a read circuit and changes a read bit width; And an interface circuit that outputs data of the read line selected by the read line selection unit to a data bus, and selects an output bus of output data of the interface circuit to make the read byte length variable, An output bus selection unit for providing output data only to the selected part of the data buses, a variable read byte length of the output data, and a data bus selected from a part of the plurality of parallel data buses. , Outputting output data of a predetermined byte length.

With this configuration, the data of the selected read line can be written only to the predetermined output bus, and the read byte length is made variable according to the purpose of use, and is output only to the set output bus. be able to.

Next, it is preferable that a module for short-circuiting a predetermined set of the data buses connected to the interface circuit be provided so that the bit width of the data bus can be adjusted.

With this configuration, the bit width of the data bus can be effectively adjusted. According to another aspect of the present invention, there is provided a semiconductor memory device including a plurality of memory array blocks each including a memory cell arranged in a matrix, and a plurality of main bit lines connected to the memory cell array block. A latch circuit connected to the main bit line for latching data on the main bit line; and a write circuit connected to the latch circuit and writing data to the latch circuit. A write line selection unit for selecting a write line and changing a write bit width,
A write circuit selection activating unit that activates only a write circuit connected to a write line selected by the write line selection unit; and an interface circuit that writes external input data to the activated write circuit. The width is variable.

With this configuration, it is possible to output only the data of the selected write line.
The write bit width can be made variable by setting. Next, the write line selection unit includes a write line switching unit that selectively conducts at least a part of a plurality of parallel write line groups of the write circuit, and a write line that conducts when the write line switching unit is selected. It is preferable that the number of lines in the group be the data write bit width.

It is preferable that the write line switching section selects a write line line group to be turned on according to a write bit width setting signal which is an external input signal, and can specify a data write bit width from outside. .

With this configuration, the continuity of the write line switching unit can be finely set by a write bit width setting signal from the outside, and the write bit width can be set according to the purpose of use.

Next, it is preferable that the semiconductor memory device is formed on the same semiconductor substrate as a logic circuit, and the bit width setting signal can be changed according to an operation mode of the logic circuit.

With this configuration, the write bit width can be dynamically changed according to the operating mode during operation without fixing the write bit width. Next, it is preferable to have a function of electrically disconnecting a bus from which data is not accessed.

With this configuration, it is possible to effectively prevent a signal from being improperly applied to another bus that is not accessed. In order to achieve the above object, a semiconductor memory device of the present invention includes a write line selection unit that selects a write line to the write circuit and changes a write bit width, and a write line selection unit that selects a write line width. An input bus selection unit that selects an input bus to the write circuit to change the write byte length, and only a write circuit connected to the write line selection unit and a write line selected by the input bus selection unit. A write circuit selecting / activating unit for activating, an interface circuit for writing external input data to the activated write circuit is provided, and a data write byte length is variable.

According to this configuration, the data of the selected write line can be written only to the data connected to the predetermined input bus, and the write byte length can be made variable by setting according to the purpose of use.

Next, the input bus selection unit includes an input bus switching unit for selectively conducting at least a part of data buses among a plurality of parallel data buses to the write circuit. It is preferable that the number of bytes of the data bus that is turned on by selection be the byte length of the write data.

It is preferable that the input bus switching section selects a data bus to be turned on in accordance with a write byte length setting signal which is an external input signal, so that the byte length of write data can be designated from outside.

With this configuration, the continuity of the input bus switching unit can be finely set by a write byte length setting signal from the outside, and the write byte length can be set according to the purpose of use.

Next, it is preferable that the semiconductor memory device is formed on the same semiconductor substrate as a logic circuit, and the byte length setting signal is changed according to a mode of operation of the logic circuit.

With this configuration, the write byte length can be dynamically changed according to the operating mode during operation without fixing the write byte length. Next, it is preferable that the byte length setting signal is taken in at a rising edge of a row address strobe cycle start clock.

With this configuration, a signal for setting the write byte length can be taken in the write cycle, and the write byte length can be dynamically set for each write cycle.

According to another aspect of the present invention, there is provided a semiconductor memory device, comprising: a write line selector for selecting a write line to the write circuit to change a write bit width; A write circuit selection activating unit for selecting a part of input buses among a plurality of parallel input buses to the write circuit selected and selectively activating only a predetermined write circuit group; And an interface circuit for writing external input data to the group of write circuits activated by (1), wherein data written only to the selected set of write circuits is written to a memory.

With this configuration, data can be written only to the selected write circuit, and the input bus and write circuit group can be set according to the purpose of use. next,
It is preferable that the write circuit selection activating unit can select a write circuit group to be activated according to a byte address setting signal which is an external input signal, and can specify a write circuit group to write data from outside.

With this configuration, the continuity of the input bus switching unit can be finely set by an external byte address setting signal, and the input bus can be set according to the purpose of use.

Next, it is preferable that the semiconductor memory device is formed on the same semiconductor substrate as a logic circuit, and the byte address signal is changed according to a mode of operation of the logic circuit.

With this configuration, the input bus can be dynamically changed according to the operating mode in operation without fixing the input bus to be read. Next, it is preferable that the byte address signal is taken in at a rising edge of a column address strobe cycle start clock.

With this configuration, a signal for setting an input bus can be taken in a write cycle, and the input bus can be dynamically set for each write cycle. In order to achieve the above object, a semiconductor memory device of the present invention includes a write line selection unit that selects a write line to the write circuit and changes a write bit width, and a write line selection unit that selects a write line width. An input bus selection unit for selecting an input bus to the write circuit and changing a write byte length, and only a part of the write circuit group selected by the write line selection unit and the input bus selection unit. A write circuit selecting and activating unit for selectively activating, and an interface circuit for writing external input data only to the write circuit group activated by the writing circuit selecting and activating unit; a variable data write byte length; Writing data of a predetermined byte length from some of the selected data buses. .

With this configuration, data can be written only from a selected input bus to a predetermined write line, and the write byte length can be made variable according to the purpose of use, and output only to the set input bus. it can.

Next, it is preferable that a module that is connected to the interface circuit and short-circuits a predetermined set of the data buses connected to the interface circuit is provided, and the bit width of the data bus can be adjusted.

With this configuration, the bit width of the data bus can be adjusted effectively. According to another aspect of the present invention, there is provided a semiconductor memory device including a plurality of memory array blocks each including a memory cell arranged in a matrix, and a plurality of main bit lines connected to the memory cell array block. A latch circuit connected to the main bit line and latching data on the main bit line; a plurality of read circuits connected to the latch circuit and having a latch function of outputting latch data of the latch circuit; In a semiconductor memory device including an interface circuit connected to a read circuit and outputting output data of the read circuit to a data bus, a read data latch connected to the read circuit and controlling data through of the read circuit A control unit, wherein the read data latch control unit operates in a page mode. In the address strobe cycle, the data of the read circuit is passed only for a predetermined period, and when the data is read in the page mode, the first data read to the output bus in the first page becomes the second data. The data is output to the output bus until immediately before the second data output in the page is output.

With this configuration, it is possible to realize a high-speed operation using the page mode in the semiconductor memory device of the present invention. According to another aspect of the present invention, there is provided a semiconductor memory device including a plurality of memory array blocks each including a memory cell arranged in a matrix, and a plurality of main bit lines connected to the memory cell array block. A latch circuit connected to the main bit line for latching data of the main bit line; a plurality of redundant memory array blocks each including a redundant memory cell arranged in a matrix; and a plurality of redundant memory cell blocks connected to the redundant memory cell array block. A plurality of redundant main bit lines, a plurality of redundant latch circuits for latching data of the redundant main bit lines,
A semiconductor memory device comprising: a read / write circuit connected to the latch circuit and having a function of reading and writing memory cell data; and a redundant read / write circuit connected to the redundant latch circuit and having a function of reading and writing redundant memory cell data. An activation circuit for simultaneously activating the read / write circuit and the redundant read / write circuit; an interface circuit for inputting / outputting data from outside; and whether the interface circuit is connected to the read / write circuit or to the redundant read / write circuit. . Is provided.

With this configuration, there is no time lag between the activation of the latch circuit and the redundant latch circuit, and the output path of the read data output from these latch circuits is fixed by the switch. Access can be performed at high speed without delay associated with data reading.

Further, it is preferable that the activating section connects a redundant read / write circuit and an interface circuit based on a redundant repair address signal which is an external input signal. With this configuration, it is possible to finely set the continuity of the redundant line selector with respect to the read line to be repaired by the redundant repair address setting signal from the outside,
Redundancy relief can be set according to the purpose of use.

In the semiconductor memory device of the present invention, it is preferable that the interface circuit is designed in several types according to the bit width, and uses the interface circuit corresponding to the bit width.

With this configuration, it is possible to easily design a chip using the semiconductor memory device of the present invention, to shorten the design time, improve the design efficiency, and reduce the design cost.

According to another aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of memory array blocks each including a memory cell arranged in a matrix; and a plurality of memory array blocks connected to the memory cell array block. A semiconductor memory device comprising: a main bit line; a plurality of latch circuits connected to the main bit line to latch data of the main bit line; and an interface circuit connected to the latch circuit. , A plurality of data lines output to each other are bundled and arranged.

With this configuration, the area of the largest unused block is increased as compared with the case where the uppermost layers of the metal wirings on which the data bus wirings are arranged are linearly arranged in parallel. Can be used efficiently, and the chip size can be reduced.

Next, it is preferable that the distance between the bundled data lines is a minimum rule of the wiring distance in a manufacturing process. With this configuration, the data line can be formed according to the minimum rule of the wiring interval according to the manufacturing process, and the chip size can be reduced.

Next, the plurality of data lines to be bundled are
It is preferable to be arranged at substantially equal intervals from the interface block to the chip end. With this configuration,
The delay of the signal flowing on the data line between the modules is equalized, stable processing can be performed, and the arrangement is well-balanced, so that the circuit layout can be made most efficient.

Next, the plurality of data lines to be bundled are
It is preferably the uppermost metal wiring layer. With this configuration, the degree of freedom in layout design with the upper wiring layer of the lower module is increased.

[0063]

(Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic layout showing an example of application of a semiconductor integrated circuit in which a DRAM macro of the present invention and a logic circuit are mixed. In FIG. 1, 1 is a logic circuit, 2
Is a DRAM macro, and 3 is a pad. Logic circuit 1 and D
The RAM macro 2 is connected by a number of signal lines. The logic circuit 1 is connected to the pad 3 and the DRAM macro 2 is connected to the pad 3 by signal lines.

FIG. 2 is a block diagram showing an example of a signal flow between functional blocks in the DRAM macro according to the first embodiment of the present invention. 4 is a 1 megabit memory array (hereinafter, mega is simply abbreviated as "M"), 5 is a row address decoder, 6 is a sense amplifier control circuit, 7 is a main bit line, 8 is a main sense amplifier block, and 9 is a row address. Buffer, 10 is a row address predecoder,
11 is a column address buffer, 12 is a column address decoder, 13 is a control circuit, and 14 is an interface block. The DRAM macro according to the configuration of the first embodiment is
Up to eight 1M-bit memory arrays can be arranged, and the memory capacity can be freely changed from 1M bits to 8M bits in 1M bit units.

CLK is a clock signal, NRAS is a row address strobe signal, NCAS is a column address strobe signal, NWE is a write enable signal.
Indicates a negative (low active) signal. RAD is a row address signal having a maximum bit width of 13, CA
D is a column address signal with a maximum bit width of 4, BAD is a byte address signal with a maximum bit width of 5, BMD is a byte mode setting signal with a bit width of 3, and BUSMODE is a bit width setting signal with a bit width of 2. The transfer of data to and from the mixed logic circuit 1 is performed by a data input / output bus DQ.
The bit width can be changed to 64 bits, 128 bits, and 256 bits, and the bit length to be accessed is 8 × 2 m.
It can be set to the power (m = 0, 1,..., 5).

Row address signal RAD input to DRAM macro 2 is input to row address buffer 9. The column address signal CAD, the byte address signal BAD, and the byte mode setting signal BMD are input to the column address buffer 11. A clock signal CLK, a row address strobe signal NRAS, a column address strobe signal NCAS,
The write enable signal NWE is input to the control circuit 13.

The row address buffer 9 is connected to the row address predecoder 10 via an address bus. The decode signal of the row address predecoder 10 is connected to the main sense amplifier block 8 via the row address decoder circuit 5, the sense amplifier control circuit 6, and the bus A. This row address decoder circuit 5 is connected to a large number of memory cells in the 1-Mbit memory array 4 via word lines.

The 1-Mbit memory array 4 is constructed by a commonly used shared sense amplifier system, and includes two 512K memory arrays 15 and three sense amplifiers disposed at both ends and an intermediate portion thereof. Block 16
Consists of 10 in each sense amplifier block 16
56 sense amplifiers (32 of which are for redundancy relief) are arranged, and 256 memory cells are connected to each sense amplifier via two pairs of bit lines. Each sense amplifier is connected to a main bit line pair MBL, NMBL via a switch element. Main bit line pair is 105
Six pairs are arranged, of which 32 pairs are for redundancy relief. 1
The main bit line pair is a main sense amplifier block 8
Connected to one of the main sense amplifiers. Input / output to / from the main sense amplifier block 8 is performed via the interface block 14. A data input / output bus DQ from the logic circuit 1 is connected to the interface block 14.

The column address decoder 12 receives a bit width setting signal BUSMODE and a signal from the column address buffer 11. The main sense amplifier block 8 and the interface block 14 are controlled by a decode signal of the column address decoder 12. Is done.

Next, the circuit configuration of each block will be described.
FIG. 3 is a block diagram of a data input / output unit of a DRAM macro cell according to the present invention.
3 shows an example of the functional configuration and connection relationship of the interface block 14. 17 is a latch circuit, 18 is a redundant part latch circuit, 19 is a 1/4 selector, 20 is a write circuit, 21 is a read circuit, 22 is a write line selector, 23 is a read line selector, and 24 is an input / output bus select , 25 is a redundant line selector, 26 is a redundant part write circuit, 27 is a redundant part read circuit, and 28 is a data output control circuit. The functions in the dotted lines in the figure are realized by a macro block unit (hereinafter abbreviated as MBU) of 264 unit blocks (256 + redundant relief units). D
I is a write data bus, DO64 is a 64-bit read data bus, DO128 is a 128-bit read data bus, DO256 is a 256-bit read data bus, DQ is a data input / output bus, and YSR (j) (j =
0-7) are read data signals for redundancy repair, YSW
(J) (j = 0 to 7) is a write data signal for redundancy repair.

The latch circuit 17 is connected to up to eight 1M memory arrays 4 by 1024 sets of main bit line pairs MBL and NMBL, and further via a １ ／ selector 19, a write circuit 20 and a read circuit 21. Are connected by a 256-bit bus. The output data of the read circuit 21 is input to a read line selector 23, and is classified into a 64-bit read data bus DO64, a 128-bit read data bus DO128, and a 256-bit read data bus DO256. Connected to. The input / output bus selector 24 is connected to the logic circuit 1 by a data input / output bus DQ of 256 bits. The input of the write line selector 22 is connected to a 256-bit write data bus DI from the input / output bus selector 24.
0 is output on a 256-bit bus.

Next, the configuration of the redundancy repair circuit section in FIG. 3 will be described. The redundant part latch circuit 18 includes a maximum of eight 1s by 32 sets of redundant part main bit line pairs SBL and NSBL.
M memory array 4 and 1/4 selector 19
Are connected to the redundant part writing circuit 26 and the redundant part reading circuit 27 via an 8-bit bus. The redundant part write circuit 26 and the redundant part read circuit 27 are connected to the redundant line selector 25. The input / output of data to / from the redundant line selector 25 is performed by reading the 8-bit redundant rescue read data YSRn (j) (n = 0 to 1,
j = 0 to 3) and the redundancy rescue write data signal YSWn (j) from the write line selector 22 (n = 0 to 3).
1, j = 0-3).

FIG. 4 shows an example of a detailed circuit diagram of the unit block MBU of the main sense amplifier block 8. 1
Reference numerals 7a and 18a denote unit blocks of the latch circuit 17 and the redundancy latch circuit 18, respectively. Reference numeral 19a denotes a Y gate circuit which performs a basic function of the 1/4 selector 19;
6a is a unit block of the write circuit 20 and the redundant unit write circuit 26, respectively, and 21a and 27a are unit blocks of the read circuit 21 and the redundant unit read circuit 27, respectively.

WD is a write signal, and RD is a read signal. Four sets of main bit line pairs MBL and NMBL are connected to one unit block MBU. Latch circuit 1
7. Unit blocks 17a and 18 of the redundancy latch circuit 18
Reference numeral a denotes a main bit line precharge circuit having a general precharge circuit configuration and a main sense amplifier circuit having a general cross-type amplifier configuration.

The main bit line precharge circuit includes an N-channel MOS transistor QM1 for equalizing and controlling the voltage of the pair of main bit lines MBL and NMBL to which the precharge signal MEQ is connected at the gate, and also the precharge signal MEQ connected to the gate. Bit lines MBL and N
The voltage of MBL is applied to main bit line precharge potential V
It is composed of three N-channel MOS transistors, N-channel MOS transistors QM2 and QM3 that precharge-control the MBP. This is one for each main bit line pair.
Are placed.

The main sense amplifier circuit has P-channel MOS transistors QM4 and QM5 whose sources are connected to the drain of P-channel MOS transistor QM8, and N-channel MOS transistors QM6 and QM6 whose sources are connected to the drain of N-channel MOS transistor QM9. Q
This is a generally used cross-type amplifier composed of M7. The gate of the P-channel MOS transistor QM8 is connected to the main amplifier start signal MSAP, the source is connected to the power supply VDD, and the gate of the N-channel MOS transistor QM9 is connected to the main amplifier start signal MSA.
At N, the source is grounded. One main sense amplifier circuit is arranged for each main bit line pair, and one data is latched in this amplifier.

The Y gate circuit 19a is composed of four gate circuits. The configuration of the gate circuit includes an N-channel MOS transistor QM10 having a gate connected to Y-gate control signal YPA and a P-channel MOS transistor having a gate connected to Y-gate control signal NYPA between main bit line MBL and data line MBS. C consisting of QM12
MOS gate, main bit line NMBL and data line N
During MBS, the gate sets the Y gate control signal YPA (i).
, And a P-channel MOS transistor QM13 whose gate is connected to a Y-gate control signal NYPA (i).
It is composed of two sets of S-gate CMOS gates. Four gate circuits are arranged between the four pairs of main bit lines MBL, NMBL and the pair of data lines MBS, NMBS. The four gate circuits are Y gate control signals YPA
(I), controlled by NYPA (i) (i = 0 to 3). This Y gate circuit 19a outputs a signal YP
According to A (i), the connection between one of the four main bit line pairs and the data lines MBS and NMBS can be controlled. The 1/4 selector 19 includes the Y gate circuit 19
a are arranged, and data of 1056 pairs of main bit lines is selected as 264.

Write circuit 20, redundant part write circuit 2
The six unit blocks 20a and 26a are composed of write buffers. The write buffer has a tri-state inverter TM1 whose input is connected to the write data signal WD and an output connected to the data line MBS, and an input whose input is the inverter IM1.
To the write data signal WD via the data line N
It comprises a tri-state inverter TM2 connected to the MBS. The control inputs of the tristate inverters TM1 and TM2 are both connected to the write control signal WEN.

Read circuit 21, redundant part read circuit 2
The seven unit blocks 21a and 27a include a data line equalizing circuit and a read data latch circuit. The data line equalizing circuit outputs a data line equalizing signal NE.
Data line pair MBS and NM with QBUS connected to the gate
An N-channel MOS transistor QM14 for equalizing and controlling the voltage of BS is provided.

Read data latch circuit has a tri-state inverter TM whose input is connected to data line NMBS.
4, the input is connected to the output of the inverter IM2, the input is connected to the output of the inverter IM2, and the output is connected to the input of the inverter IM2. It is composed of tri-state inverters TM3 connected in a zigzag manner. The control inputs of these tristate inverters TM3 and TM4 are both connected to data latch signal DLCH.

FIG. 5 shows a detailed circuit diagram example of the unit block 23a of the read line selector 23 in the main sense amplifier block 8. The main sense amplifier block 8 includes 64 blocks. The n-th unit block 23a (n) has four unit blocks MBU.
(4n-4n + 3) (n = 0, 1,..., 63). By the read line selector 23, 25
The output data of the six unit blocks MBU is branched.

SW1 to SW7 are data selectors which are read line switching units, and YSR0, 1 (j) (j =
0-3) are read data signals for redundancy repair, YSI (4
n to 4n + 3) are select signals for redundancy repair, PA2, 3
Is a column address decode signal.

The data selectors SW1 to SW7 are circuits that output the values of the inputs A and B to the Y output according to the L and H of the input S. The data inputs A of the data selectors SW1 to SW4 have four unit blocks MBU (4n to 4n +
The read data signal RD of 3) is the data selector S
Redundant rescue unit block read data YSR1 (j) is input to data inputs B of W2 and SW4, and redundant rescue unit block read data YSR0 (j) is input to data inputs B of SW1 and SW3. The input S includes redundant select signals YSI (4n) to YSI.
SI (4n + 3) is connected. Data selector SW
5 are provided with data selectors SW1, S
The Y output of W2 has a column address decode signal P
A2 is connected. The outputs of the data selectors SW3 and SW4 are connected to the data inputs A and B of the data selector SW6, and the column address decode signal PA2 is connected to the input S. The data inputs A and B of the data selector SW7 are connected to the outputs of the data selectors SW5 and SW6, and the input S is connected to the column address decode signal PA3. Outputs Y of the data selectors SW1 to SW7 are read data buses DO256 (n + 192) and DO256 (n
+64), DO256 (n + 128), DO256
(N) 128-bit wide read data bus DO128
(N + 64), DO128 (n), and 64-bit read data bus DO64 (n).

With the configuration of the unit block 23a, four unit blocks MBU (4n to 4n + 3) to be connected are connected.
Read data signal RD and two redundant repair unit block read data YSRn (j) are supplied to the switch SW1.
7 and output to the read data buses DO64 to 256 of each bit width.

FIG. 6 is a detailed circuit diagram of the unit block 22a of the write line selector 22 in the main sense amplifier block 8. Sixty-four of these blocks are arranged in the line selector 22. One block n is connected to four unit blocks MBU (4n to 4n + 3).

TW1 to TW11 are connected to the control signal H
Alternatively, the tri-state inverter is a write line switching unit that outputs a signal in a high impedance state or a phase opposite to the input signal according to L. W
Ei (0-3) (i = 0-7) is a write control signal, B
US0-4 are bit width control signals, YSW0-1 (j)
(J = 0-3) is a write data signal for redundancy relief.

The four unit blocks MBU (4n to 4n + 3) connected to this unit block (n = 0, 1,...)
., 63) write data signal WD (4n to 4n +
In 3), one write data bus DI (n) is input to the lowest stage through the inverter IW1 and the other three stages via the tri-state inverters TW1 to TW1 to TW3. The control inputs of the tri-state inverters TW1 to TW3 have negative polarities, and the bit width control signals BUS1 and BUS
0 and BUS0.

Further, unit block MBU (4n + 2),
The write data signal WD (4n + 3) of the MBU (4n + 3)
2), one write data bus DI (n + 64) is input to WD (4n + 3) via tri-state inverters TW5 and TW6. The control inputs of these tri-state inverters TW5 and TW6 have a negative polarity and are connected to bit width control signals BUS3 and BUS2. Further, one write data bus DI (n + 1) is supplied to the write data signal WD (4n + 1) of the unit block MBU (4n + 1) via the tristate inverter TW4.
28) is input. This tri-state inverter T
The control input of W4 is negative, and the bit width control signal BUS4
Connected to. Similarly, unit block MBU (4n + 3)
A write data bus DI (n + 192) is input to the write data signal WD (4n + 3) via the tri-state inverter TW7, and the control input is negative and is connected to the bit width control signal BUS4. As described above, each write data signal bus DI is branched by the write line selector 22 under the control of the bit width control signal BUS, and is input to the write data signal WD of a predetermined unit block MBU.

The write data signal WD (4n),
(4n + 2) are the tri-state inverters TW8, TW8
The write data signal YSW0 for redundancy repair is provided via W10.
(J). This tri-state inverter T
The W8 and TW10 control inputs are connected to the redundancy repair select signals YSI (4n) and YSI (4n + 2), respectively. Similarly, the write data signals WD (4n + 1), (4
n + 3) are the tri-state inverters TW9, TW1
1 through the redundant write data signal YSW1
(J) and output to the tri-state inverter TW9,
The control inputs of the TW11 are connected to the redundancy repair select signals YSI (4n + 1) and YSI (4n + 3), respectively. As described above, each write data signal WD (4n to 4n +
3) is a redundant repair select signal YSI (4n to 4n +
By the control of 3), the write data signal YS for redundancy repair
W0, 1 (j).

Each unit block MBU (4n to 4n + 3)
Are connected to the write control signals WEi (0-3) (i = 0-7).

FIG. 7 is a detailed circuit diagram of the unit block 25a of the redundant line selector 25 in the main sense amplifier block 8. The redundant line selector 25 has four (j
= 0 to 3) are arranged.
One unit block is composed of two redundant unit block MBUs.
(2j) and (2j + 1). The circuit configuration of the redundant unit block MBU is the same as that of the unit block MBU except that the connected main bit line pair is a redundant main bit line pair SBL, NSBL.

YSEPENj is an even-numbered part redundant enable signal, and YSOPENj is an odd-numbered part redundant enable signal.
SEPBj (0-3) is an even-numbered part redundant repair address decode signal, and YSOPBj (0-3) is an odd-numbered part redundant repair address decode signal. In this circuit, the redundant unit block MBU (2j) is a redundant repair circuit for the even-numbered part of the unit block MBU, and the redundant unit block MBU (2j + 1) is a redundant repair circuit for the odd-numbered part.

Unit block MBU (2j) for repairing even part
Read data signal RD (2j) and the even-number part redundancy enable signal YSEPENj are input to the AND element,
The output of the D element is a readout data signal YSR0 for redundancy repair.
(J). Write data signal WD (2j)
, A NAND logic signal of the redundancy rescue write data signal YSW0 (j) and the even-number portion redundancy enable signal YSEPENj is input. Similarly, the odd-numbered unit block MB
The U read data signal RD (2j + 1) and the odd-number portion redundancy enable signal YSOPENj are input to the AND element, and the output of the AND element is connected to the redundancy repair read data signal YSR1 (j). Write data signal WD
(2j + 1) includes a redundancy repair write data signal YS.
W1 (j) and odd part redundancy enable signal YSOPENj
Is input.

The write control signals WEN (2j) of the redundancy repair circuit of the even part include write control signals WEi (0),
WEi (2), WEi + 1 (0), WEi + 1 (2) and even part redundancy repair address decode signal YSEPBj
The (0, 1, 2, 3) decode signal is input. Similarly, the write control signal WEN (2
j + 1) include write control signals WEi (1), WEi
(3), WEi + 1 (1), WEi + 1 (3) and the odd part redundant repair address decode signal YSOPBj (0,1,.
2, 3) decoded signals are input.

FIG. 8 is a schematic diagram showing the arrangement and connection of the write line selector 22, the read line selector 23, and the redundant line selector 25 in the main sense amplifier block 8.

Unit block 25 of redundant line selector 25
a (j = 0) is the write data signal YSW for redundancy repair
0 (0), YSW1 (0) and the redundant relief read data signals YSR0 (0), YSR1 (0) via the four unit blocks 22a, 23a (0) of the write line selector 22 and the read line selector 23. To 15). That is, the unit block 25a (j) functions as a redundancy repair circuit for n = 0 to 63 of the unit block MBU (n). Similarly, the unit blocks 25a (j = 1, 2, 3) of the redundant line selector 25 are the unit blocks 22 of the write line selector 22 and the read line selector 23.
a, 23a (16-31), (32-47), (48-
63) connected to the unit block MBU (64 to 12).
7), (128 to 191), and (192 to 255) function as a redundancy repair circuit.

In order to control the circuit block to be repaired, the redundancy repair select signal YSI (0 to 25) is used.
5) corresponds to the write block selector 22 and the read line selector 2 corresponding to n = 0 to 255 of the unit block MBU.
3 is connected.

FIG. 9 shows an example of a detailed circuit diagram of each unit block of the interface block 14. Numeral 24a is a unit block of the input / output bus selector 24 and 64 are arranged in the interface block 14 (n = 0 to 6
3) and 28a are arranged in eight unit blocks of the data output control circuit 28 (i = 0 to 7). Unit block 2
In 4a, O0i to O6i are macro data output control signals, and NW (0 to 3) are write data through signals. In the unit block 24a (n), macro data input / output signals DQ (n), DQ (n + 64), DQ (n + 1)
28), and DQ (n + 192) are connected. Tri-state inverter T as input / output bus switching unit
Of the I1 to TI7, the tri-state inverter TI
1, the output terminals of TI2 and TI3 are both DQ (n) of the macro data input / output signal, and the input terminals are DO256 (n) and DO128 (n) of the read data bus, respectively.
The control input to DO64 (n) is connected to macro data output control signals O0i, O1i, O3i, respectively. The output terminals of tristate inverters TI4 and TI5 are both connected to macro data input / output signal DQ (n + 64), and the input terminals are DO25 of the read data bus, respectively.
6 (n + 64), connected to DO128 (n + 64),
The control input terminals are respectively macro data output control signals O4
i, O5i. Tri-state inverter T
The output terminal of I6 is connected to the macro data input / output signal DQ (n
+128), the input terminal is connected to the read data bus DO256 (n + 128), and the control input terminal is connected to the macro data output control signal O2i. The output terminal of the tristate inverter TI7 is connected to the macro data input / output signal DQ (n + 192), the input terminal is connected to the read data bus DO256 (n + 192),
The control input terminal is connected to the macro data output control signal O6i. Macro data input / output signals DQ (n), DQ
(N + 64), DQ (n + 128), DQ (n + 19
2) are the write data buses DI (n) and DI (n +
64), DI (n + 128), DI (n + 192),
D-type flip with general load and hold function
Read data latch control unit (DQLH) which is a flop
CL), a clock signal CLK is input to the read data latch control unit, and a write data through signal NW (0 to 3) is input to the load / hold control terminal.

In the unit block 28a, OECF is a data output enable flag, OEi (0-3) is a data output enable signal, and PBA (i) is a byte address decode signal. The unit block 28a is formed of a standard logic circuit, and has input terminals of a data output enable flag OECF and a data output enable signal OEi (0 to 0).
3) A decoder circuit which outputs the byte address decode signal PBA (i) and outputs macro data output control signals O0i to O6i.

FIG. 10 is a detailed circuit diagram of the column address decoder 12. CADEC is a write / read signal decode circuit, BUD is a BUS signal decode circuit,
MBC is a read / write control circuit, and YGD is a Y gate control signal decode circuit. SW8 and SW9 are L and H of the input S.
A switch that outputs the values of inputs A and B to the Y output according to
YDEN is a Y decoder enable signal input from the control circuit 13, WECF is a write enable control signal also input from the control circuit 13, and CAD0 to CAD3 are column address signals input from the column address buffer 11.

Write / read signal decode circuit CA
DEC is a standard logic circuit and switches SW8 and SW9.
, Byte address signals BAD0 to BAD4 input from a column address buffer, and a byte mode setting signal BM
D0 to D3, a bit width setting signal BUSMODE0 to 1, a data output enable flag OECF, a write enable pre-signal WEP, and a column address signal CAD2 to CAD3, and a write control signal WEi (0 to 3) and a data output enable signal OEi ( 0-3), byte address decode signal PBA (i), column address decode signal PA2
And a decoding circuit for outputting PA3. Due to space limitations, the write control signal WEi (0-3) and the data output enable signal OEi (0-3) indicate only i = 0, 1, 7; It is configured with.

The BUS signal decoding circuit BUD is formed of a standard logic circuit, and has a bit width setting signal BUSMODE.
This is a circuit which receives 0 to 1 as inputs and outputs bit width control signals BUS0 to BUS4.

The read / write control circuit MBC comprises a standard logic circuit and a delay element DL. The read / write control circuit MBC receives a Y decoder enable signal YDEN and a write enable control signal WECF as inputs, and receives a write enable pre signal WEP, a data latch signal DLCH, and a data line equalize. Signal NEQBU
S is an output circuit. The Y-gate control signal decode circuit YGD is formed of a standard logic circuit, and receives as input the column address signals CAD0 to CAD1 and a signal generated by the read / write control circuit MBC, and performs Y-gate control. The signal YPA (0
3), a circuit that outputs NYPA (0-3).

FIG. 11 shows eight sets of write control signals WEi (0-3) (i) decoded by the column address decoder 12.
= 0 to 7) and an example of a connection relationship between the write line selector 22. WE0 (0-3) are connected to the unit blocks 22a (0-7) of the write line selector 22, and similarly, the unit blocks 22a (8-15),.
..22a (56 to 63) is WE1 (0 to 3),
., WE7 (0 to 3).

WE0 (0-3) and WE1 (0-3) are connected to the redundant line selector unit block 25a (0), and similarly, each of the redundant line selector unit blocks 25a.
(1), (2), and (3) indicate the write control signals WE2 and WE3.
(0-3), WE4, 5 (0-3), WE6, 7 (0
3) are connected to control the write operation of the redundancy repair section.

As described above, the write control signals WEi (0 to WEi)
3) is a unit block 22 of eight write line selectors
a for each byte, enabling output in byte units. FIG. 12 shows eight sets of data output enable signals OEi (0 to 3) (i
= 0 to 7) and the unit blocks 28a (i) (i = 0) of the data output control circuit 28 in the interface block 14.
7) and the unit block 24a of the input / output bus selector 24
It is the schematic diagram which showed the example of the connection relationship of (n) (n = 0-63).

Eight sets of data output enable signals OEi
(0-3) are input to each unit block 28a (i = 0-7). The macro data output control signals O0i to O6i (i = 0) of each unit block 28a (i = 0 to 7)
The unit blocks 24a (n) (n = 0 to 7) are controlled. According to the same rule, each unit block 28a (i = 1 to
7) input data output enable signal OEi (0
3), i = 1 to 7, the unit block 24a (n)
Are controlled from n = 8 to 15 to n = 56 to 63.

As described above, one data output control circuit 28
Are divided into eight input / output bus selectors 24 by macro data output control signals O0i to O6i.
And the unit block 24a (n) is controlled to enable output in byte units.

The DRA of the present embodiment configured as described above
The operation of the M macro will be described below. First, a method of setting the bit width mode of the present DRAM macro will be described. FIG. 13 shows a DRAM macro according to this configuration.
Bit width to be set and bit width setting signal BUSMODE
5 is a table showing an example of the relationship between bit width control signals BUS0 to BUS4. As shown in FIG. 13, the bit width setting signal BUS
The width can be selectively set to 64, 128, or 256 bits by setting the potential of MODE. The setting of the bit width mode can be set in advance according to the specification of the LSI to be mixed, or can be set in advance according to the operation mode. The bit width setting signal BUSMODE is output from the BUS signal decoding circuit BUD in FIG.
Decoded to US0-4.

Next, a method of setting the bit length to be accessed will be described. The DRAM macro of this configuration has a function of performing a read or write operation only on a predetermined bit of the set bit width.

FIG. 14 is a table showing an example of the relationship between the set bit length and the byte mode setting signal BMD. The bit length of access to the DRAM macro is set to 8 × 2 m (m = 0, 1,...) By setting the byte mode setting signal BMD.
Can be set to

The data input / output bus DQ to be accessed can be arbitrarily selected by the byte address signal BAD. FIG. 15 shows an example in which the input byte address signal BAD is set to a 128-bit width.
5 is a table showing an example of the relationship between the selected data input / output bus DQ. For example, the byte mode setting signal BMD (0 to 0)
When 2) is set to (H, L, L) and set to 16 bits, the byte address signals BAD (0 to 4) are set to (L, L).
H, L, L, x) (x is arbitrary),
Only n = 16 to 31 are selected for the data input / output bus DQ (n), and data can be input / output using only these 16 bits.

As described above, the bus for transferring data in units of 8 × 2 m (m = 0, 1,...) Bit lengths can be selected by the byte address signal BAD. Next, a method for setting the redundancy relief will be described. DR of this configuration
The redundancy repair of the column system of the AM macro is performed for each unit block MBU in the main sense amplifier block 8. When a certain unit block MBU (k) does not operate normally due to some problem in the manufacturing process, and it is necessary to perform redundancy repair, in a wafer inspection process, a redundancy repair address is set by means such as laser trimming using a general fuse circuit. I do. When power is turned on based on this setting,
The redundancy repair select signal YSI (k) corresponding to the defective unit block MBU (k) is set to the H level.

The path of data transmission to the redundancy repair circuit will be described. FIG. 16 shows the write line selector 22.
And read line selector 23 and redundant line selector 2
5 is a schematic diagram showing an example of a connection state of No. 5; When the redundancy repair select signal YSI (k) is set to the H level as described above, the tri-state inverter in the write line selector 22 in FIG. The switches SW1 to SW4 in the read line selector 23 change the connection path, and the unit block MB
The write data bus DI and the read data bus DO connected to U (k) are connected to the redundant line selector 25 via the redundant repair write data signal YSW and the redundant repair read data signal YSR instead.

When the unit block MBU (k) in the main amplifier block 8 to be redundantly repaired is an even-numbered part, a predetermined even-numbered part redundant enable signal YSEPENj of the unit block of the connected redundant line selector 25 and the redundant relief are provided. A predetermined one of the even-numbered part redundant repair address decode signals YSEPBj (0 to 3) indicating the address of the unit block MBU to be executed is at the H level. A predetermined one of the signals YSOPBj (0 to 3) is set to H level, the redundant line selector 25 switches, and the write data bus DI and the read data bus DO data are input to the unit block MBU.

As described above, the DRA having the configuration of the present embodiment
The M macro determines the setting of the redundancy selection when the power is turned on, and is connected by the tri-state inverter in the write line selector 22 controlled by the redundancy repair select signal YSI and the switches SW1 to SW4 in the read line selector 23. This is a configuration example in which a route is changed. During operation, the redundancy relief circuit is also activated at the same time as the normal circuit without comparing the address where the redundancy relief is performed with the address where the read / write is performed, and the data is output only through the switch, so that The operation can be performed at a higher speed than a conventional method of activating a circuit after selecting an address.

Next, the operation of the DRAM macro of this embodiment will be described with reference to the timing charts of FIGS. The write and read operations of this memory are composed of a row address operation RAS, a column address operation CAS, and a precharge operation PRE.

First, the write operation will be described. In the row address operation RAS, a clock signal CLK is input to the DRAM macro 2, a row address is input to the row address signal RAD, a predetermined byte mode is input to the byte mode setting signal BMD, and the row address is set to a rising edge of the clock.
This operation is started by setting the column address strobe signal NRAS to L level.

In response, precharge signal MEQ is set to L level, and the main bit line precharge circuits of unit blocks 17a and 18a are stopped. Thereafter, the word line is set to the H level from the row address decoder 5, and an ON signal of the memory cell Tr gate of 1056 memory cells (32 of which are for redundancy repair) in the connected memory array 15 is output and sensed. A sense amplifier activation signal is output from the amplifier control circuit 6, and 1056 data are latched by the sense amplifier in the sense amplifier block 16.

Thereafter, when the transfer gate control signal goes high, the latched data is transmitted to 1056 pairs of main bit lines MBL and NMBL. After transmission
The main amplifier activation signal MSAN goes low and the main amplifier activation signal MSAP goes high, activating the main sense amplifier circuit and latching data. On the other hand, the byte mode setting signal BMD input to the DRAM macro is held in the column address buffer 11 and output to the column address decoder 12. With this operation, data of the selected 1056 memory cells is latched in the main amplifier block 8. The above is the row address operation RAS of the present DRAM macro.

Next, the column address operation CAS will be described. Following the row address operation RAS, the write enable signal NWE is set to L level, and the column address signal CAD is set.
, A byte address is input to the byte address signal BAD, write data is input to the data input / output bus DQ, and the column address strobe signal NCAS is set to L level by the rising edge of the clock. Enter this operation.

The input column address signal CAD and byte address signal BAD are held in the column address buffer 11 and output to the column address decoder 12. When the write enable signal NWE input to the DRAM macro is set to L level, the write enable control signal WECF
Are set to the H level. In response, the unit block 2 of the input / output bus selector 24 in the interface block 14
4a, a predetermined one of the write data through signals NW (0-3) is set to L level, and the data input / output bus D
Write data input to Q is set in the D-type flip-flop. FIG. 19 shows an example of the relationship between the write data through signal NW (x) at L level and the set bit width of the DRAM macro. Each of the four write data through signals NW (x) is connected to 64 D-type flip-flops,
In the case of an 8-bit width setting, of NW (x), x = 1,
3 is set to H level, and 128 data are
Latched on the flop. A data input / output bus DQ having a load / hold function and not performing D-type flip-flop input / output (DQ in the case of a 128-bit width is set.
(128 to 255)) can be floating.

The data on the data input / output bus DQ corresponding to each bit width is thereafter supplied with the data write signal DI (0 to 0) of the write line selector 22 in the main sense amplifier block 8 in synchronization with the rise of the clock signal CLK.
255).

The input data write signal DI is supplied to the bit line control signal BUS0 in the write line selector 22.
4, the data is branched by the tri-state buffer group and input to the write data signal WD of the unit block MBU. For example, when the width is set to 128 bits, it is input to the write data signal WD of the predetermined 128 unit blocks MBU and is input to the write buffer of the write circuit 20a in the unit block MBU.

Unit block MBU to which data is input
When (k) is targeted for redundancy repair, the tri-state inverter in the write line selector 22 connected to the redundancy repair select signal YSI (k) is turned on when the power is turned on, and the arrow in FIG. As shown in the path, the data write signal DI (x) to the unit block MBU (k) is output as a predetermined redundancy rescue write data signal YSW, and the predetermined redundancy rescue in the redundant line selector 25 is performed. Data signal WD of unit block MBU
And input to the write buffer of the redundant unit writing circuit 26a in the redundant unit block MBU.

When the Y decoder enable signal YDEN input to the read / write control circuit MBC is changed to H level in response to the start clock of the column address operation CAS, the read / write control circuit MBC and the Y gate control signal decode circuit Y
By GD, a data line equalizing signal NEQBUS and
Y gate control signals YPA (0-3), NYPA (0-3)
And the write enable pre-signal WEP are respectively at L level, H level,
L level and H level are set.

As a result, the data line equalizing circuit BE in the unit block MBU is stopped, the 1/4 selector 19 is activated, and 1056 main bit line pairs MB
L and NMBL are selected as 1/4 of 264 pairs and connected to the write buffer. Thereafter, the predetermined write control signals WEi (0 to 3) are set to the H level, and the write buffer is activated. Data is written to the memory cells by activating the write buffer. As an example, FIG. 21 shows the relationship between the write control signals WEi (0 to 3) and the byte address signal BAD in the case of a 128-bit width. For example, 1
In the case of a 6-bit length, for each combination of byte address signals BAD,
Two of the write control signals WEi (n) become H level. As shown in FIG. 11, each of the write control signals WEi (0 to 3) is connected to eight write buffers and one redundant rescue block, and 16 write buffers (redundant relieved). 17 in this case) are activated.

With the configuration for controlling the activation of the write amplifier for each of the eight amplifiers, 8 × 2 m (m = 0, 1,...)
Writing in bit units becomes possible. The redundant line selector 25 uses the write control signal WEi and the even part redundant repair address decode signal YSEPBj or the odd part redundant repair address decode signal YSOPBj to connect the redundant part write circuit 2 in the redundant part unit block MBU to be connected.
7 are activated. Data is written to the memory cells of the redundant portion based on the data input to the write data signal WD of the unit block for redundancy repair MBU via the write data signal for redundancy repair YSW.

As described above, the unit block MBU (n) and the redundant unit block are simultaneously activated, and the path of the input / output data is determined by a switch fixed when the power is turned on. The delay associated with activation after address comparison can be eliminated.

Thereafter, Y decoder enable signal YD
EN goes low after a predetermined period, the write control signals WEi (0-3) go low, the write buffer stops, and the Y gate control signals YPA (0-3), NYPA
(0-3) are at L level and the data line equalize signal NE
QBUS is set to H, the data line equalizing circuit BE is activated, and prepares for the next operation.

Next, the precharge operation PRE will be described. By the rising edge of the clock, the row address strobe signal NRAS and the column address strobe signal N
This operation is entered by setting CAS to the H level.

In response to the start of the precharge operation PRE,
The row address decoder 5 outputs an off signal of the memory cell Tr gate in the memory array 15, and subsequently outputs a sense amplifier stop signal from the sense amplifier control circuit 6. Thereafter, the main amplifier start signal MSAN is set to L level, the main amplifier start signal MSAP is set to H level, and the main sense amplifier circuit stops. Thereafter, the precharge signal MEQ is set to the H level, the main bit line precharge circuit is activated, and the main bit line is charged to the main bit line precharge potential VMBP.

Next, the reading operation will be described. The row address operation RAS is the same as in the case of the write operation, and a description thereof will be omitted.

The method of entering the column address operation CAS is the same as that of the write operation except that the write enable signal NWE is set to the H level. In response to the start of the address operation CAS, the Y decoder enable signal YDEN becomes H level.
And a pair of the read / write control circuit MBC and the Y gate control signal decode circuit YGD are set to L level, H level, and L level, respectively. As a result, the result BE of the data line equalizing circuit in the unit block MBU is stopped, the 1/4 selector 19 is activated, and the column address CA
1/4 determined by S0 to 1 (256 + redundant portions = 26)
(4) main bit line pairs and 26 in the read circuit 21.
Four read data latch circuits are connected, and data on the main bit line NMBL is input to the read data latch circuit.

Thereafter, Y gate control signal decode circuit Y
Due to the GD, the data latch signal DLCH is set to L level, and the data of the main bit line NMBL input to each read data latch circuit is passed through. The passed data is output as a read data signal RD (n) of the unit block MBU (n). Redundant unit block MBU
Similarly, when the data of (j) is passed through and the redundancy relief is performed, YSEPENj or YSOPENj is at the H level when the power is turned on, and the connected redundant relief read data signals YSR0 to 1 (j) Data is output.

The read data signal RD of the main sense amplifier unit block MBU and the redundancy repair read data signals YSR0 to 1 (j) are selected by the switches SW1 to SW4 of the unit blocks of the read line selector 23. The outputs of the switches SW1 to SW4 are DO256 (n + 192) and DO256 by switches SW5 to SW7 based on the column address decode signals PA2 and PA3 output from the write / read signal decode circuit CADEC based on the column address signals CAD2 and CAD3. (N + 6
4), DO256 (n + 128), DO256 (n),
DO128 (n + 64), DO128 (n), DO64
Data is output to (n).

Thereafter, data output enable flag OE
CF is set to H level. In response, the write / read signal decode circuit CADEC sets the predetermined read control signals OEi (0-3) to the H level based on the byte mode setting signal BMD, the byte address signal BAD, and the bit width setting signal BUSMODE. You. A read control signal OEi (0 to 3) for each bit width;
The relationship between the byte address signal BAD and the write control signal WEi (0 to 3) is similar to that of the write control signal WEi and will not be described. For example, in the case of a 16-bit length, two predetermined write control signals OEi (0 to 3) become H level for each combination of byte address signals BAD.

In response, macro data output control signal O of unit block 24a (i) in data output control circuit 24 is received.
Of Oi to O6i, O3i in a 64-bit width configuration from the decoding configuration, O1i and O5 in a 128-bit width configuration.
i, O0i, O2i, O4i,
O6i becomes H level.

This macro data output control signals O0i-0
6i, the tri-state inverter T in the unit block 14a (n) of the input / output bus selector 14
When a predetermined one of I1 to I7 is turned on, the read data bus D
The data of O is output to the data input / output bus DQ. Since each of the macro data output control signals O0i to 06i is connected to eight interface block unit blocks IF as shown in FIG. 12, for example, in the case of a 16-bit configuration, the write control signals OEi (0 to 3) 2) Two predetermined data output control signals O0i to 06i are set to H level, and the data is output to 16 data input / output buses DQ. This makes it possible to read data in units of bytes in an 8 × 2 m (m = 0, 1,...) Bit configuration.

The Y decoder enable signal YDEN goes low after a predetermined period, and data is latched.
Read data is held in each read data latch circuit. In the page mode (when the CAS cycle is continuously performed), the held data is held until the next DLCH is set to the L level. During that time, the read data is always output. In the page mode, the period is at most the same as the clock period, so that the control of the acquisition of the read data becomes easy. From the interface circuit, the data is Y gate control signals YPA (0-3), NYPA (0-3) is at L level,
The data line equalize signal NEQBUS is set to H, and the data line equalize circuit BE is activated to prepare for the next operation.

The description of the precharge operation PRE is the same as that of the write operation, except that OECF is set to the L level at the start of the operation. In response, the output of the read data is stopped.

As described above, according to the present embodiment, the bit width setting signal BUSMODE of the external input corresponds to the application.
Can change the bit configuration to 64, 128, 256 bits. Further, DR is set by the byte mode setting signal BMD.
The bit length of access to the AM macro is set to 8 × 2 m, and the input / output bus DQ to be accessed can be selected by the byte address BAD.

In the above description, the bit width is set as follows:
The bit width of the data bus can be adjusted by providing a module for short-circuiting a predetermined set of the data buses connected to the interface circuit by the bit width setting signal BUSMODE.

In the above embodiment, the bit width setting signal can be set by connecting each signal line for supplying the bit width setting signal to either the power supply or the ground for each LSI manufacturing mask. Further, the connection of each signal line for supplying the bit width setting signal can be set by trimming the fuse element, and the bit width setting signal can be set. Further, each signal line for supplying the bit width setting signal is connected to the pad, and the bit width setting signal can be set by the external pin of the semiconductor chip, so that the user can flexibly customize.

Similarly, in the above embodiment, L
The byte length setting signal can be set by connecting each signal line for providing the byte length setting signal to either the power supply or the ground for each SI manufacturing mask. Further, the connection of each signal line for supplying the byte length setting signal can be set by trimming the fuse element, and the byte length setting signal can be set. Also, each signal line for providing a byte length setting signal can be connected to a pad, and the byte length setting signal can be set by an external pin of the semiconductor chip, so that the user can flexibly customize.

Further, according to the setting of the redundancy repair address according to the configuration of the present embodiment, the path of the input / output data is changed to the switch when the power is turned on, and the read / write of the redundant portion is performed.
By activating the write circuit at the same time as activating the normal read / write circuit, the delay associated with activating the circuit after performing the conventional redundant address comparison can be eliminated, and the operation can be performed at high speed. .

(Embodiment 2) The circuit shown in FIG.
9 shows another embodiment of the unit block 24a (n) of the input / output bus selector 24 in the interface block 14 in the RAM macro 2, and another embodiment of the data output control circuit 28a (i). In this example, the input / output bit width is 128
This shows the optimal configuration of the unit block when the bit is set. A 128-bit read data bus DO128 (n), DO (n + 6) required for a 128-bit configuration
4) and the write data buses DI (n) and DI (n +
64) are arranged only. A D-type flip-flop having no load / hold function can be used. By using the dedicated interface block 14 for the set bit width, the circuit area can be greatly reduced. In this case, the input / output bit width is 12
Although only the case of limiting to 8 bits is shown, the same configuration can be applied to the case of limiting to 64 bits and limiting to 256 bits.

(Embodiment 3) FIG. 23 shows a module having a function of changing the width of a connected bus to 8 bits like a general-purpose DRAM when the DRAM macro 2 is set to 8 bits. 2 shows a detailed circuit diagram and an example of a connection relationship between the module and a DRAM macro 2. FIG. 29
Are bus connection modules. Bus connection module 2
9 is connected between the interface block 14 of the DRAM and the logic circuit 1. CB is a data bus that connects the bus connection circuit and the logic circuit 1. Its configuration is D
The data bus C is connected to the data input / output bus DQ of the RAM macro 2.
The logic circuit 1 is connected via B. FIG.
The DQ (8n + i)
(N = 0 to 7) and CB (i) (i = 0 to 7) are connected.

When the DRAM macro 2 has an 8-bit length, the DQs selected for each byte address and used for inputting / outputting data are bundled to form an 8-bit data in the same manner as a conventional general-purpose DRAM chip. Data input / output on the bus becomes possible, and the
Design resources such as a microcomputer having a bit bus can be utilized. Also, the number of wires can be greatly reduced,
The chip area and power consumption can be reduced. Although only the case where the length is set to 8 bits is shown here due to space limitations, other cases such as a 16-bit length and a 32-bit length can be configured with the same concept.

FIG. 24 shows a D / D having a wide input / output bit width.
The present invention relates to a mask layout technique that is effective in reducing a chip area when designing a RAM macro. In general, in a DRAM, data input / output signals from an interface circuit are linearly output outside the macro by the uppermost metal wiring layer.

However, in the case where the input / output bit width is wide as in this embodiment, when this method is used, the uppermost metal wiring layer is occupied by data input / output signals, and the number of contacts increases when wiring is performed. This causes problems such as a decrease in reliability and an increase in chip area. Therefore, in the present embodiment, as shown in this figure, the input / output buses are bundled at several places and connected to the outside of the DRAM macro, so that the areas A to D of the peripheral circuit 30 in which the power supply circuit and the like are arranged are the uppermost layers. The metal wiring layer can be used freely, the area efficiency of the wiring can be increased, and the chip area can be reduced.

As is clear from the above embodiment, the semiconductor memory device of the present invention can flexibly set the read bit width, read byte length, write bit width, and write byte length. By designing and preparing several types having a width and a byte length, it is possible to shorten the design period and reduce the design cost in customizing design for use in various applications.

The bit width and byte length used in the embodiment described above are examples, and it goes without saying that the present invention can be applied to other bit widths and byte lengths.

[0155]

According to the semiconductor memory device of the present invention, DR
The bit width of the input / output data bus of the AM macro can be set to several types by external input. By changing the byte mode setting, the input / output data bus can be selected more finely and used for various purposes. DRA
In the M macro, it is possible to provide a semiconductor memory device in which the optimum bit width of the input / output data bus for each application can be set only by external input.

Further, according to the semiconductor memory device of the present invention,
It is possible to activate the data input / output of the memory cells of the redundant repair block simultaneously with the data input / output of the normal memory cells, and it is possible to speed up the access of the redundant repair block which is a bottleneck in the access speed. A semiconductor memory device having an improved access speed can be provided.

Furthermore, according to the semiconductor memory device of the present invention,
The area of the largest unused block increases compared to the case where the top layer of the metal wiring on which the data bus wiring is arranged is arranged in parallel in a straight line, and the metal wiring of that part is used efficiently. And reduce chip size

[Brief description of the drawings]

FIG. 1 is a schematic layout diagram of a chip on which a semiconductor memory device of the present invention is mounted.

FIG. 2 is a block diagram showing an example of a signal flow between functional blocks of the DRAM macro according to the first embodiment of the present invention;

FIG. 3 is a block diagram of a data input / output unit of the DRAM macro cell of the present invention.

4 is a detailed circuit diagram of a unit block MBU of the main sense amplifier block 8 shown in FIG.

5 is a detailed circuit diagram of a unit block 23a (n) of the read line selector 23 shown in FIG.

6 is a detailed circuit diagram of a unit block 22a (n) of the write line selector 22 shown in FIG.

7 is a detailed circuit diagram of a unit block 25a (j) of the redundant line selector 25 shown in FIG.

FIG. 8 is a schematic diagram of the arrangement and connection relationship of a write line selector 22, a read line selector 23, and a redundant line selector 25 according to the present invention.

9 is an interface block 1 shown in FIG.
Detailed circuit diagram of each unit block in 4

FIG. 10 is a detailed circuit diagram of a column address decoder 12 shown in FIG. 2;

FIG. 11 shows a write control signal WEi (0 to 3) (i =
0 to 7) and a schematic diagram showing an example of a connection relationship between the write line selector 22.

12 is a schematic diagram showing an example of a connection relationship among a data output enable signal OEi in the interface block 14 of FIG. 3, a unit block 28a of the data output control circuit 28, and a unit block 24a of the input / output bus selector 24.

FIG. 13 is a diagram showing a relationship between a bit width setting signal of a DRAM macro of the present invention and a set bit width.

FIG. 14 is a diagram showing a relationship between a byte mode setting signal and a set bit width of a DRAM macro of the present invention.

FIG. 15 is a diagram showing a relationship between a byte address and a selected data input / output signal DQ when the DRAM macro of the present invention is set to a 128-bit width.

FIG. 16 is a schematic diagram showing a signal flow to a redundant unit block MBU of the present invention.

FIG. 17 is a diagram showing the timing of the DRAM macro of the present invention.

FIG. 18 is a diagram showing timing of a DRAM macro of the present invention.

FIG. 19 is a diagram showing a relationship between a set bit width of a DRAM macro of the present invention and a write data through signal.

FIG. 20 is a diagram showing a relationship between an input column address and a Y gate control signal;

FIG. 21 is a diagram showing the relationship between write enable signals when the DRAM macro of the present invention is set to a 128-bit width.

FIG. 22 is a diagram showing a detailed circuit diagram of an optimum unit block in the interface block when the DRAM macro of the present invention is set to a 128-bit width.

FIG. 23 is a circuit diagram of a module for reducing the bus width of the DRAM macro of the present invention to 8 bits.

FIG. 24 is a diagram showing a layout method of a data input / output bus effective for an embedded DRAM macro according to the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Logic circuit 2 DRAM macro 3 Pad 4 Memory array block 5 Row address decoder 6 Sense amplifier control circuit 7 Main bit line 8 Main sense amplifier block 9 Row address buffer 10 Row address predecoder 11 Column address buffer 12 Column address decoder 13 Control circuit 14 Interface Block 15 512K Memory Array 16 Sense Amplifier Block 17 Latch Circuit 18 Redundant Part Latch Circuit 19 1/4 Selector 20 Write Circuit 21 Read Circuit 22 Write Line Selector 23 Read Line Selector 24 I / O Bus Selector 25 Redundant Line Selector 26 redundant part write circuit 27 redundant part read circuit 28 data output control circuit 29 bus connection module 30 peripheral circuit MBL, NMBL ... main bit line C LK clock signal NRAS row address strobe signal NCAS column address strobe signal NWE write enable signal RAD row address signal CAD column address signal BAD byte address signal BMD byte mode setting signal BUSMODE bit width setting signal DQ data input / output bus SBL, NSBL redundancy section main Bit line MBU Unit block of main amplifier block WD Write signal of unit block MBU RD Read signal of unit block MBU MEQ Precharge signal QM1-3, 6-8, 10, 11, 14 N channel M
OS transistor VMBP Main bit line precharge potential QM4 to 5, 9, 12, 13 P-channel MOS transistor QM9 MSAN, MSAP main amplifier start signal MBS, NMBS Data line pair YPA (0-3), NYPA (0-3) Y Gate control signal NEQBUS Data line equalize signal TM1-4 Tristate inverter IM1-2 Inverter WEN (n) Write control signal DLCH Data latch signal SW1-7 Data selector YSR0-1 (j) Redundant relief read data signal YSI (k) To YSI (k + 3) select signal for redundancy repair DO256 (n + 192), DO256 (n + 64),
DO256 (n + 128), DO256 (n), DO1
28 (n + 64), DO128 (n), DO64 (n)
Read data signal PA2, PA3 Address decode signal IW1 Inverter TW1-11 Tristate inverter DI (n) Write data signal WEi (0-3) Write control signal YSEPENj Even part redundant enable signal YSOPENj Odd part redundant enable signal YSEPBj (0-3) ) Even part redundant repair address decode signal YSOPBj (0-3) Odd part redundant repair address decode signal NW (0-3) Write data through signal PBA (i) Byte address decode signal O0i-O6i Macro data output control signal OEi (0) 3) Block data output enable signal OECF Data output enable flag CADEC Write / read signal decode circuit BUD BUS signal decode circuit MBC read / write control circuit GD Y gate control signal decoding circuit SW8, SW9 switch YDEN Y decoder enable signal WECF write enable control signal

Continued on the front page (72) Inventor Kiyoto Ota 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. Inventor Masahiro Hirose 1006 Kazuma Kadoma, Kadoma-shi, Osaka F-term (reference) in Matsushita Electric Industrial Co., Ltd.

Claims (39)

[Claims] 1. A plurality of memory array blocks each including memory cells arranged in a matrix, a plurality of main bit lines connected to the memory array blocks, and the main bit lines connected to the main bit lines A latch circuit for latching the data of
A semiconductor memory device including a read circuit that outputs latch data of the latch circuit; a read line selecting unit that selects a read line of output data of the read circuit and changes a read bit width; A read / write line selected by the read line selecting unit, the interface circuit being configured to output data of the read line to a data bus, and a read bit width of the output data is variable. 2. The read line selection unit further includes a read line switching unit that selectively turns on at least a part of a plurality of parallel read line lines of the read circuit, and the read line switching unit turns on when the read line switching unit is selected. 2. The semiconductor memory device according to claim 1, wherein the number of read line lines to be read is a read bit width of output data. 3. The read line switching unit according to claim 2,
2. The semiconductor device according to claim 1, wherein a read line line group that is conductive according to a read bit width setting signal that is an external input signal is selected, and a read bit width of output data can be designated from outside. 4. The semiconductor device according to claim 1, wherein said semiconductor memory device is formed on the same semiconductor substrate as a logic circuit, and said read bit width setting signal is changed according to an operation mode of said logic circuit. Storage device. 5. A plurality of memory array blocks each including memory cells arranged in a matrix, a plurality of main bit lines connected to the memory cell array blocks, and the main bit lines connected to the main bit lines. A latch circuit for latching the data of the above, and a read circuit connected to the latch circuit and outputting the latch data of the latch circuit. A read line selector for changing the width, an interface circuit connected to the read line selector, and outputting data of a read line selected by the read line selector to a data bus;
A semiconductor memory device, comprising: an output bus selecting unit that selects an output bus of output data of the interface circuit to change a read byte length, and makes a read byte length of output data variable. 6. The output bus selection unit includes an output bus switching unit that selectively conducts at least a part of data buses among a plurality of parallel data buses of the interface circuit, and the output bus selection unit selects the output bus switching unit. 6. The semiconductor memory device according to claim 5, wherein the number of bytes of the conductive data bus is a byte length of the output data. 7. The output bus switching unit according to claim 5, wherein a data bus to be turned on is selected according to a read byte length setting signal which is an external input signal, and a byte length of read data can be designated from outside. Semiconductor device. 8. The semiconductor device according to claim 5, wherein the semiconductor memory device is formed on the same semiconductor substrate as a logic circuit, and the read byte length setting signal is changed according to a mode of operation of the logic circuit. Storage device. 9. The semiconductor memory device according to claim 6, wherein said read byte length setting signal is taken in at a rising edge of a row address strobe cycle start clock. 10. A plurality of memory array blocks each including memory cells arranged in a matrix, a plurality of main bit lines connected to the memory cell array blocks,
A semiconductor device comprising: a latch circuit connected to the main bit line for latching data of the main bit line; and a read circuit connected to the latch circuit and outputting latch data of the latch circuit. A read line selecting unit for selecting a read line of output data to change a read bit width; and a read line connected to the read line selector and outputting data of a read line selected by the read line selector to a data bus. An interface circuit;
An output bus selection unit that selects one of a plurality of parallel data buses among the plurality of parallel data buses connected to the interface circuit and provides output data, and selectively outputs a part of the plurality of parallel data buses; A semiconductor memory device that outputs output data only from a semiconductor memory device. 11. The output bus selection section can select an output bus to which output data is applied according to a byte address setting signal which is an external input signal, and designate an output bus to output output data from outside. The semiconductor device according to claim 10. 12. The semiconductor memory device according to claim 11, wherein said semiconductor memory device is formed on the same semiconductor substrate as a logic circuit, and said byte address signal is changed according to a mode of operation of said logic circuit. . 13. The semiconductor memory device according to claim 11, wherein said byte address signal is taken in at a rising edge of a column address strobe cycle start clock. 14. A plurality of memory array blocks each including a memory cell arranged in a matrix, a plurality of main bit lines connected to the memory cell array block,
A semiconductor device comprising: a latch circuit connected to the main bit line for latching data of the main bit line; and a read circuit connected to the latch circuit and outputting latch data of the latch circuit. A read line selecting unit for selecting a read line of output data to change a read bit width; and a read line connected to the read line selector and outputting data of a read line selected by the read line selector to a data bus. An interface circuit;
An output bus selector for selecting an output bus of output data of the interface circuit to change a read byte length, and providing output data only to the selected part of the plurality of parallel data buses; Wherein the read byte length is variable, and output data of a predetermined byte length is output from a selected one of a plurality of parallel data buses. 15. The data bus according to claim 14, further comprising a module for short-circuiting a predetermined set of the data buses connected to the interface circuit, wherein a bit width of the data bus can be adjusted.
3. The semiconductor memory device according to claim 1. 16. A plurality of memory array blocks each including memory cells arranged in a matrix, a plurality of main bit lines connected to the memory cell array blocks,
A semiconductor memory device comprising: a latch circuit connected to the main bit line for latching data of the main bit line; and a write circuit connected to the latch circuit and writing data to the latch circuit. A write line selection section for selecting a write bit width, a write circuit selection activation section for activating only the write circuit connected to the write line selected by the write line selection section, A semiconductor memory device comprising an interface circuit for writing external input data to a write circuit, wherein a data write bit width is variable. 17. The writing line selection unit includes a writing line switching unit that selectively turns on at least a part of a plurality of parallel writing line groups of the writing circuit, and the writing line switching unit is turned on by selecting the writing line switching unit. 17. The semiconductor memory device according to claim 16, wherein the number of lines in the write line group is a data write bit width. 18. The write line switching unit can select a write line line group to be conductive according to a write bit width setting signal which is an external input signal, and can externally designate a write bit width of data. 3. The semiconductor device according to claim 1. 19. The semiconductor memory device is formed on the same semiconductor substrate as a logic circuit, and the bit width setting signal is
3. The logic circuit according to claim 1, wherein said logic circuit is changed according to an operation mode of said logic circuit.
7. The semiconductor memory device according to 6. 20. The semiconductor memory device according to claim 16, further comprising a function of electrically disconnecting a bus from which data is not accessed. 21. A plurality of memory array blocks each including memory cells arranged in a matrix, a plurality of main bit lines connected to the memory cell array blocks,
A semiconductor memory device comprising: a latch circuit connected to the main bit line for latching data on the main bit line; and a write circuit connected to the latch circuit and writing data to the latch circuit. A write line selector for selecting a line to vary the write bit width, an input bus selector for selecting an input bus to the write circuit selected by the write line selector and varying the write byte length, A write circuit selection activating unit that activates only a write circuit connected to the write line selection unit and a write line selected by the input bus selection unit; and an interface that writes external input data to the activated write circuit. Circuit with variable data write byte length Semiconductor storage device. 22. The input bus selector, comprising: an input bus switching unit for selectively conducting at least a part of a plurality of parallel data buses to the write circuit. 22. The semiconductor memory device according to claim 21, wherein the number of bytes of the data bus which is turned on by the data bus is a byte length of the write data. 23. The input bus switching section according to claim 21, wherein a data bus to be turned on is selected in accordance with a write byte length setting signal which is an external input signal, and the byte length of write data can be designated from outside. Semiconductor device. 24. The semiconductor memory device is formed on the same semiconductor substrate as a logic circuit, and the byte length setting signal is
22. The semiconductor memory device according to claim 21, wherein an operation of said logic circuit is changed according to a mode. 25. The semiconductor memory device according to claim 21, wherein said byte length setting signal is taken in at a rising edge of a row address strobe cycle start clock. 26. A plurality of memory array blocks each including memory cells arranged in a matrix, a plurality of main bit lines connected to the memory cell array blocks,
A semiconductor memory device comprising: a latch circuit connected to the main bit line for latching data on the main bit line; and a write circuit connected to the latch circuit and writing data to the latch circuit. A write line selection unit for selecting a line to change a write bit width, and selecting a part of a plurality of parallel input buses to a write circuit selected by the write line selection unit to perform a predetermined write operation; A write circuit selecting / activating unit for selectively activating only the circuit group; and an interface circuit for writing external input data to the writing circuit group activated by the write circuit selecting / activating unit; Semiconductor memory device for writing data written only to a memory to a memory Place. 27. The write circuit selection activating section selects a write circuit group to be activated according to a byte address setting signal which is an external input signal, and can designate a write circuit group to write data from outside. 27. The semiconductor device according to 26. 28. The semiconductor memory device according to claim 26, wherein said semiconductor memory device is formed on the same semiconductor substrate as a logic circuit, and said byte address signal is changed according to a mode of operation of said logic circuit. . 29. The semiconductor memory device according to claim 26, wherein said byte address signal is taken in at a rising edge of a column address strobe cycle start clock. 30. A plurality of memory array blocks each including memory cells arranged in a matrix, a plurality of main bit lines connected to the memory cell array blocks,
A semiconductor memory device comprising: a latch circuit connected to the main bit line for latching data on the main bit line; and a write circuit connected to the latch circuit and writing data to the latch circuit. A write line selector for selecting a line to vary the write bit width, an input bus selector for selecting an input bus to the write circuit selected by the write line selector and varying the write byte length, A write circuit selecting and activating unit for selectively activating only a part of the write circuit group selected by the write line selecting unit and the input bus selecting unit; and a write circuit selecting and activating unit. Equipped with an interface circuit that writes external input data only to the write circuit group, and writes data A semiconductor memory device having a variable byte length and writing data of a predetermined byte length from a selected one of a plurality of parallel data buses. 31. The semiconductor according to claim 30, further comprising a module connected to the interface circuit and short-circuiting a predetermined set of the data buses connected to the interface circuit, wherein a bit width of the data bus can be adjusted. Storage device. 32. A plurality of memory array blocks each including memory cells arranged in a matrix, a plurality of main bit lines connected to the memory cell array blocks,
A latch circuit connected to the main bit line for latching data on the main bit line; a plurality of read circuits connected to the latch circuit and having a latch function of outputting latch data of the latch circuit; and the read circuit A semiconductor memory device including an interface circuit connected to the read circuit and outputting output data of the read circuit to a data bus; a read data latch control unit connected to the read circuit and controlling data through of the read circuit; Wherein the read data latch control unit passes data of the read circuit only for a predetermined period during a column address strobe cycle in a page mode, and when reading is performed in a page mode, the output bus is output in a first page. The first data read on the second page is output on the second page. The semiconductor memory device, wherein the data is output to the output bus until immediately before the input second data is output. 33. A plurality of memory array blocks each including memory cells arranged in a matrix, a plurality of main bit lines connected to the memory cell array blocks,
A latch circuit connected to the main bit line for latching data of the main bit line; a plurality of redundant memory array blocks each including a redundant memory cell arranged in a matrix; and a plurality of redundant memory cell blocks connected to the redundant memory cell array block A plurality of redundant main bit lines;
A plurality of redundant latch circuits for latching the data of the redundant main bit line, a read / write circuit connected to the latch circuit and having a function of reading and writing memory cell data, and a read / write circuit connected to the redundant latch circuit for storing redundant memory cell data; A semiconductor memory device having a redundant read / write circuit having a read / write function, an activation circuit for simultaneously activating the read / write circuit and the redundant read / write circuit, an interface circuit for inputting / outputting data from outside, and the interface A semiconductor memory device comprising a redundant line selector for selecting whether to connect a circuit to the read / write circuit or to the redundant read / write circuit. 34. The activation section connects a redundancy read / write circuit and an interface circuit based on a redundancy repair address signal which is an external input signal.
3. The semiconductor device according to claim 1. 35. The interface circuit according to claim 1, wherein several types of said interface circuits are designed according to said bit width, and said interface circuits corresponding to said bit width are used.
33. The semiconductor memory device according to any one of 4, 16, 21, 26, 30, and 32. 36. A plurality of memory array blocks each including memory cells arranged in a matrix, a plurality of main bit lines connected to the memory cell array blocks,
A semiconductor memory device comprising: a plurality of latch circuits connected to the main bit line to latch data of the main bit line; and a plurality of interface circuits connected to the latch circuit. A semiconductor memory device, wherein the data lines are bundled and arranged. 37. The semiconductor memory device according to claim 36, wherein an interval between the bundled data lines is a minimum rule of an interconnect interval in a manufacturing process. 38. The semiconductor memory device according to claim 36, wherein said plurality of bundled data lines are arranged at substantially equal intervals from said interface block to a chip end. 39. The semiconductor memory device according to claim 36, wherein said plurality of bundled data lines are an uppermost metal wiring layer.