JP3291206B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention generally relates to a DRAM (Dy
For more information, please refer to DRA
M relates to the layout of the memory core.

[0002]

2. Description of the Related Art FIG. 11 is a configuration diagram of a conventional DRAM for explaining a structure around a memory core. D in FIG.
The RAM includes a memory block 300, a row decoder (row decoder) 301, and a column decoder (column decoder) 30.
2, sense amplifier 303, input / output latch 304, data bus 305, sense amplifier area 306, local word driver area 307, cell block 308, global data bus 310, data bus switch 311, local data bus 312, column select line 313, It includes a global word line 314 and an input / output line 320. DR in FIG.
AM is shown in a simplified manner, and mainly describes an arrangement of data signal lines for reading and writing data transmission and an arrangement of address signal lines for specifying addresses in the memory block 300. Things.

A plurality of memory blocks 300 shown in FIG. 11 are prepared in one memory chip. When a certain address is designated for the memory chip, only one of the plurality of memory blocks 300 is selectively activated, and the selected memory block 300 is further activated.
Access is made to the specified address in.
The memory block 300 is provided with a plurality of cell blocks (cell matrices) 308 arranged vertically and horizontally. One cell block 308 includes a plurality of memory cells (not shown) arranged vertically and horizontally.
Holds bit data. In order to access a memory cell at a specific address in the memory block 300, a row decoder 301 and a column decoder 302 are used.

[0004] The row decoder 301 has a memory block 3
The position in the vertical direction in the drawing within 00 is selected. First, one of the plurality of global word lines 314 is selected (only the selected global word line is shown in the figure), and one row of the cell blocks 308 arranged vertically and horizontally is selected. The selected global word line 314 supplies a word address signal of a plurality of bits. In each column, a local word driver region 307 is provided between the cell blocks 308, and a local word driver column (not shown) is arranged in this region. Global word line 314
, One local word driver is selected from a row of local word drivers, and one word line connected thereto is activated.
Thereby, a memory cell is selected for a row.

When a memory cell is selected for a row, data is read (or written) from the selected memory cell. Explaining data reading as an example, first, data of a selected memory cell is supplied to a sense amplifier column 306 provided in a sense amplifier region 306 via a bit line (not shown) arranged in parallel with a column selection line 313. (Not shown). The sense amplifier area 306 is provided between each cell block 308 for each column of the cell blocks 308 arranged vertically and horizontally in the memory block 300.

The column decoder 302 selects a position in the memory block 300 in the horizontal direction in the drawing. That is, the column decoder 302 selects one of a plurality of column selection lines 313 extending in the vertical direction, and activates this to select a memory cell for a column. actually,
Column select line 313 is connected to a sense amplifier column in the sense amplifier region, and is activated by column select line 313.
Is read out to the local data bus 312 from the sense amplifier corresponding to.

[0007] The data read to the local data bus 312 is transmitted to the global data bus 310 via a data bus switch 311 provided between the cell block columns. Data on the global data bus 310 is read into the sense amplifier 303. Here, the data bus switch 311 is connected to the unselected local data bus 312 (the local data bus 312 is
08 is provided for each row of the memory matrix (provided for each row of the memory matrix).

In FIG. 11, a global data bus 31
Each of the 0s transmits, for example, 2 bits of information. In this case, each of the four sense amplifiers 303 can read 2-bit data in the corresponding cell block 3 in one data read.
08 will be received. That is, 8-bit data is read from the memory block 300. The 8-bit data is supplied to the data bus 305 in the memory chip. This data bus 305
Are commonly wired to a plurality of memory blocks 300 in a memory chip.

The data supplied to the data bus 305 is
Latched in the input / output latch 304, the input / output line 320
Output to the outside through

[0010]

In the DRAM, the concept of bandwidth is often used as an index indicating the data read / write capability. The bandwidth is a product of the operating frequency of the DRAM and the number of bits of data read / written from / to the memory chip. That is,
The higher the operating frequency and the number of data bits, the higher the DR
The AM bandwidth becomes larger.

[0011] Under the condition that the operating frequency is constant, it is necessary to increase the number of data bits in order to increase the bandwidth. For example, by selectively activating one or more memory blocks among a plurality of memory blocks in a memory chip to read data, the number of data bits can be increased. Assuming that 8-bit data can be read from one memory block as shown in FIG.
Bit data can be read. However, selectively activating a plurality of memory blocks is not preferable because it leads to an increase in power consumption. Therefore, it is desirable that the number of data bits can be increased in one memory block.

To increase the number of data bits in the memory block shown in FIG.
On the other hand, it is necessary to increase the number of buses themselves or the number of wirings constituting each bus. However, in the layout of the memory block of FIG. 11, since global data bus 310 extends in parallel to column selection line 313,
The global data bus 310 has no choice but to be arranged in the space of the local word driver area 307 or the like. That is, the global data bus 310 must be wired using an extra space other than the space occupied by the column selection line 313. The number of signal lines that can be arranged in this extra space is limited, and it is necessary to increase the space in order to increase the number of signal lines, but this leads to an increase in chip area, which is not preferable.

That is, in a layout as shown in FIG.
Attempting to increase the bandwidth involves an increase in chip area. Conversely, it is difficult to reduce the chip area while maintaining the same bandwidth. Considering the reduction in power consumption of the DRAM, it is preferable to increase the number of memory blocks into which a memory chip is divided and reduce the area of each memory block. This is because if the area of each memory block can be reduced, the area to be selectively activated becomes smaller, which leads to a reduction in power consumption. However, as described above, it is difficult to reduce the chip area of the memory block while maintaining the same bandwidth. Therefore, if an attempt is made to increase the number of memory blocks into which a memory chip is divided while maintaining the same bandwidth, the chip area of the entire memory chip increases.

An object of the present invention is to provide a DRAM capable of increasing the bandwidth without increasing the chip area.

[0015]

According to the present invention, there are provided a plurality of devices .
A bit line, and a first sense electrode connected to the bit line.
And the bit line via the first sense amplifier.
And the first data connected in parallel with the bit line.
A first bus and the first bit bus.
Signal for connecting the data bus line and the bit line
And a column select line for supplying
Connected to the column selection line via a connection portion.
And a global column selection line.

In the above invention, the first data bus for signal transmission is arranged parallel to the bit lines, and the column selection line for selecting a column address is arranged perpendicular to the bit lines.
With this configuration, the space occupied by the column selection lines in the conventional DRAM configuration can be used for the wiring of the first data bus for signal transmission. Therefore, many wirings can be provided for signal transmission .

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The principle and embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a configuration around a memory core of a DRAM based on the principle of the present invention. According to the present invention, by arranging the column selection lines and the data bus orthogonally in the memory block, a sufficient space can be secured for the data bus wiring.

The DRAM shown in FIG.
A row decoder 11, a column decoder 12, a data transmission buffer 13, an input / output latch 14, a second data bus 15,
Sense amplifier area 16, local word driver area 1
7, including a cell block (cell matrix) 18, a global column selection line 20, a row block selection unit 21, a column selection line 22, a row block selection line 23, a first data bus 24, a global word line 25, and an input / output line 30. .

A plurality of memory blocks 10 shown in FIG. 1 are prepared in one memory chip. When a certain address is specified for the memory chip, only one of the plurality of memory blocks 10 is selectively activated, and the specified address in the selected memory block 10 is accessed. Is performed. The memory block 10 is provided with a plurality of cell blocks (cell matrices) 18 arranged vertically and horizontally. One cell block 18 includes a plurality of memory cells (not shown) arranged vertically and horizontally, and each memory cell holds 1-bit data. In order to access a memory cell at a specific address in the memory block 10, a row decoder 11 and a column decoder 12 are used.

In the DRAM of the present invention shown in FIG. 1, row selection is performed using a local word driver column arranged in a global word line and a local word driver area, similarly to the prior art DRAM shown in FIG. is there. That is, the row decoder 11 first sets the plurality of global word lines 25
(Only the selected global word line is shown in the figure), and the cell blocks 18 arranged in rows and columns are selected.
Select one of the lines. The selected global word line 25 supplies a word address signal of a plurality of bits. In each column, a local word driver region 17 is provided between the cell blocks 18, and a local word driver column (not shown) is arranged in this region. According to the word address signal of the global word line 25, one local word driver is selected from a row of local word drivers, and one word line connected thereto is activated. Thereby, a memory cell is selected for a row.

A bit line connected to each cell of the cell block 18 extends in parallel with the first data bus 24, and a gate (not shown) is connected to a sense amplifier row (not shown) in the sense amplifier region 16. Connected via. Global column selection lines 20 extending from column decoder 12 in parallel with first data bus 24 are arranged between cell blocks 18 (local word driver area). This global column selection line 20 supplies a column address signal of a plurality of bits. The row decoder 11 selects a row block selection line 23 corresponding to the cell block 18 to be accessed (only the selected row block selection line is shown in the figure). , A column address signal of a plurality of bits is supplied through a row block selecting unit 21. The column address signal supplied to the column selection line 22 selectively turns on the gates connected to the sense amplifier row, thereby connecting the selected sense amplifier to the first data bus 24.
Connect to As a result, data is read from the selected sense amplifier to the first data bus 24 and supplied to the data transmission buffer 13. Conversely, in the case of data writing, the first data bus 24
The data is written to the selected sense amplifier via.

In the case of reading data, the data supplied to the data transmission buffer 13 is output to the second data bus 15. Data on the data bus 15 is latched by the input / output latch 14 and output to the outside via the input / output line 30. In the case of writing data, the data supplied from the input / output line 30 to the input / output latch 14
To the data transmission buffer 1 from the data bus 15.
3 is written.

As described above, in the DRAM according to the principle of the present invention, the first data bus 24 for signal transmission is arranged in the memory block 10 in parallel with the bit line and in the cell block 18.
Column selection line 2 for column address selection
2 are arranged perpendicular to the bit lines. With such a configuration, the space occupied by the column selection line 313 in the conventional DRAM configuration of FIG. 11 can be used for the wiring of the first data bus 24 for signal transmission. Therefore, a large number of signal transmission wirings can be provided for one row of cell blocks 18.

In the configuration shown in FIG. 1, one global column select line 20 is connected to two columns of cell blocks 18 on both sides thereof by a half of the first data bus 2 of each column.
4 is assigned. However, this is not an essential feature, and similar to the configuration of FIG. 11, one global column select line 20 is connected to the first data bus corresponding to the entire cell block with respect to one row of cell blocks on one side. 24. However, FIG.
With such a configuration, the length that the column selection line 22 extends from the row block selection unit 21 can be set short.

FIG. 2 is a schematic diagram showing the overall configuration of a DRAM based on the principle of the present invention. In the DRAM of FIG.
Command / address input terminal 36 and data input / output terminal 3
7 is connected to a node 34 of the chip 32 by a bonding wire or the like. The node 34 related to data input / output is connected to the data transmission buffer 13 via the input / output latch 14 and the second data bus 15 in FIG. The input / output latch 14 and the second data bus 15
It is omitted in FIG. 2 for simplification of the drawing. The node 34 related to the address input is connected to the row decoder 11 and the column decoder 12. As described with reference to FIG. 1, the row decoder 11 and the column decoder 12 perform row and column address selection for the memory block 10 including the plurality of cell blocks 18.

FIG. 3 shows the global column selection line 2 of FIG.
FIG. 5 is a diagram showing an example of a row block selection unit 21, a row block selection line 22, and a row block selection line 23. FIG.
1, the same components as those of FIG. 1 are referred to by the same numerals. The numbers in parentheses are used to distinguish a plurality of components having the same number.

In FIG. 3, among the four row block selecting sections 21 (1) to 21 (4), the row block selecting sections 21 (1) and 21 (2) are ,
This is for performing column selection for the cell blocks 18 (1) and 18 (2).
(3) and 21 (4) are for performing column selection for the cell blocks 18 (3) and 18 (4). Therefore, for example, when selecting the cell blocks 18 (1) and 18 (2) in the same row, both the row block selection lines 23 (1) and 23 (2) are selected. In FIG. 1, one row block selection line 23 is used to select one row of the cell block 18. However, in the embodiment of FIG. 3, two row blocks sandwiching a certain row are used. By selecting the row block selection line 23, the row is selected.

The column decoder 12 includes a NAND circuit 45
To 52. The NAND circuits 45 to 52 are provided with a column selection signal Y0Y1Y2 to / Y obtained by decoding three bits of the six bits Y0, Y1, Y2, Y3, Y4, and Y5 indicating the column address.
0 / Y1 / Y2 is used as one input, and the cell block column selection signal is used as the other input. Therefore, when the cell block column selection signal is high, an inverted signal of the column selection signals Y0Y1Y2 to / Y0 / Y1 / Y2 is output to the global column selection line 20. Therefore, out of the eight global column selection lines 20, only one becomes low.

For example, the row block selector 21 (3) includes NOR circuits 41 to 44, and NOR circuits 41 to 4
Reference numeral 4 designates the row block selection line 23 (3) as one input and the four global column selection lines 20 corresponding to the column selection signals Y0Y1Y2 to / Y0 / Y1Y2 as the other inputs. Other row block selectors 21 (1), 21 (2), and 21
(4) is also composed of a NOR circuit.

Hereinafter, the cell blocks 18 (3) and 18
The case where (4) is selected will be described as an example. When selecting cell blocks 18 (3) and 18 (4), both row block select lines 23 (3) and 23 (4) are pulled low. The other low block selection line 23 is high. For example, when the global column selection line 20 corresponding to the column selection signal Y0Y1Y2 is low, both inputs of the NOR circuit 41 are low. Therefore, the output of the NOR circuit 41 becomes high. The outputs of the other NOR circuits 42 to 44 are
Low. Therefore, in this case, four column selection lines 22
(3) Only one becomes high. The other column select lines 22 (1), 22 (2), and 22 (4) are all low.

The column selection signal output from the column decoder 12 is supplied to the row block selection line 23
Can be supplied to the selected column selection line 22. That is, only one of the eight column selection lines 22 corresponding to the selected one-row cell block 18 can be selected to be high.

In the example shown in FIG. 3, the global column select line 20 is connected to the decoded column select signals Y0Y1Y2 to / Y
Although shown as eight lines for transmitting 0 / Y1 / Y2, three lines for transmitting the column address signals Y0, Y1, and Y2 before decoding may be used. In this case, the row block selector 2
1 only needs to have the function of a decoder for decoding the column address signals Y0, Y1, and Y2.

As described with reference to FIG. 1, the column address signal (column selection signal) supplied through the column selection line 22 selectively turns on the gates connected to the sense amplifier columns in the sense amplifier region. By making it conductive,
The selected sense amplifier is connected to the first data bus 24. In FIG. 3, for example, at the time of data reading, the data read to the first data bus 24 is supplied to the sense amplifiers 13-1 to 13-64 of the data transmission buffer 13. Thus, in this example, the first data bus 24 transmits 64 bits (consisting of 64 pairs of signal lines).

A circuit for connecting the selected sense amplifier in the sense amplifier area to the first data bus 24 will be described below. FIG. 4 is a diagram showing an embodiment of the sense amplifier, the column selection line 22, and the first data bus 24 in the sense amplifier region. The column selection line 22 shown in FIG. 4 corresponds to, for example, the column selection line 22 (3) in FIG. That is, FIG. 4 shows, for example, a portion of the sense amplifier region 16A of FIG. 3, and the column selection line 22 is connected to the column selection signal Y0Y1.
Transmit Y2 ~ / Y0 / Y1Y2. In FIG. 4, the column selection signals are shown as Y0Y1Y2 * BLK to / Y0 / Y1Y2 * BLK.
3 indicates that the signal is selected by the signal BLK.

In FIG. 4, the sense amplifier array in the sense amplifier area includes NMOS transistors 62-1 to 62-1.
6 and PMOS transistors 63-1 to 63-16, for example, NMOS transistors 62-1 and 6-16.
2-2 and the PMOS transistors 63-1 and 63-2 constitute one sense amplifier. Also, for example, NMOS
Transistors 62-3 and 62-4 and PMOS transistors 63-3 and 63-4 constitute one sense amplifier, and so on. Therefore, FIG. 4 shows eight sense amplifiers. NMOS transistor 64
Reference numerals -1 to 64-8 denote transistors for driving the sense amplifier array. When signal NSA-d is high, these N
The MOS transistors 64-1 to 64-8 become conductive, and a current flows to the sense amplifier. At this time, the signal PS
Ad also goes high, supplying current flowing to the sense amplifier. Note that the current of the sense amplifier flows toward the low potential Vss.

Each sense amplifier is connected to a pair of bit lines. For example, a pair of bit lines BL0 and / BL0 is composed of NMOS transistors 62-1 and 62-2 and PM
It is connected to a sense amplifier including OS transistors 63-1 and 63-2. FIG. 4 shows eight pairs of bit lines B
L0 and / BL0 to BL7 and / BL7 are shown.
These eight pairs of bit lines are connected to the eight sense amplifiers.

NMOS transistors 61-1 to 61-
Reference numeral 24 is provided for precharging and short-circuiting the bit line. When the precharge signal PC1 is high, all the NMOS transistors 61-1 to 61-24 become conductive. As a result, all the bit line pairs have the voltage V
pr and ensure that each bit line in each bit line pair is shorted to the same potential. For example, when the precharge signal PC1 is high, NM
OS transistors 61-1 and 61-3 become conductive,
The bit lines BL0 and / BL0 are set to the potential of the voltage Vpr, and the NMOS transistor 61-2 is turned on to ensure that the bit lines BL0 and / BL0 are short-circuited to each other and have the same potential.

NMOS transistors 65-1 to 65-
Reference numeral 16 is provided for connecting the sense amplifier selected by the column selection signal of the column selection line 22 to the first data bus 24. FIG. 4 shows two pairs of first data buses DB0 and / DB0 and DB1 and / DB1. For example, if the column select signal Y0Y1Y2 * BLK is high,
The NMOS transistors 65-1 and 65-2 are turned on. As a result, the bit line BL0 is connected to the first data bus D
While connected to B0, bit line / BL0 is connected to first data bus / DB0. Therefore, the data of the bit lines BL0 and / BL0 amplified by the sense amplifier are supplied to the first data buses DB0 and / DB0.

In this manner, the first data buses DB0 and / DB0 are connected to one of the four pairs of bit lines BL0 and / BL0 to BL3 and / BL3. The first data buses DB1 and / DB1 are connected to one pair of four pairs of bit lines BL4 and / BL4 to BL7 and / BL7. The selection of the bit line pair is performed by the column selection signal Y0Y1Y2 * B of the column selection line 22 as described above.
Performed by LK ~ / Y0 / Y1Y2 * BLK. That is, in FIG. 4, one pair is selected from four pairs of bit lines and connected to the first data bus 24.

The sense amplifier region of FIG. 4 corresponds to the sense amplifier region 16A shown in FIG. The column selection signal supplied to the sense amplifier area 16A is 4 bits out of 8 bits. The remaining four bits are supplied to the sense amplifier area 16B in FIG. In the sense amplifier region 16B, as in the sense amplifier region 16A, when one bit of the 4-bit column selection signal becomes high,
One pair is selected from four pairs of bit lines and connected to the first data bus 24. However, the four pairs of bit lines to be selected include a sense amplifier region 16A and a sense amplifier region 16B.
And different. In this example, when one bit is selected from the 4-bit column selection line 22 (3),
All 4-bit column select lines 22 (4) are unselected. Therefore, in the configurations shown in FIGS. 3 and 4, one pair is selected from eight pairs of bit lines and connected to the first data bus 24.

In FIG. 4, the first data bus 24
Shield lines SH1 to SH3 are provided in parallel with (DB0 and / DB0 and DB1 and / DB1). The shield lines SH1 to SH3 are connected to the power supply voltage Vss. As a result, noise such as crosstalk between the pairs of the first data bus 24 can be suppressed.

In FIG. 4, an NMOS transistor 6 serving as a driver transistor for driving a sense amplifier is provided.
4-1 to 64-8 are provided for each sense amplifier. This driver transistor may be provided in common for some sense amplifiers. However, for example, one driver transistor is provided for all the sense amplifiers in FIG.
When a common wiring for connecting the driver transistor and each sense amplifier is provided at the position of the power supply line, the wiring becomes longer and the wiring resistance increases. In addition, since a large amount of current flows through this wiring, a large wiring resistance and a large amount of current increase the potential at the position of the sense amplifier. In order to avoid this phenomenon, it is preferable to connect as few sense amplifiers as possible to one driver transistor.

FIG. 5 is a diagram showing an embodiment of the sense amplifier in the sense amplifier area, the sense amplifier of the data transmission buffer 13, the second data bus 15, the input / output latch 14, and the periphery thereof. 5, the same components as those of FIGS. 1, 3, and 4 are referred to by the same numerals, and a description thereof will be omitted.

The upper part of FIG. 5 shows a part of the sense amplifier area 16A of FIG. 3, that is, the first data bus 24 of the circuit of FIG.
Are shown, a pair of DB0 and / DB0, bit lines BL0 and / BL0 connected thereto, and peripheral circuits.
In FIG. 5, the PMOS transistors 63-1 and 63-2 and the NMOS transistors 62-1 and 62- of FIG.
2 is designated by reference numeral 60.

A circuit including a PMOS transistor 66, an NMOS transistor 67, and inverters 68 and 69 generates the drive signals PSA-d and NSA-d of the sense amplifier described with reference to FIG. That is, the signal Se
When nseEnable is high, signals PSA-d and N
SA-d both go high.

The pair of first data buses DB0 and / DB0 extending from the sense amplifier area 16A is input to the sense amplifier 13-1 of the data transmission buffer 13 in FIG.
As shown in FIG. 5, the sense amplifier 13-1 is connected to the NM
OS transistors 91 to 93, readout amplifier 9
4 and a write amplifier 95. The NMOS transistors 91 to 93 are for performing a precharge and short operation on the pair of first data buses DB0 and / DB0. That is, the precharge signal PC2
Is high, the NMOS transistors 91 to 93 are turned on, DB0 and / DB0 are charged to the potential Vpr and short-circuited to each other.

The read amplifier 94 is supplied with amplifier drive signals S1 and S2, and the write amplifier 95 is supplied with amplifier drive signals S3 and S4. These amplifier drive signals S1 to S4 and the precharge signal PC2
Is generated by the signal generation circuit 70. The signal generation circuit 70 operates only when the sense amplifier 13-1 is selected from the plurality of sense amplifiers 13-1 to 13-64 (FIG. 3) of the data transfer buffer 13.

The selection of the sense amplifier is performed by the decoder 13
Performed by 0. The decoder 130 includes a NAND circuit 131 and an inverter 132, and among the six bits Y0, Y1, Y2, Y3, Y4, and Y5 indicating a column address, Y3 and Y3.
4. Decode the 3 bits Y5. In the example of FIG.
3. When Y4 and Y5 are both high (negative logic is acceptable),
The decoder 130 outputs high.

In the case of the read operation, since the output signal of the decoder 130 and the read signal Read-2 are both high, the NAND circuit 134 outputs low, and the output of the inverter 136 becomes high. At this time, the write signal Wri
Since te-2 is low, the output of inverter 135 is low.

In the case of a write operation, since the output signal of the decoder 130 and the read signal Write-2 are both high, the NAND circuit 133 outputs low, and the output of the inverter 135 goes high. At this time, the write signal Re
Since ad-2 is low, the output of inverter 136 is low.

In the case of the precharge operation, the write signal W
Since both write-2 and read signal Read-2 are low, the outputs of inverters 135 and 136 are both low. The outputs of the inverters 135 and 136 are supplied to the amplifier drive signal generation circuit 70. The amplifier drive signal generation circuit 70 includes NMOS transistors 71 to 77 and PMOS transistors 78 to 84.

NMOS transistors 76 and 77 and PM
The circuit composed of the OS transistors 83 and 84 constitutes a two-stage inverter. When the output of the inverter 135 is high, the amplifier drive signals S3 and S4 are made high. Conversely, when the output of the inverter 135 is low, the amplifier drive signals S3 and S4 are set low. Since the output of the inverter 135 goes high only in a write operation, the amplifier drive signals S3 and S4 go high only in a write operation.

NMOS transistors 74 and 75 and PM
The circuit composed of the OS transistors 81 and 82 constitutes a two-stage inverter. When the output of the inverter 136 is high, the amplifier drive signals S1 and S2 are made high. Conversely, when the output of the inverter 136 is low, the amplifier drive signals S1 and S2 are set low. Since the output of the inverter 136 goes high only during the read operation, the amplifier drive signals S1 and S2 go high only during the read operation.

NMOS transistors 71 to 73 and P
The circuit consisting of the MOS transistors 78 to 80 is AND
Circuit (a series connection of a NAND circuit and an inverter), and a precharge signal PC2 only when two inputs are high.
To high. These two inputs are connected to the write signal Wri.
Since it is an inverted signal of te-2 and the read signal Read-2, the precharge signal PC2 becomes high when neither the write operation nor the read operation is performed.

The read amplifier 94 operates when the amplifier drive signals S1 and S2 are both high, and the data bus DB
0 and / DB0 are amplified to form a second data bus 1
5 The read amplifier 94 includes the NMOS transistors 101 to 105 and the PMOS transistor 10.
6 to 111. Here, the NMOS transistor 10
Reference numeral 1 denotes a transistor for driving the amplifier, which conducts when the amplifier drive signal S1 is high and drives the amplifier. Also P
The MOS transistors 108 and 109 are provided to turn off the PMOS transistors 110 and 111 that supply the amplifier output to the second data bus 15 when the amplifier drive signal S2 is low, that is, other than the read operation. Other configurations are well-known amplifiers, and thus description thereof will be omitted.

The write amplifier 95 operates when both the amplifier drive signals S3 and S4 are high, amplifies the data on the second data bus 15, and outputs the data buses DB0 and / DB.
Supply 0. The write amplifier 95 is a PMOS transistor 110 for data output of the read amplifier 94.
And 111 are PMOS transistors 102 and 113
Since it is the same as the readout amplifier 94 except that it is replaced with NMOS transistors 114 to 117, the description is omitted.

In FIG. 5, the input / output latch 14 includes an input amplifier 141, an output amplifier 142, an output data latch circuit 143, a NOR circuit 146, and an inverter 147. The input amplifier 141 has data input terminals Din and / or
The data is received from Din, amplified and supplied to the second data bus 15. The configuration of the input amplifier 141 is the same as the configuration of the readout amplifier 94, and will not be described.

The output amplifier 142 is connected to the second data bus 15
, And amplifies it and supplies it to the output data latch circuit 143. The output amplifier 142 is a well-known amplifier, and a description thereof will be omitted. The output data latch circuit 143 includes NAND circuits 144 and 145 and forms a flip-flop. The output data latch circuit 143 holds the data supplied from the output amplifier 142 and supplies the data to the data output terminals Dout and / Dout.

The input amplifier 141 receives the write signal W
It operates when write-1 is high and the output amplifier 142
Operates when the read signal Read-1 is high.
Also, the write signal Write-1 and the read signal Re
The logical sum of ad-1 is obtained by the NOR circuit 146 and the inverter 147 and supplied to the precharge circuit 120.

The precharge circuit 120 is for precharging and short-circuiting the second data bus 15. The precharge circuit 120 is a PMOS transistor 1
21 to 123, the write signal Write-1 and the read signal Rea supplied from the input / output latch 14.
When the logical sum of d-1 is low, the second data bus 15 is precharged and short-circuited. That is, the precharge operation is performed when neither the write operation nor the read operation is performed.

As described above, the column select line 22 is selected by the configuration shown in FIG. 3, and the bit line of the column selected by the configuration shown in FIG. 4 is connected to the first data bus 24, as shown in FIG. According to the configuration, the sense amplifier of the data transmission buffer 13 is selected, and the selected one of the first data buses 24 is connected to the second data bus 15. This makes it possible to read data from the bit line to the second data bus 15 and write data from the second data bus 15 to the bit line. That is, if the configurations shown in FIGS. 3, 4, and 5 are used, the DRAM according to the principle of the present invention shown in FIG. 1 can be realized.

As can be seen from the above description, one pair is selected from eight pairs of bit lines by three bits of column addresses Y0, Y1, Y2 and connected to the first data bus 24.
Column addresses Y3, Y4, Y5 from the first data bus 24 of the pair
Are selected by the three bits of the second data bus 15
Connected to. Therefore, when the bit line has 2048 bits, the output from the data transmission buffer 13 is 32 bits (2048/64). Of course, the first data bus 2
4 is prepared for 256 bits (2048/8), so that if the selectivity of the sense amplifier in the data transmission buffer 13 is adjusted, data up to 256 bits can be supplied to the second data bus. It is possible.

FIG. 6 is a timing chart showing how data is transferred from the bit line to the second data bus when reading data. FIG. 6 corresponds to FIGS. 3 and 5 and corresponds to FIGS. 3 and 5, a sense amplifier driving signal SenseEnable, a bit line signal, a signal on the row block selection line 23, a signal on the global column selection line 20, a signal on the first data bus 24, Read signal Read-2, output signal of read amplifier 94, signal of second data bus 15, read signal Read
6 shows d-1 and an output signal of the output amplifier 142.

The signal on the row block selection line 23, the signal on the global column selection line 20, the signal on the first data bus 24, and the signal on the second data bus 15 have a slight signal timing difference depending on the selected column. . In FIG. 6, a plurality of lines seen at the rising and falling portions of the signal indicate the timing difference of the signal.

As shown in FIG. 6, the signal SenseE
The “enable” drives the sense amplifier 60, and at the same time, a signal appears on the bit line. Next, the row block selection line 23 and the global column selection line 20 are simultaneously activated, and the signal of the selected bit line appears on the first data bus 24 as data. The data on the first data bus 24 is supplied to the read amplifier 94 at the timing of the read signal Read-2. In response to this, data appears at the output of the read amplifier 94 and the data is propagated to the second data bus 15. The data on the second data bus 15 is supplied to the output amplifier 142 at the timing of the read signal Read-1. In response, data appears at the output of output amplifier 142.

FIG. 7 is a timing chart showing how data is transferred from the second data bus to the bit line at the time of data writing. FIG. 7 corresponds to FIGS. 3 and 5, and illustrates a write signal Write-1, a signal on the second data bus 15,
Input signal of write amplifier 95, write signal Wri
te-2, a signal of the global column selection line 20, a signal of the row block selection line 23, a bit line signal, and a signal SenseEnable for driving a sense amplifier.

In FIG. 7, as in FIG. 6, a plurality of lines appearing at the rising and falling portions of the signal indicate the timing difference of the signal. As shown in FIG. 7, data is output to the second data bus 15 at the timing of the write signal Write-1. Second data bus 1
The data of No. 5 becomes an input signal of the write amplifier 95, the write amplifier 95 operates at the timing of the write signal Write-2, and data is output to the first data bus. The global column selection line 20 and the row block selection line 23 are simultaneously activated, and the data on the first data bus appears on the selected bit line as a bit line signal. Then, the sense amplifier is driven by the signal SenseEnable to amplify the bit line signal.

Various modifications can be made to the above-described embodiment. For example, in the configuration of FIG. 5, the power consumption for transferring a large number of bits of data is large. Therefore, by suppressing the amplitude of the data signal on the first data bus 24 and / or the second data bus 15, the power consumption is reduced. It is conceivable to reduce the amount. In order to realize this, a transistor having a narrow gate width may be used as a transistor for outputting a signal from the sense amplifier or the like to the data bus. Specifically, in FIG. 5, the first data bus 2
4, the gate width of the NMOS transistors 65-1 and 65-2 for outputting a signal is reduced. The gate width of the PMOS transistors 110 and 111 for outputting a signal to the second data bus 15 when reading data is reduced. PMOS that outputs a signal to the first data bus 24 when writing data
Of the transistors 112 and 113 and the NMOS transistors 114 to 117, the gate width of at least one of the three transistors connected in series is reduced. The gate width of the output PMOS transistor of the output amplifier 111 that outputs a signal to the second data bus 15 at the time of data writing is reduced.

When the gate width is reduced in this manner, the output current and output voltage of the transistor do not change rapidly. If the change of the signal synchronized with the clock is relatively faster than the change of the output current and the output voltage of the transistor, the precharge operation and the short operation are performed before the signal reaches the maximum amplitude. Is small as a result.

At the time of data reading, the potential difference between the bit line pair is about 200 mV. Normally, this is amplified and supplied to the data bus. In this modification, for example, the potential difference between the pair of wires of the first data bus 24 is determined as
About 200 mV, and about 400 mV as a potential difference between the wires of the pair of the second data buses 15 can be used.

When writing data, the input amplifier 1
The input to 41 is such that the potential difference between the paired wires is about 3.3 V, for example, the potential difference between the paired wires of the second data bus 15 is about 400 mV, and the potential difference between the paired wires of the first data bus 24 is 3.3 V. It is possible to return to. Alternatively, in the first data bus 24, the signal at the time of data writing may have a suppressed signal amplitude.

As described above, if a signal having a small amplitude is used on the internal bus of the DRAM, unnecessary power consumption can be avoided even when a large number of data buses are activated to read / write a large amount of data. It is preferable because it is possible. As another modified example, a circuit in a sense amplifier area (FIG. 4)
In this case, a driver transistor for driving the sense amplifier can be provided for each column redundancy unit. Column redundancy means that when one pair of data buses (first data buses 24) cannot operate normally due to a manufacturing defect, a fuse or the like is switched before shipment of a product to another data bus by an address of the defective data bus pair. Means to allocate parts. By performing this column redundancy, the user can normally access all the addresses.

FIG. 8 shows an example of a circuit in which a driver transistor for driving a sense amplifier is provided for each column redundancy unit. 8, the same elements as those of FIG. 4 are referred to by the same numerals, and a description thereof will be omitted. In FIG. 8,
Driver transistor 64A includes a pair of data buses DB.
0 and / DB0, and a driver transistor 64B is provided for a sense amplifier connected to a pair of data buses DB1 and / DB1. In this example, column redundancy is performed for each pair of data buses.

In consideration of the column redundancy of the DRAM, it is desirable that the driver transistor be provided for each column redundancy unit. In this way, when it becomes necessary to replace the defective portion with another portion, it is possible to easily perform a procedure of disconnecting the driver transistor of the defective portion and connecting the driver transistor of the replaced portion. The column redundancy does not necessarily need to be performed in units of a pair of data buses, but may be performed in a larger or smaller unit. In this case, it is preferable that the driver transistors are also assigned to each column redundancy unit, not to the data bus pair.

As another modification, the second data bus 1
5 can be provided for data reading and data writing. FIG. 9 shows the sense amplifier in the sense amplifier area, the sense amplifier in the data transmission buffer 13, and the second data bus 1 when two systems of the second data bus 15 are provided.
FIG. 5 is a diagram showing an input / output latch 5, and its periphery.
9, the same components as those of FIG. 5 are referred to by the same numerals, and a description thereof will be omitted.

The second data bus 15A in FIG. 9 includes a read bus 15A-1 and a write bus 15A-2. The read bus 15A-1 is connected to the read amplifier 9
4 and the output amplifier 142, and the write bus 15
A-2 is connected to the input amplifier 141 and the write amplifier 95. These amplifiers 94, 95, 141, and 142 are the same as those in FIG. 5 except that they are separately connected to the read bus 15A-1 and the write bus 15A-2.

As described above, two values are used for reading and writing.
If a system bus is provided on the second data bus 15A, for example, when switching from a read operation to a write operation, the write bus 15A-2 is precharged during the read operation to prepare for write data transfer. As a result, the time required for the precharge operation can be reduced. Therefore, by providing two buses, high-speed data transfer becomes possible. It is needless to say that providing two buses on the first data bus also enables high-speed data transfer.

In the description of the above embodiment, the operation of the row decoder 11 and the timing of the row block selection signal of the row block selection line 23 are not particularly mentioned.
As described above, when the global word line 25 selects one row of the cell block 18, the row block selection line 23 connects the column selection line 22 corresponding to that row to the global column selection line 20. . Therefore,
It is also possible to read data at the same timing as in a conventional DRAM. However, it is also possible to improve the memory read speed by executing the row block (one row of the memory cell 18) selection by the row block selection line 23 like a bank interleave operation for switching banks.

FIG. 10 is a timing chart for explaining the operation of executing high-speed data reading by bank interleaving in the DRAM of the present invention shown in FIG. FIG.
The timing chart of 0 shows a word line selection signal (selection signal of the global word line 25), a signal SenseEnable for driving the sense amplifier in the sense amplifier area, a row block selection signal of the row block selection line 23, and a column of the global column selection line 20. 3 shows a selection signal and data on the first data bus 24. As a set of these signals,
Five sets of signals are shown for banks 1 to 5, which are row blocks accessed in order. 10 shows a clock signal and a command / address signal supplied in synchronization with the clock signal.
In the lowermost part, data on the first data bus 24 read from the five row blocks of bank 1 to bank 5 are shown.

In FIG. 10, address inputs A, B, C, D, and E of command / address inputs are respectively assigned to bank 1
Through address input for reading data in the bank 5. As shown in the figure, the address input is, for example,
It is performed every two clock cycles.

First, when the address A of the bank 1 is inputted, a word line selection signal is supplied to the bank 1,
The word line is selected. As a result, the data of the memory cell corresponding to the selected word line is supplied to the bit line. Further, the sense amplifier drive signal SenseEnable
Is supplied, and the data of the bit line is amplified by the sense amplifier. When the data of the bit line is amplified by the sense amplifier, the row block selection signal of the row block selection line 23 selects the bank 1 and, at the same time, the column selection signal of the global column selection line 20 is supplied. As a result, the data of the bit line is transferred to the first data bus 24.

First, when the address B of the bank 1 is inputted, a word line selection signal is supplied to the bank 2, and
The word line is selected. As a result, the data of the memory cell corresponding to the selected word line is supplied to the bit line. Further, the sense amplifier drive signal SenseEnable
Is supplied, and the data of the bit line is amplified by the sense amplifier. When the data on the bit line is amplified by the sense amplifier, the row block selection signal on the row block selection line 23 selects the bank 2 and, at the same time, the column selection signal on the global column selection line 20 is supplied. As a result, the data of the bit line is transferred to the first data bus 24.

As can be seen from a comparison between the operation for bank 1 and the operation for bank 2, the word line selection signal, the sense amplifier drive signal, and the bit line data are shifted between the banks 1 and 2 in terms of timing. overlapping. That is, for example, with respect to the bit line data of the bank 2, before the bit line data of the bank 1 starts the precharge operation after reading the data of the address A, the precharge operation is already completed and the data of the address B is read.
As described above, by performing the bank interleave operation between the bank 1 and the bank 2, the data of the address A of the bank 1 and the address B of the bank 2 are continuously transferred to the first bank.
It can be transferred to the data bus 24.

Similarly, address C of bank 3 and bank 4
, And the address E of the bank 5 are sequentially input, the data of each address is continuously read on the first data bus 24. Therefore, when five banks are successively accessed by the bank interleave operation, the first data bus 24 has addresses A to E
Are continuously read out.

As described above, in the DRAM of the present invention shown in FIG. 1, the word line selection and the sense amplifier drive for each row block (each row of the cell block 18) are continuously performed by overlapping the timings. Row block selection line 2
The bank interleave operation can be realized by selecting each bank (row block) by 3 and transferring data from the bit line to the first data bus 24. Thereby, high-speed data reading becomes possible. It is clear that the same applies to data writing.

Although the present invention has been described with reference to the embodiment and the modification, various modifications and changes can be made within the scope of the claims without being limited to the above embodiment or modification. .

[0087]

According to the present invention, a first data bus for signal transmission is arranged in parallel with a bit line, and a column selection line for selecting a column address is arranged perpendicular to the bit line.
With this configuration, the space occupied by the column selection lines in the conventional DRAM configuration can be used for the wiring of the first data bus for signal transmission. Therefore, many wirings can be provided for signal transmission.

In the present invention, a column address signal can be supplied to a column selection line via a global column selection line arranged in parallel with a bit line. Ma
In the present invention, one row of the cell block is selected by selecting one of the block selection lines by the row decoder, and the column selection line corresponding to this one row can be activated.

Further, in the present invention, by providing one sense amplifier driver for each of the first sense amplifiers, a common sense amplifier driver is provided for many first sense amplifiers. In this case, it is possible to suppress the fluctuation of the source potential which occurs in the case.

Further, according to the present invention, the variation of the source potential of the sense amplifier can be suppressed, and the procedure for replacing each pair of the first data buses is simplified by column redundancy. Further, in the present invention, the fluctuation of the source potential of the sense amplifier can be suppressed, and the procedure for replacing each pair of the first data buses by column redundancy is simplified.

In the present invention, crosstalk noise can be reduced between each pair of the first data buses. Further, in the present invention, when data is transferred from the first data bus to the second data bus, data on the first data bus can be selected to reduce the number of data bits. Therefore, the capacity for taking out a sufficiently large number of bits is provided in the first data bus, and
The number of bits can be reduced according to the number of bits required for the second data bus.

In the present invention, power consumption can be reduced by using a signal having a small amplitude.
Further, in the present invention, power consumption can be reduced by using a signal having a small amplitude.

In the present invention, by separately providing a data bus for reading data and a data bus for writing data, the time required for the precharge operation between read / write switching can be shortened. I can do it.

[Brief description of the drawings]

FIG. 1 is a diagram showing a layout of a DRAM according to the principle of the present invention.

FIG. 2 is a diagram showing an overall configuration of a DRAM according to the present invention.

FIG. 3 is a diagram illustrating an embodiment of a global column selection line, a row block selection unit, a column selection line, and a row block selection line in FIG. 1;

FIG. 4 is a diagram showing an example of a sense amplifier, a column selection line, and a first data bus in a sense amplifier region of FIG. 1;

5 is a diagram showing an example of a sense amplifier in a sense amplifier area, a sense amplifier of a data transmission buffer, a second data bus, an input / output latch, and peripherals thereof in FIG. 1;

FIG. 6 is a timing chart showing how data is transferred from a bit line to a second data bus at the time of data reading.

FIG. 7 is a timing chart showing how data is transferred from a second data bus to a bit line during data writing.

FIG. 8 is a diagram showing a circuit in which a driver transistor for driving a sense amplifier is provided for each column redundancy unit.

FIG. 9 is a diagram showing a sense amplifier in a sense amplifier area, a sense amplifier of a data transmission buffer, a second data bus, an input / output latch, and its periphery when two systems of a second data bus are provided.

FIG. 10 is a timing chart illustrating an operation of executing high-speed data reading by bank interleaving in the DRAM of FIG. 1;

FIG. 11 is a diagram showing a layout of a conventional DRAM.

[Explanation of symbols]

 Reference Signs List 10 memory block 11 row decoder 12 column decoder 13 data transmission buffer 14 input / output latch 15, 15A second data bus 16, 16A, 16B sense amplifier area 17 local word driver area 18 cell block 20 global column selection line 21 row block selection unit 22 column select line 23 row block select line 24 first data bus 25 global word line 30 input / output line 60 sense amplifier 70 signal generation circuit 94 read amplifier 95 write amplifier 130 decoder 141 input amplifier 142 output amplifier 143 output data latch circuit 300 memory block 301 row decoder 302 column decoder 303 sense amplifier 304 input / output latch 305 data bus 306 sense amplifier area 307 local Word driver areas 308 cell block 310 the global data bus 311 data bus switch 312 the local data bus 313 column selection lines 314 global word lines 320 output line

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Makoto Koga 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-7-320480 (JP, A) JP-A-6-36556 (JP, A) JP-A-8-139290 (JP, A) JP-A-3-225697 (JP, A) JP-A-8-106785 (JP, A) JP-A-8-212773 (JP , A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 11/401 G11C 11/41

Claims (12)

(57) [Claims] 1. A plurality of memos formed in a cell block.
Re- cell, a plurality of bit lines connected to the plurality of memory cells, and a plurality of first sense cells connected to the plurality of bit lines.
A first data bus arranged in parallel with the bit line, and a plurality of bit lines arranged orthogonal to the bit line.
Are connected to the first data bus line.
And a column selection line for supplying a signal for connection to the first data bus.
And the cell block further comprises:
A plurality are arranged in the orthogonal direction, and the
Extends parallel to the bit line and selects the column via a connection
The global column selection line that controls the line
Semiconductor memory characterized by being arranged between blocks
apparatus. 2. The semiconductor device according to claim 2 , wherein
The plurality of cells arranged in a direction parallel to a bit line;
That it further has a block selection line to select the lock
2. The semiconductor memory device according to claim 1, wherein: Wherein the connecting portion, claims and selects said column select lines based on the signal from the signal from the global column select line block selection lines
Item 3. The semiconductor memory device according to item 2 . 4. A device provided in correspondence with the first sense amplifier.
And a sense amplifier for driving the first sense amplifier.
4. A method according to claim 1, further comprising a driver.
A semiconductor memory device according to any of the above. 5. A data bus corresponding to each pair of the first data bus lines.
Provided to drive the first sense amplifier
2. The method according to claim 1, further comprising an amplifier driver.
4. The semiconductor memory device according to any one of 3 to 3. 6. A column redundancy unit is provided for each unit to be switched.
And a sense amplifier for driving the first sense amplifier.
4. A method according to claim 1, further comprising a driver.
A semiconductor memory device according to any of the above. 7. A data bus arranged in parallel with said first data bus.
And a power line for shielding the first data bus from each other.
4. The method according to claim 1, further comprising:
13. The semiconductor memory device according to claim 1. 8. A second data bus connected to the first data bus.
And the first data bus via the second sense amplifier.
And a second data bus connected to the second sense amplifier and selectively driving the second sense amplifier.
The cell block arranged in a direction orthogonal to the bit line.
Select at least one of the
Item 4. The semiconductor memory device according to item 2 or 3. 9. A signal transmitted on the first data bus.
Is the voltage applied externally to the data input / output terminals.
9. The semiconductor of claim 8, wherein the semiconductor is smaller than
Storage device. 10. A signal transmitted on the second data bus.
Signal amplitude is supplied to the data input / output terminal from the outside.
9. The semiconductor of claim 8, wherein the pressure is less than the pressure.
Body storage. 11. The data read bus as claimed in claim 11, wherein
Data bus for writing and data bus for writing data.
9. The semiconductor memory device according to claim 8, comprising:
Place. 12. The semiconductor device according to claim 12, wherein said plurality of bit lines are arranged in a direction parallel to said bit lines.
Two or more cell blocks of the plurality of cell blocks
Block selection lines so that the block operations overlap.
And a row decoder for selecting the next row.
The semiconductor memory device according to claim 2.