JP3695962B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a dynamic semiconductor memory device (DRAM), and more particularly to a semiconductor memory device having a so-called column redundancy function in which defective memory cells are replaced with spare memory cells in units of columns.
[0002]
[Prior art]
DRAMs used mainly as main storage devices such as personal computers (PCs) and workstations (WSs) have been increased in capacity by a factor of four for each generation. As a result, a large capacity of 1 Gb has already been realized even at the trial production stage and the conference presentation stage. In such a large-capacity DRAM chip, it is unlikely that all memory cells operate normally. Therefore, a so-called redundancy technique for replacing defective memory cells with spare memory cells is essential.
[0003]
If a large number of spare memory cells are prepared, the manufacturing yield of DRAM can be improved. However, of course, the chip size increases and the cost increases. Therefore, it is important to increase the efficiency of the redundancy technique, that is, to realize a high manufacturing yield with as few spare memory cells as possible.
[0004]
The redundancy technology is roughly divided into replacement methods for defective memory cells, and can be divided into row redundancy (Row Redundancy) that replaces in units of word lines and column redundancy (Column Redundancy) that replaces in units of column selection lines (CSL).
[0005]
Here, pay attention to column redundancy. In general, in column redundancy, a defective memory cell is replaced with a spare memory cell for each CSL.
Usually, the number of bit lines selected by one CSL is equal to the number of data input / output lines (DQ lines). Therefore, the minimum replacement unit for column redundancy is equal to the number of DQ lines.
[0006]
Now consider the number of DQ lines. There has been a demand for speeding up the DRAM, and at present, an access speed of about 50 ns to 60 ns is said to be the limit. Therefore, the bandwidth of data transfer has been improved by using a so-called multi-bit product having many data input / output pins. In order to increase the number of data input / output pins, it is necessary to increase the bus width inside the DRAM. For this purpose, it is necessary to increase the number of DQ lines.
[0007]
However, this means that the minimum replacement unit of the column redundancy is increased as described above. As a result, there is a problem that the column redundancy redundancy efficiency is lowered.
[0008]
Under such circumstances, a column redundancy technique has been developed that improves the remedy efficiency of defective products without increasing the number of spare memory cells. FIG. 12 shows an example. This technique is described in JP-A-5-54691, and will be described below.
[0009]
FIG. 12A shows the configuration of the main memory cell array of DRAM and its peripheral circuits described in the above publication. Similarly, FIG. 12B shows the configuration of the spare memory cell array and its peripheral circuits.
[0010]
In FIG. 12A, MC11, MC12, MC21 and MC22 are memory cells, WL1 and WL2 are word lines, BL1, / BL1, BL2 and / BL2 are bit line pairs, and SA1 and SA2 are the above two pairs. Sense amplifiers DQ0, / DQ0, DQ1, and / DQ1 that are connected to the bit line pairs BL1, / BL1, BL2, and / BL2 and sense data read out to the respective bit line pairs are DQ line pairs, Q11, Q12, and Q21. , Q22 turns the bit line pair BL1, / BL1, BL2, / BL2 after the data is sensed by the two sense amplifiers SA1, SA2 into the two pairs of DQ line DQ0, / DQ0, DQ1, / DQ1. It is a transfer gate that controls connection.
[0011]
All of the four transfer gates Q11, Q12, Q21, and Q22 are commonly connected to one column selection line CSL1.
In FIG. 12B, MCR11 and MCR12 are spare memory cells, BLR1 and / BLR1 are connected to a spare bit line pair, and SAR1 is connected to a spare bit line pair BLR1 and / BLR1, and read to this spare bit line pair. The sense amplifiers QR11, QR12, QR21, and QR22 sense data, and the spare bit line pair BLR1, / BLR1 after the data is sensed by the sense amplifier SAR1 are replaced with the two pairs of DQ line pairs DQ0, / DQ0, DQ1, This is a transfer gate that controls connection to / DQ1.
[0012]
Of the four transfer gates in FIG. 12B, the gates of the two transfer gates QR11 and QR12 are commonly connected to the spare column selection line CSLR1, and the remaining two transfer gates QR21 and QR22 are spare. Commonly connected to the column selection line CSLR2.
[0013]
In such a configuration, when one of the word lines WL1 and WL2 is selected by a row decoder (not shown), a memory cell connected to the activated word line, for example, the word line WL1 is selected. The data stored in each memory cell from the memory cells MC11 and MC12 is read to the bit line pair, in this case, the bit line pair BL1, / BL1, and then the sense amplifiers SA1, SA2 are activated. The stored data is sensed.
[0014]
After the sense amplifiers SA1 and SA2 are activated, sense data in one bit line pair BL1 and / BL1 is transferred to one DQ line pair DQ0 and / DQ0 via transfer gates Q11 and Q12. Sense data in the other bit line pair BL2, / BL2 is transferred to the other DQ line pair DQ1, / DQ1 via transfer gates Q21, Q22.
[0015]
If a defective memory cell exists in the memory cell array, spare memory cells MCR11 and MCR12 in the spare memory cell array are used instead of the defective memory cell. That is, when one or both of the memory cells MC11 and MC12 are defective cells, when an attempt is made to access both the memory cells MC11 and MC12 from the outside, the spare column selection line CSLR1 is driven by a redundancy control circuit (not shown). The transfer gates QR11 and QR12 are turned on. Thus, spare bit line pair BLR1, / BLR1 is connected to DQ line pair DQ0, / DQ0 via these two transfer gates QR11, QR12. As a result, data is read / written in the spare memory cells MCR11 and MCR12 instead of the memory cells MC11 and MC12.
[0016]
On the other hand, when one or both of the memory cells MC21 and MC22 are defective cells, the spare column selection line CSLR2 is driven and the two transfer gates QR21 and QR22 are turned on. The spare bit line pair BLR1 and / BLR1 are connected to the DQ line pair DQ1 and / DQ1 through the two transfer gates QR21 and QR22, and the spare memory cells MCR11 and MCR12 are replaced with the memory cells MC21 and MC22. Data is read and written.
[0017]
[Problems to be solved by the invention]
Incidentally, in the conventional example shown in FIG. 12, all of the four transfer gates Q11, Q12, Q21, Q22 on the memory cell array side are controlled by the signal of one column selection line CSL1.
[0018]
In general, since column redundancy replaces a defective column in units of column selection lines, if one or more of the memory cells MC11, MC12, MC21, MC22 becomes defective, the column redundancy All the bit line pairs connected to the selection line CSL1 are replaced with the spare columns in FIG. In that case, in a general replacement method, the first set of spare columns is connected to the DQ line pair of DQ0 and / DQ0, and the second set of spare columns is connected to the DQ line pair of DQ1 and / DQ1. become.
[0019]
For this reason, in this conventional example, the bit line pair BLR1, / BLR1 of the spare column is configured to be connectable to either DQ line pair, but such a configuration is not used. In comparison, there is a drawback that there is almost no improvement in the relief efficiency.
[0020]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device capable of improving the remedy efficiency of defective products without increasing the number of spare memory cells. It is in.
[0021]
[Means for Solving the Problems]
A semiconductor memory device of the present invention includes a plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, a plurality of data lines, A plurality of transfer gates for controlling connection of the plurality of bit lines to any of the plurality of data lines, a plurality of column selection lines for controlling conduction of the plurality of transfer gates, and one column address input from the outside of the chip And a column selection line driving circuit for simultaneously selecting and driving at least two of the plurality of column selection lines.
[0022]
A semiconductor memory device according to the present invention includes a plurality of memory cells, a plurality of bit line pairs connected to the plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, and a plurality of data line pairs. A plurality of transfer gates connected between the plurality of bit line pairs and the plurality of data line pairs, and a plurality of first lines connected to half of the plurality of data line pairs. A first column selection line for controlling conduction of the transfer gate and a second column selection line for controlling conduction of the plurality of second transfer gates connected to the remaining half of the plurality of data line pairs. And a column selection line driving circuit for simultaneously selecting and driving the first and second column selection lines in response to one column address input from the outside of the chip.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram schematically showing the internal structure of a DRAM chip according to the present invention. The DRAM chip includes an address input pin 10, a column address buffer 11, a column address strobe signal input pin 12, a / CAS buffer 13, a column partial decoder 14, a column decoder controller 15, a spare column address comparison circuit 16, a CSL driver group 17, A spare CSL driver group 18, a memory cell array 21 including a main body memory cell array 19 and a spare memory cell array 20, a sense amplifier (S / A) group 22 and the like are provided.
[0024]
A plurality of word lines WL are provided so as to cross the main memory cell array 19 and the spare memory cell array 20 continuously. The main memory cell array 19 is provided with a plurality of column selection lines CSL that cross in the direction intersecting the word lines WL. The spare memory cell array 20 is provided with a plurality of spare column selection lines CSLR (spare column CSL) in a direction parallel to the plurality of column selection lines CSL.
[0025]
The main memory cell array 19 and the spare memory cell array 20 are provided with a plurality of bit line pairs and spare bit line pairs, respectively, although not shown.
An address signal Addr is input to the address input pin 10 from the outside of the chip. Although only one address input pin 10 is shown for the sake of convenience, the address signal Addr actually consists of a plurality of bits, so that there are as many pins 10 as the number of bits of the address signal Addr. .
[0026]
A row address signal input from the address input pin 10 is supplied to a row circuit (not shown). A column address signal input from the address input pin 10 is supplied to the column address buffer 11.
[0027]
A column address strobe signal / CAS is input to the signal input pin 12 from the outside of the chip. The column address strobe signal / CAS is supplied to the / CAS buffer 13. The / CAS buffer 13 receives the column address strobe signal / CAS and outputs a latch signal. This latch signal is supplied to the column address buffer 11. Upon receiving the latch signal, the column address buffer 11 latches the column address signal and outputs an internal column address signal. The internal column address signal is supplied to the column partial decoder 14, the column decoder controller 15, and the spare column address comparison circuit 16.
[0028]
The column partial decoder 14 receives the internal column address signal and outputs three types of column address signals YAddr.A, YAddr.B and YAddr.C each consisting of a plurality of bits to the CSL driver group 17. Here, for example, YAddr.A and YAddr.B are both (N + 1) -bit signals, and YAddr.C is a (M + 1) -bit signal. However, the number of bits of each address signal is not limited to this.
[0029]
In addition, an example in which three types of column address signals YAddr.A, YAddr.B, and YAddr.C are output from the column partial decoder 14 has been shown, but the number of column address signals output from the column partial decoder 14 is as follows. It is not limited.
[0030]
The spare column address comparison circuit 16 has a fuse circuit 16a provided with a plurality of fuses, and a fuse latch circuit 16b that latches a signal according to the connection / disconnection state of the plurality of fuses provided in the fuse circuit 16a. are doing. In the spare column address comparison circuit 16, the defective column address is programmed by selectively blowing the fuse in the fuse circuit 16a. The spare column address comparison circuit 16 compares the internal column address signal output from the column address buffer 11 with a pre-programmed defective column address when data is accessed. Address signal Spare Select Addr. Is output. The defective column address signal Spare Select Addr. Is supplied to the column decoder controller 15 and the spare CSL driver group 18.
[0031]
The column decoder controller 15 outputs two sets of control signals CDRVL, / CDRVL, CDRVU, and / CDRVU according to the internal column address signal, the defective column address signal Spare Select Addr., And the CSL enable signal CSL Enable. These control signals CDRVL, / CDRVL, CDRVU, / CDRVU are supplied to the CSL driver group 17.
[0032]
The CSL driver group 17 includes a plurality of column selection lines according to the above three types of column address signals YAddr.A, YAddr.B, YAddr.C and the two sets of control signals CDRVL, / CDRVL, CDRVU, / CDRVU. Selectively drives CSL. At this time, the CSL driver group 17 is configured to select and drive a plurality of, for example, two of the plurality of column selection lines CSL simultaneously in response to one input of the internal column address signal.
[0033]
In addition to the defective column address signal “Spare Select Addr.”, The spare CSL driver group 18 includes a spare CSL enable signal “Spare CSL Enable”, a control signal / Select Lower DQ for selecting a lower bit side of the DQ line described later, and an upper A control signal / Select Upper DQ for selecting the bit side is supplied. The spare CSL enable signal Spare CSL Enable is a signal which is set to the H level when the spare CSL driver group 18 selectively drives the spare column selection line CSLR, and is generated by a circuit (not shown). The control signals / Select Lower DQ and / Select Upper DQ are signals that define which DQ line pair the spare column to be selected is connected to. For example, a specific bit of a column address signal is used as both signals. Can be used.
[0034]
The spare CSL driver group 18 selectively drives one or a plurality of spare column selection lines CSLR in accordance with these signals.
FIG. 2A shows a pattern layout of the entire DRAM chip of FIG. This example is a case of a DRAM chip 30 having a storage capacity of 64 Mbits, and the chip 30 is provided with four 16 Mbit subarrays 31-0 to 31-3 each having a storage capacity of 16 Mbits.
[0035]
FIG. 2B shows a pattern layout of one subarray 31-i (i = 0 to 3) in FIG. The subarray 31-i is provided with 16 1M bit memory cell array blocks 32-0 to 32-15 each having a storage capacity of 1M bit, a plurality of sense amplifiers 33, and a plurality of row decoders 34.
[0036]
FIG. 2C shows a pattern layout of one memory cell array block 32-j (j = 0 to 15) in FIG. In the memory cell array block 32-j, a part of the main memory cell array 19 and a part of the spare memory cell array 20 are provided. That is, the memory cells in the main memory cell array 19 are ½ of the memory capacity of the entire main memory cell array. ⁶ The memory cell array block is divided into 64 (1/64) times larger capacity, and the spare memory cell is arranged for each memory cell array block.
[0037]
FIG. 3 shows a specific circuit configuration of the main body memory cell array 19 and its peripheral circuits of the DRAM shown in FIG. 1, and FIG. 4 shows a specific circuit configuration of the spare memory cell array 20 and its peripheral circuits. .
[0038]
3, MC11, MC12, MC21, MC22, MC31, MC32, MC41, MC42, MC51, MC52, MC61, MC62, MC71, MC72, MC81, MC82... Are memory cells, WL1, WL2. BL1, / BL1,..., BL8, / BL8... Are provided in the sense amplifier group 22, and are connected to the bit line pairs BL1, / BL1,..., BL8, / BL8. Sense amplifiers DQ0, / DQ0 to DQ3, / DQ3 for sensing data read to each bit line pair are DQ line pairs, Q11, Q12, Q21, Q22, Q31, Q32, Q41, Q42, Q51, Q52, Q61, Q62, Q71, Q72, Q81, Q82. Transfer control for connecting the bit line pairs BL1, / BL1,..., BL8, / BL8... After the data is sensed at the buffers SA1,... SA8... To the four DQ line pairs DQ0, / DQ0 to DQ3, / DQ3. Gates, CSL11, CSL12, CSL21, CSL22... Are column selection lines that are selectively driven by the CSL driver group 17.
[0039]
In the CSL driver group 17, a plurality of CSL drivers 41-11, 41-12, 41-21, 41-21,... Are provided.
The CSL driver 41-11 includes a 0th bit signal of the (N + 1) -bit column address signal YAddr.A, a 0th bit signal of the (N + 1) -bit column address signal YAddr.B, and the (M + 1) ) The 0th bit signal of the column address signal YAddr.C and the control signals CDRVL and / CDRVL are supplied.
[0040]
The CSL driver 41-12 receives the 0th bit signal of the (N + 1) -bit column address signal YAddr.A, the 0th bit signal of the (N + 1) -bit column address signal YAddr.B, and the (M + 1) ) The 0th bit signal of the column address signal YAddr.C and the control signals CDRVU and / CDRVU are supplied. That is, the same column address signal as that supplied to the previous CSL driver 41-11 is supplied to the CSL driver 41-12. However, the types of the control signals CDRV and / CDRV are different.
[0041]
The CSL driver 41-21 receives the first bit signal of the (N + 1) -bit column address signal YAddr.A, the zeroth bit signal of the (N + 1) -bit column address signal YAddr.B, and the (M + 1) ) The 0th bit signal of the column address signal YAddr.C and the control signals CDRVL and / CDRVL are supplied.
[0042]
The CSL driver 41-22 includes a first bit signal of the (N + 1) -bit column address signal YAddr.A, a zeroth bit signal of the (N + 1) -bit column address signal YAddr.B, and the (M + 1) ) The 0th bit signal of the column address signal YAddr.C and the control signals CDRVU and / CDRVU are supplied. That is, the same column address signal as that supplied to the previous CSL driver 41-21 is supplied to the CSL driver 41-22. However, the types of the control signals CDRV and / CDRV are different.
[0043]
Each of these CSL drivers decodes the column address signal when the respective control signal CDRVL or CDRVU is at H level and / CDRVL or / CDRVU is at L level, and drives the corresponding column selection line CSL by the decoded output. The levels of the control signals CDRVL, / CDRVL and CDRVU, / CDRVU are based on the column address input to the column decoder controller 15 in FIG. 1 and the defective column address signal Spare output from the spare column address comparison circuit 16. Set based on both Select Addr.
[0044]
The four transfer gates Q11, Q12, Q21, Q22 are provided between two bit line pairs BL1, / BL1, BL2, / BL2 and two DQ line pairs DQ0, / DQ0, DQ1, / DQ1. Each is connected. The gates of these four transfer gates Q11, Q12, Q21, and Q22 are commonly connected to the column selection line CSL11.
[0045]
The four transfer gates Q31, Q32, Q41, and Q42 are provided between two bit line pairs BL3, / BL3, BL4, / BL4 and two pairs of DQ line pairs DQ0, / DQ0, DQ1, / DQ1. Each is connected. The gates of these four transfer gates Q31, Q32, Q41, and Q42 are commonly connected to the column selection line CSL12.
[0046]
The four transfer gates Q51, Q52, Q61, Q62 are provided between two bit line pairs BL5, / BL5, BL6, / BL6 and two pairs of DQ line pairs DQ2, / DQ2, DQ3, / DQ3. Each is connected. The gates of these four transfer gates 51, Q52, Q61, and Q62 are commonly connected to the column selection line CSL21.
[0047]
The four transfer gates Q71, Q72, Q81, Q82 are provided between two bit line pairs BL7, / BL7, BL8, / BL8 and two DQ line pairs DQ2, / DQ2, DQ3, / DQ3. Each is connected. The gates of these four transfer gates 71, Q72, Q81, Q82 are commonly connected to the column selection line CSL22.
[0048]
In FIG. 4, MCR11, MCR12, MCR21, MCR22, MCR31, MCR32, MCR41, MCR42... Are spare memory cells, BLR1, / BLR1, BLR2, / BLR2, BLR3, / BLR3, BLR4, / BLR4. The pair, SAR1, SAR2, SAR3, and SAR4 are connected to the spare bit line pairs BLR1, / BLR1, BLR2, / BLR2, BLR3, / BLR3, BLR4, / BLR4,. The sense amplifiers QR11, QR12, QR21, QR22, QR31, QR32, QR41, QR42, QR51, QR52, QR61, QR62, QR71, QR72, QR81, QR82. The spare bit line pairs BLR1, / BLR1, BLR2, / BLR2, BLR3, / BLR3, BLR4, / BLR4... After the data is sensed by R1... SAR8. , / DQ3 transfer gates CSLR11, CSLR12, CSLR21, CSLR22,... Are spare column selection lines that are selectively driven by the output of the spare CSL driver group 18.
[0049]
In the spare CSL driver group 18, spare CSL drivers 42-1, 42-2,... Are provided. Each of these spare CSL drivers has two output nodes.
[0050]
The spare CSL driver 42-1 includes a 0th bit signal of the (P + 1) -bit defective column address signal Spare Select Addr., A spare CSL enable signal Spare CSL Enable, a control signal for selecting a lower-order DQ line / A control signal / Select Upper DQ for selecting the Select Lower DQ and the upper DQ line is supplied. Spare column selection line CSLR11 is connected to one output node of spare CSL driver 42-1, and spare column selection line CSLR12 is connected to the other output node.
[0051]
The spare CSL driver 42-12 includes a first bit signal of the defective column address signal Spare Select Addr., A spare CSL enable signal Spare CSL Enable, a control signal / Select Lower DQ for selecting a lower DQ line, and an upper bit. A control signal / Select Upper DQ for selecting the side DQ line is supplied. Spare column selection line CSLR21 is connected to one output node of spare CSL driver 42-2, and spare column selection line CSLR22 is connected to the other output node.
[0052]
The two transfer gates QR11 and QR12 are connected and connected between the spare bit line pair BLR1, / BLR1 and the DQ line pair DQ0, / DQ0, respectively. The gates of these two transfer gates QR11 and QR12 are commonly connected to a spare column selection line CSLR11.
[0053]
The two transfer gates QR31 and QR32 are connected and connected between the spare bit line pair BLR1, / BLR1 and the DQ line pair DQ2, / DQ2. The gates of these two transfer gates QR31 and QR32 are commonly connected to a spare column selection line CSLR12.
[0054]
The two transfer gates QR21, QR22 are connected and connected between the spare bit line pair BLR2, / BLR2 and the DQ line pair DQ1, / DQ1, respectively. The gates of these two transfer gates QR21 and QR22 are commonly connected to a spare column selection line CSLR11.
[0055]
The two transfer gates QR41 and QR42 are connected and connected between the spare bit line pair BLR2, / BLR2 and the DQ line pair DQ3, / DQ3, respectively. The gates of these two transfer gates QR41 and QR42 are commonly connected to a spare column selection line CSLR12.
[0056]
The two transfer gates QR51 and QR52 are connected and connected between the spare bit line pair BLR3 and / BLR3 and the DQ line pair DQ0 and / DQ0, respectively. The gates of these two transfer gates QR51 and QR52 are commonly connected to a spare column selection line CSLR21.
[0057]
The two transfer gates QR61 and QR62 are connected and connected between the spare bit line pair BLR3 and / BLR3 and the DQ line pair DQ2 and / DQ2. The gates of these two transfer gates QR61 and QR62 are commonly connected to a spare column selection line CSLR21.
[0058]
The two transfer gates QR71 and QR72 are connected and connected between the spare bit line pair BLR4 and / BLR4 and the DQ line pair DQ1 and / DQ1, respectively. The gates of these two transfer gates QR71 and QR72 are commonly connected to a spare column selection line CSLR21.
[0059]
The two transfer gates QR81 and QR82 are connected and connected between the spare bit line pair BLR4 and / BLR4 and the DQ line pair DQ3 and / DQ3, respectively. The gates of these two transfer gates QR81 and QR82 are commonly connected to a spare column selection line CSLR22.
[0060]
In such a configuration, when there is no defective memory cell in the main body memory cell array 19, that is, when the defective column address is not programmed by the spare column address comparison circuit 16, the word line WL1 is handled from the outside of the chip. Assume that a row address signal and a column address signal corresponding to the column selection lines CSL11 and CSL12 (one column address) are input. At this time, the word line WL1 is driven by the output of a row decoder (not shown). Further, the column decoder controller 15 sets both the control signals CDRVL and CDRVU to the H level and both / CDRVL and / CDRVU to the L level. As a result, the two CSL drivers 41-11 and 41- in the CSL driver group 17 are displayed. 12 The column selection lines CSL11 and CSL12 are selectively driven at the same time.
[0061]
When the word line WL1 is driven, the stored data is read from the memory cells MC11, MC21, MC31, MC41, MC51, MC61, MC71, MC81... In the main body memory cell array 19 connected to the word line WL1. Thereafter, the sense amplifiers SA1,... SA8,... Are activated to sense data.
[0062]
On the other hand, when the column selection lines CSL11 and CSL12 are selectively driven at the same time, the four transfer gates Q11, Q12, Q21, and Q22 whose gates are connected to the column selection line CSL11 become conductive, and the bit line pair BL1, / BL1, BL2, and / BL2 are connected to the DQ line pair DQ0, / DQ0, DQ1, and / DQ1 through these transfer gates. At the same time, the four transfer gates Q31, Q32, Q41, Q42 whose gates are connected to the column selection line CSL12 are turned on, and the bit line pairs BL3, / BL3, BL4, / BL4 are connected to the DQ line via these transfer gates. Connected to pairs DQ2, / DQ2, DQ3, / DQ3.
[0063]
In this way, the data stored in the four memory cells MC11, MC21, MC31, MC41 is sensed and transmitted to the four DQ line pairs DQ0, / DQ0 to DQ3, / DQ3 as 4-bit data. .
[0064]
At this time, since the spare CSL driver group 18 does not drive any spare column selection line, data reading from the spare memory cell is not performed.
In the above description, an example in which an address signal is supplied from outside the chip to select a memory cell and data is read from the selected memory cell is taken as an example. However, when data is written to the selected memory cell, Write data may be given to each of the four pairs of DQ lines.
[0065]
Next, a case where a defective memory cell exists in the main body memory cell array 19 will be described. If, for example, the memory cell MC11 is a defective memory cell, the spare column address comparison circuit 16 selectively blows the fuse in the fuse circuit 16a, so that the column address corresponding to the defective memory cell becomes a defective column. Pre-programmed as an address.
[0066]
After the programming, when a column address corresponding to a defective memory cell is input to the spare column address comparison circuit 16, a defective column address signal Spare Select Addr. Is output from the spare column address comparison circuit 16. In this case, only the 0th bit signal of the defective column address signal Spare Select Addr. Becomes H level, and all signals other than 0 bit become L level. When the defective column address signal Spare Select Addr. Is input to the column decoder controller 15, the column decoder controller 15 sets the control signal CDRVL to L level and / CDRVL to H level, sets the control signal CDRVU to H level, / CDRVU is set to L level.
[0067]
As a result, the CSL driver 41-11 does not drive the column selection line CSL11 regardless of the column address signal. Therefore, the two bit line pairs BL1, / BL1, BL2, / BL2 including the bit line BL1 to which the defective memory cell MC11 is connected are not connected to the DQ line pairs DQ0, / DQ0, DQ1, and / DQ1.
[0068]
On the other hand, the CSL driver 41-12 drives the column selection line CSL12, and the two bit line pairs BL3, / BL3, BL4, / BL4 are connected to the DQ line pairs DQ2, / DQ2, DQ3, / DQ3.
[0069]
At this time, the control signal / Select Lower DQ input to the spare CSL driver group 18 is L level, the control signal / Select Upper DQ is H level, and only the signal output from the spare CSL driver 42-1 to the spare column selection line CSL11 is received. Is set to H level. As a result, the four transfer gates QR11, QR12, QR21, QR22 whose gates are connected to the spare column selection line CSL11 become conductive, and the spare bit line pair BLR1, / BLR1, BLR2, / BLR2 To the DQ line pair DQ0, / DQ0, DQ1, and / DQ1.
[0070]
That is, the four memory cells MC11, MC12, MC21, and MC22 including the defective memory cell MC11 are thereby replaced with the spare memory cells MCR11, MCR12, MCR21, and MCR22.
[0071]
Here, when a failure occurs in any of the memory cells MC11, MC12, MC21, and MC22, the spare column selection line CSLR11 is driven in place of the column selection line CSL11. Are replaced by spare memory cells MCR11, MCR12, MCR21, and MCR22.
[0072]
If any of the memory cells MC31, MC32, MC41, and MC42 is defective, the control signal CDRVL supplied to the CSL driver 41-11 is H level, / CDRVL is L level, and the CSL driver 41-12 The control signal CDRVU supplied to is set to L level and / CDRVU is set to H level. Conversely, the column selection line CSL11 is driven by the CSL driver 41-11, and the column selection line CSL12 is driven by the CSL driver 41-12. Disappear.
[0073]
At this time, the control signal / Select Lower DQ input to the spare CSL driver group 18 is H level, the control signal / Select Upper DQ is L level, and only the signal output from the spare CSL driver 42-1 to the spare column selection line CSL12 is displayed. Is set to H level. As a result, the four transfer gates QR31, QR32, QR41, QR42 whose gates are connected to the spare column selection line CSL12 become conductive, and the spare bit line pair BLR1, / BLR1, BLR2, / BLR2 To the DQ line pair DQ2, / DQ2, DQ3, / DQ3.
[0074]
The other column selection lines CSL21 and CSL22 are selected at the same time when one internal column address is input.
As described above, in the DRAM according to the present embodiment, a column selection line is provided independently for each bit line pair that is half the number of DQ line pairs, and the two column selection lines are activated simultaneously, and in units of column selection lines. By replacing the memory cells of the main body memory cell array with spare memory cells, the column redundancy repair unit can be reduced, and the repair efficiency can be improved.
[0075]
Further, in the case where the same relief efficiency as that of the prior art is ensured, the number of spare memory cells can be reduced, so that the chip area can be reduced. As a result, the manufacturing cost of the chip can be reduced.
[0076]
In addition, high relief efficiency can be realized even when the number of DQ line pairs is increased for high speed and wide bandwidth.
FIG. 5A shows an example of a specific circuit configuration of the CSL driver 41-11 that selectively drives the column selection line CSL11 in FIG. The other CSL drivers all have the same circuit configuration, except that the input column address signal and the control signals CDRV and / CDRV are higher and lower.
[0077]
The CSL driver 41-11 is provided with a three-input NAND gate 51, a P-channel transistor 52, two N-channel transistors 53 and 54, and two inverters 55 and 56.
[0078]
The NAND gate 51 includes a 1-bit signal of the (N + 1) -bit column address signal YAddr.A, a 1-bit signal of the (N + 1) -bit column address signal YAddr.B, and the (M + 1) -bit. 1-bit signal is supplied from the column address signal YAddr.C.
[0079]
The control signal CDRVL is supplied to the source of the P-channel transistor 52. The gate of the transistor 52 is connected to the output node of the NAND gate 51. The drain of the N-channel transistor 53 is connected to the drain of the transistor 52.
[0080]
The source of the transistor 53 is connected to the ground voltage node. The gate of the transistor 52 is connected to the output node of the NAND gate 51.
[0081]
The drain of the N-channel transistor 54 is connected to the drain common connection node of the transistors 52 and 53. The source of the transistor 54 is connected to the ground voltage node. Further, the control signal / CDRVL is supplied to the gate of the transistor 52.
[0082]
The input node of the inverter 55 is connected to the drain common connection node of the transistors 52, 53 and 54. The output node of the inverter 55 is connected to the input node of the inverter 56. The output node of the inverter 56 is connected to the column selection line CSL11.
[0083]
In the CSL driver having such a configuration, the output signal of the NAND gate 51 becomes L level when all the 1-bit signals of the column address signals YAddr.A, YAddr.B and YAddr.C are all at H level. When the control signal CDRVL is at the H level and / CDRVL is at the L level, the H level of the signal CDRVL is supplied to the source of the transistor 52 and the transistor 54 is turned off, so that the circuit including the transistors 52 and 53 operates as an inverter. Then, the output signal of the drain common connection node of the transistors 52, 53, and 54 becomes H level. Therefore, the output signal of the inverter 55 becomes L level, the output signal of the inverter 56 becomes H level, and the corresponding column selection line CSL11 is selectively driven.
[0084]
Here, if at least one of the 1-bit signals of each of the column address signals YAddr.A, YAddr.B and YAddr.C is L level, the output signal of the NAND gate 51 becomes H level, and the corresponding column The selection line CSL11 is not selected.
[0085]
Further, when the control signal CDRVL is L level and / CDRVL is H level, since the H level signal / CDRVL is input to the source of the transistor 52, the transistor 54 is turned on, and the drains of the transistors 52, 53 and 54 are common. The output signal of the connection node becomes L level. Accordingly, the output signal of the inverter 55 is at the H level, the output signal of the inverter 56 is at the L level, and the corresponding column selection line CSL11 is in a non-selected state.
[0086]
FIG. 5B shows an example of a specific circuit configuration of the spare CSL driver 42-11 in FIG. The other spare CSL drivers all have the same circuit configuration, and only the bit position of the input defective column address signal Spare Select Addr. Is different.
[0087]
The spare CSL driver 42-11 is provided with a 2-input NAND gate 61, two 2-input NOR gates 62, 63, and four inverters 64-67.
[0088]
The NAND gate 61 receives a bit signal having a defective column address signal Spare Select Addr. And a spare CSL enable signal Spare CSL Enable. The one NOR gate 62 receives a control signal / Select Lower DQ for selecting the lower DQ line and the output signal of the NAND gate 61.
[0089]
The input node of the inverter 64 is connected to the output node of the NOR gate 62. The input node of the inverter 65 is connected to the output node of the inverter 64. The output node of the inverter 65 is connected to the spare column selection line CSLR11.
[0090]
The other NOR gate 63 receives a control signal / Select Upper DQ for selecting the upper DQ line and an output signal of the NAND gate 61.
The input node of the inverter 66 is connected to the output node of the NOR gate 63. The output node of the inverter 66 is connected to the input node of the inverter 67. The output node of the inverter 67 is connected to the spare column selection line CSLR12.
[0091]
In such a configuration, when the signal of a certain bit of the defective column address signal Spare Select Addr. Input to the NAND gate 61 and the spare CSL enable signal Spare CSL Enable are both at the H level, the output signal of the NAND gate 61 is L Become a level.
[0092]
At this time, if the control signal / Select Lower DQ for selecting the lower DQ line is L level, the output signal of the NOR gate 62 becomes H level, the output signal of the inverter 64 is L level, and further the inverter 65 The output signal becomes H level, and spare column selection line CSLR11 is selectively driven.
[0093]
On the other hand, when the output signal of NAND gate 61 is at L level, if the control signal / Select Upper DQ for selecting the upper DQ line is at L level, the output signal of NOR gate 63 becomes H level, and the inverter The output signal of 65 becomes L level and the output signal of the inverter 66 becomes H level, and the spare column selection line CSLR12 is selectively driven.
[0094]
FIG. 6 shows another specific circuit configuration of the main body memory cell array and its peripheral circuits of the DRAM shown in FIG. Note that portions corresponding to those in FIG. 3 are denoted by the same reference numerals and description thereof is omitted, and only portions different from FIG.
[0095]
In the case of FIG. 3, the gates of the transfer gates Q11, Q12, Q21, and Q22 are connected to the column selection line CSL11. However, in the case of FIG. 6, these gates are connected to the column selection line CSL21.
[0096]
Further, in the case of FIG. 3, the transfer gates Q31, Q32, Q41, Q42 are connected between the bit line pair BL3, / BL3, BL4, / BL4 and the DQ lines DQ2, / DQ2, DQ3, / DQ3, The gate was connected to the column selection line CSL12. However, in the case of FIG. 6, the transfer gates Q31, Q32, Q41, and Q42 are connected between the bit line pairs BL3, / BL3, BL4, / BL4 and the DQ lines DQ0, / DQ0, DQ1, / DQ1, Each gate is connected to a column selection line CSL11.
[0097]
Further, in the case of FIG. 3, the transfer gates Q51, Q52, Q61, Q62 are connected between the bit line pairs BL5, / BL5, BL6, / BL6 and the DQ lines DQ0, / DQ0, DQ1, / DQ1, The gate was connected to the column selection line CSL21. However, in the case of FIG. 6, the transfer gates Q51, Q52, Q61, Q62 are connected between the bit line pairs BL5, / BL5, BL6, / BL6 and the DQ lines DQ2, / DQ2, DQ3, / DQ3, Each gate is connected to a column selection line CSL12.
[0098]
In FIG. 6, between the column selection lines CSL21 and CSL22 that are simultaneously selected and driven by the CSL driver group 17, the column selection lines CSL11 and CSL12 that are simultaneously selected and driven by the CSL driver group 17 are arranged adjacent to each other. The column selection lines CSL11 and CSL12 are adjacent to the column selection lines CSL21 and CSL22 that are not selected when each is selected.
[0099]
That is, a plurality of column selection lines are arranged so that non-selected column selection lines that are not selectively driven by the CSL driver group 17 are adjacent to the selected column selection lines that are simultaneously selected and driven by the CSL driver group 17.
[0100]
Here, consider the layout of the transfer gate in which the column selection line is connected to the gate. Generally, a transfer gate is arranged for each bit line pair adjacent to the sense amplifier. Therefore, the transfer gate must be arranged according to the arrangement pitch of the memory cells, like the sense amplifier. For this reason, the size in the direction perpendicular to the bit line is limited.
[0101]
As shown in FIG. 6, a plurality of column selection lines are arranged so that non-selected column selection lines that are not selectively driven by the CSL driver group 17 are adjacent to the selected column selection lines that are simultaneously selected and driven by the CSL driver group 17. Then, the source / drain diffusion layers of the transfer gates Q11 and Q42, Q12 and Q41, Q21 and Q32, and Q22 and Q31 can be made common, and the contacts connecting these diffusion layers and the DQ line are made common. Can be
[0102]
Accordingly, efficient layout arrangement is possible, and arrangement in the bit line vertical direction is facilitated. In addition, since the number of diffusion layers connected to the DQ line via the contacts is halved, the diffusion capacity of the DQ line capacity is halved. This makes it possible to reduce power consumption and speed, reduce the size of transistors in a circuit such as a write buffer that drives a DQ line, and the like.
[0103]
FIG. 7 shows an example of a pattern layout of transfer gates and DQ lines in the circuit of FIG. In the figure, reference numerals 71a to 71d denote source / drain diffusion layers of the transfer gate. Reference numerals 72a, 72b, and 72c are wiring layers that are made of, for example, polysilicon or metal and serve as gate electrodes of the transfer gate. Reference numerals 72d to 72f denote wiring layers in the same layer as the wiring layers 72a, 72b, and 72c. 73a to 73h are wiring layers one layer above the wiring layers 72a to 72f, and constitute the bit line pairs BL0, / BL0. Further, 74a to 74d are wiring layers one layer above the wiring layers 73a to 73h, and constitute the DQ line pairs DQ0, / DQ0.
[0104]
Here, the wiring layer 72d is connected to the underlying source / drain diffusion layer 71a via a contact 75a, and this wiring layer 72d is connected to the wiring layer 74b constituting the DQ line / DQ0 via a via 76a. Has been. That is, two transfer gates (Q12, Q41) are formed in the vertical direction across the contact 75a, and the contact portion between the two transfer gates and the DQ line / DQ0 is shared. Similarly, 75b, 75c, and 75d are contacts, and 76b, 76c, and 76d are vias.
[0105]
If the pattern layout as shown in FIG. 7 is adopted, the transfer gate and the DQ line are connected as compared with the case where the source / drain diffusion layer of each transfer gate is provided with a unique contact portion and connected to the DQ line. The number of contact portions to be reduced can be halved, and the degree of integration can be increased.
[0106]
FIG. 8 shows another specific circuit configuration of the main body memory cell array and its peripheral circuits of the DRAM shown in FIG.
The circuit shown in FIG. 8 is different from that shown in FIG. 6 in that the column selection lines CSL11 and CSL12 are connected between the column selection lines CSL11 and CSL12 that are simultaneously selected and driven by the CSL driver group 17. A column selection line CSL21 that is not selected when it is selected is arranged, and the column selection lines CSL21 and CSL22 are selected between the column selection lines CSL21 and CSL22 that are simultaneously selected and driven by the CSL driver group 17. The column selection line CSL12 which is not selected when being selected is arranged.
[0107]
That is, a plurality of column selection lines are arranged on both sides of the selected column selection lines that are simultaneously selected and driven by the CSL driver group 1717 so that non-selected column selection lines that are not selectively driven by the CSL driver group 17 are adjacent to each other.
[0108]
Also in this case, the source / drain diffusion layers of the transfer gates Q11 and Q42, Q12 and Q41, Q21 and Q32, Q22 and Q31, Q51 and Q82, Q52 and Q81, Q61 and Q72, and Q62 and Q71 are shared. Since each can be connected to the DQ line via a common contact portion, the degree of integration can be increased for the same reason as in FIG.
[0109]
FIG. 9 shows the main memory cell array and its peripheral circuit of the DRAM shown in FIG. 8 together with the spare memory cell array and its peripheral circuit.
Here, only the configuration on the spare side will be described. MCR11, MCR12 to MCR41, MCR42... Are spare memory cells, BLR1, / BLR1,... BLR4, / BLR4. Are connected to spare bit line pairs BLR1, / BLR1,... BLR4, / BLR4, and sense amplifiers for sensing data read to these spare bit line pairs, and QR11, QR12,. Transfer gate for controlling connection of spare bit line pairs BLR1, / BLR1,... BLR4, / BLR4... After data is sensed by SAR1,. , CSLR11, CSLR12, CSLR21 CSLR22 ... is a spare column select lines, respectively.
[0110]
The two transfer gates QR11 and QR12 are connected between the spare bit line pair BLR1 and / BLR1 and the DQ line pair DQ0 and / DQ0, and each gate is commonly connected to the spare column selection line CSLR11. Yes.
[0111]
The two transfer gates QR21 and QR22 are connected between the spare bit line pair BLR2 and / BLR2 and the DQ line pair DQ1 and / DQ1, and each gate is commonly connected to the spare column selection line CSLR11. Yes.
[0112]
The two transfer gates QR31 and QR32 are connected between the spare bit line pair BLR1 and / BLR1 and the DQ line pair DQ2 and / DQ2, and each gate is commonly connected to the spare column selection line CSLR12. Yes.
[0113]
The two transfer gates QR41 and QR42 are connected between the spare bit line pair BLR2 and / BLR2 and the DQ line pair DQ3 and / DQ3, and each gate is commonly connected to the spare column selection line CSLR12. Yes.
[0114]
The two transfer gates QR51 and QR52 are connected between the spare bit line pair BLR3 and / BLR3 and the DQ line pair DQ0 and / DQ0, and each gate is connected in common to the spare column selection line CSLR21. Yes.
[0115]
The two transfer gates QR61 and QR62 are connected between the spare bit line pair BLR4 and / BLR4 and the DQ line pair DQ1 and / DQ1, and each gate is commonly connected to the spare column selection line CSLR12. Yes.
[0116]
The two transfer gates QR71, QR72 are connected between the spare bit line pair BLR2, / BLR2 and the DQ line pair DQ2, / DQ2, and each gate is connected in common to the spare column selection line CSLR21. Yes.
[0117]
The two transfer gates QR81 and QR82 are connected between the spare bit line pair BLR2 and / BLR2 and the DQ line pair DQ3 and / DQ3, and each gate is commonly connected to the spare column selection line CSLR21. Yes.
[0118]
In such a configuration, the spare column selection lines CSLR11 and CSLR21 are selectively driven by the output of the spare CSL driver group 18 instead of the four column selection lines CSL11, CSL12, CSL21, and CSL22, so that the internal memory cell array MC81, MC12,..., MC81, MC82... Are replaced with spare cells MCR11, MCR12,.
[0119]
FIG. 10 shows a waveform diagram when the column selection lines CSL11 and CSL12 are selected and driven simultaneously when the memory cells in the main body memory cell array in FIG. 9 are normal. Here, the numbers in parentheses attached to the end of each of the column address signals Y Addr. A, Y Addr. B, and Y Addr. C indicate the bit positions of the respective address signals. That is, when the column address signals Y Addr.A (0), Y Addr.B (0), and Y Addr.C (0) all become H level, the column selection lines CSL11 and CSL12 both become H level, Selection lines CSL11 and CSL12 are selectively driven at the same time.
[0120]
FIG. 11 shows waveforms when the spare column selection line CSLR11 is driven in place of the column selection line CSL11 when a defect exists in the memory cell related to the column selection line CSL11 in the main body memory cell array in FIG. The figure is shown. Here, the number in parentheses at the end of the defective column address signal Spare Select Addr. Indicates the bit position of the address signal.
[0121]
Needless to say, the present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above embodiment, a case has been described in which a column selection line is provided independently for each half of the number of DQ line pairs and replaced with a spare memory cell. This is one of the number of DQ line pairs. A column selection line may be provided independently for each bit line pair of / m (m is an integer of 2 or more) and replaced with a spare memory cell.
[0122]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a semiconductor memory device capable of improving the remedy efficiency of defective products without increasing the number of spare memory cells.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing an internal configuration of part of a DRAM according to the present invention;
2 is a diagram showing a pattern layout of the entire DRAM chip of FIG. 1 and a part thereof.
FIG. 3 is a circuit diagram showing a specific configuration of a main body memory cell array and its peripheral circuits of the DRAM shown in FIG. 1;
4 is a circuit diagram showing a specific configuration of a spare memory cell array of DRAM and its peripheral circuit shown in FIG. 1;
5 is a circuit diagram showing an example of a specific configuration of the CSL driver in FIG. 3 and the spare CSL driver in FIG. 4;
6 is a circuit diagram showing another specific configuration of the main body memory cell array and its peripheral circuits of the DRAM shown in FIG. 1;
7 is a diagram showing a pattern layout of transfer gates and DQ lines in FIG. 6;
FIG. 8 is a circuit diagram showing still another specific configuration of the main body side memory cell array and its peripheral circuits of the DRAM shown in FIG. 1;
9 is a circuit diagram showing the main body memory cell array and its peripheral circuits of the DRAM shown in FIG. 8 together with a spare memory cell array and its peripheral circuits. FIG.
10 is a waveform diagram showing an example of the operation of the circuit of FIG.
11 is a waveform diagram showing an example of the operation of the circuit of FIG.
FIG. 12 is a circuit diagram showing a main memory cell array of a conventional DRAM and its peripheral circuit together with a spare memory cell array and its peripheral circuit.
[Explanation of symbols]
10: Address input pin,
11: Column address buffer,
12 ... Column address strobe signal input pin,
13 ... / CAS buffer,
14: Column partial decoder,
15 ... Column decoder controller,
16: Spare column address comparison circuit,
17 ... CSL driver group,
18 ... Spare CSL driver group,
19 ... Main body memory cell array,
20 ... spare memory cell array,
21 ... Memory cell array,
22 ... sense amplifier (S / A) group,
WL, WL1, WL2 ... word lines,
CSL, CSL11, CSL12, CSL21, CSL22 ... column selection line,
MC11, MC12, MC21, MC22, MC31, MC32, MC41, MC42, MC51, MC52, MC61, MC62, MC71, MC72, MC81, MC82 ... memory cells,
BL1, / BL1 to BL4, / BL4... Bit line pairs,
SA1 to SA4, SAR1, SAR2 ... sense amplifier,
DQ0, / DQ0 to DQ3, / DQ3 ... DQ line pairs,
Q11, Q12, Q21, Q22, Q31, Q32, Q41, Q42, Q51, Q52, Q61, Q62, Q71, Q72, Q81, Q82 ... transfer gate,
MCR11, MCR12, MCR21, MCR22, MCR31, MCR32, MCR41, MCR42 ... spare memory cells,
BLR1, / BLR1, BLR2, / BLR2 ... spare bit line pairs,
CSLR11, CSLR12, CSLR21, CSLR22... Spare column selection line.

Claims (20)

A plurality of memory cells;
A plurality of bit lines connected to the plurality of memory cells;
A plurality of word lines connected to the plurality of memory cells;
Multiple data lines,
A plurality of transfer gates for controlling connection of the plurality of bit lines to any of the plurality of data lines;
A plurality of column selection lines for controlling conduction of the plurality of transfer gates;
And a column selection line driving circuit that simultaneously selects and drives at least two of the plurality of column selection lines in response to one column address input from the outside of the chip.   2. The semiconductor according to claim 1, wherein the column selection line driving circuit is configured to simultaneously select and drive two column selection lines in response to one column address input from the outside of the chip. Storage device.   The plurality of column selection lines are arranged so that non-selected column selection lines that are not selectively driven by the column selection line driving circuit are adjacent to the selected column selection lines that are simultaneously selected and driven by the column selection line driving circuit. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device.   The plurality of column selection lines are arranged such that two non-selected column selection lines that are not selectively driven by the column selection line driving circuit are adjacent to both sides of each of the selected column selection lines that are selectively driven by the column selection line driving circuit. 3. The semiconductor memory device according to claim 1, wherein a line is disposed. Each of the plurality of transfer gates has a source / drain diffusion layer formed in a semiconductor substrate, and the source / drain diffusion layer and the plurality of data lines are connected via a contact portion,
The transfer gate controlled in conduction by a non-selected column selection line adjacent to the contact portion connecting the source / drain diffusion layer of the transfer gate controlled in conduction by the selected column selection line to the data line and the selection column selection line 5. The semiconductor memory device according to claim 3, wherein a contact portion connecting the source / drain diffusion layer to the data line is shared.   The column selection line driving circuit is provided with a number corresponding to the number of the column selection lines, and is configured by a plurality of column selection line drivers each having an output node connected to the corresponding column selection line. The semiconductor memory device according to claim 1.   Of the column selection line drivers, the same column address signal is input to at least two column selection line drivers that simultaneously select and drive the at least two column selection lines in response to one column address input. The semiconductor memory device according to claim 6. A plurality of spare memory cells;
A plurality of spare bit lines connected to the plurality of spare memory cells;
A plurality of spare column selection lines including at least first and second spare column selection lines;
A plurality of first spare transfer gates for controlling connection of the plurality of spare bit lines to the plurality of data lines by the first spare column selection line;
A plurality of second spare transfer gates for controlling connection of the plurality of spare bit lines to the plurality of data lines by the second spare column selection line;
The plurality of spare bit lines are connected to a part of the plurality of data lines via a plurality of first spare transfer gates controlled to be connected by the first spare column selection line, and the second spare column 8. The data line according to claim 1, wherein the data line is connected to another data line different from the part of the plurality of data lines via a plurality of second spare transfer gates controlled by a selection line. 2. A semiconductor memory device according to item 1. The plurality of spare bit lines are composed of at least first and second spare bit line groups;
The plurality of data lines are composed of at least first and second data line groups,
The first spare bit line group is connected to the first data line group via a plurality of first spare transfer gates controlled by the first spare column selection line, and the second spare bit 9. The semiconductor memory according to claim 8, wherein the line group is connected to the second data line group through a plurality of second spare transfer gates controlled by the second spare column selection line. apparatus. The plurality of memory cells are divided into 2 ⁿ memory cell array blocks having a capacity that is 1/2 ⁿ (n is a positive integer) times the total memory capacity, and the spare memory is divided into each memory cell array block. 10. The semiconductor memory device according to claim 8, wherein cells are respectively arranged. A plurality of memory cells;
A plurality of bit line pairs connected to the plurality of memory cells;
A plurality of word lines connected to the plurality of memory cells;
Multiple data line pairs,
A plurality of transfer gates connected between the plurality of bit line pairs and the plurality of data line pairs;
A first column select line for controlling conduction of a plurality of first transfer gates connected to half of the plurality of data line pairs;
A second column selection line for controlling conduction of a plurality of second transfer gates connected to the remaining half of the plurality of data line pairs;
And a column selection line driving circuit for simultaneously selecting and driving the first and second column selection lines in response to one column address input from the outside of the chip. A plurality of spare memory cells;
A plurality of spare bit line pairs connected to the plurality of spare memory cells;
First and second spare column selection lines;
A plurality of first spare transfer gates for controlling connection of the plurality of spare bit line pairs to the plurality of data line pairs by the first spare column selection line;
A plurality of second spare transfer gates for controlling connection of the plurality of spare bit line pairs to the plurality of data line pairs by the second spare column selection line;
The plurality of spare bit lines are connected to a part of the plurality of data line pairs via a plurality of first spare transfer gates controlled to be connected by the first spare column selection line, and the second spare bit lines 12. The data line pair according to claim 11, wherein the data line pair is connected to another data line pair different from the part of the plurality of data line pairs via a plurality of second spare transfer gates controlled to be connected by a column selection line. The semiconductor memory device described. A plurality of memory cells;
A plurality of bit lines consisting of a first bit line group and a second bit line group and connected to the memory cells;
A plurality of word lines connected to the plurality of memory cells;
A plurality of data lines composed of a first data line group and a second data line group;
A first transfer gate group provided between the first bit line group and the first data line group;
A second transfer gate group provided between the second bit line group and the second data line group;
A first column select line connected to the first transfer gate group;
A second column selection line connected to the second transfer gate group;
A first column selection line driver corresponding to the first column selection line; and a second column selection line driver corresponding to the second column selection line, the first and second column selection lines. A semiconductor memory device comprising: a column selection line driving circuit to which a common column address signal is supplied to a driver. A third column selection line disposed adjacent to the first column selection line and not selected simultaneously with the first and second column selection lines;
And a fourth column selection line arranged adjacent to the second column selection line and not selected simultaneously with the first and second column selection lines. 14. The semiconductor memory device according to 13.   5. A fifth column selection line that is disposed between the first and second column selection lines and is not selected simultaneously with the first and second column selection lines. Item 14. A semiconductor memory device according to Item 13. A third transfer gate group connected to the third column selection line;
A fourth transfer gate group connected to the fourth column selection line,
Each of the first transfer gate groups has a first source / drain diffusion layer;
Each of the second transfer gate groups has a second source / drain diffusion layer,
Each of the third transfer gate groups shares a first source / drain diffusion layer with the first transfer gate group,
15. The semiconductor memory device according to claim 14, wherein each of the fourth transfer gate groups shares a second source / drain diffusion layer with the second transfer gate group.   The output of the first column selection line driver and the output of the second column selection line driver are simultaneously activated corresponding to one column address input, whereby the first and second column selections are performed. 14. The semiconductor memory device according to claim 13, wherein the lines are selectively driven simultaneously. A plurality of spare memory cells;
A plurality of spare bit lines connected to the plurality of spare memory cells;
A first spare transfer gate group provided between the plurality of spare bit lines and the first data line group;
A second spare transfer gate group provided between the plurality of spare bit lines and the second data line group;
A first spare column selection line connected to the first spare transfer gate group;
A second spare column selection line connected to the second spare transfer gate group,
The plurality of spare bit lines are connected to the first data line group via the first spare transfer gate group controlled to be connected by the first spare column selection line, and the second spare column selection is performed. claim 1 3 Symbol mounting of the semiconductor memory device is characterized in that through the second spare transfer gate group connected controlled by line is connected to the second data line group. The plurality of memory cells are divided into 2 ⁿ memory cell array blocks having a capacity that is 1/2 ⁿ (n is a positive integer) times the total memory capacity, and the spare memory is divided into each memory cell array block. 19. The semiconductor memory device according to claim 18 , wherein each cell is arranged.   14. The semiconductor memory according to claim 13, wherein the plurality of bit lines are composed of a pair of bit lines, and each of the first and second data line groups is composed of a pair of data lines. apparatus.

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