JP2002140895A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which can transfer data at high speed. SOLUTION: A semiconductor memory 1000 is provided with a memory cell array MA, a pair of normal data line, a pair of redundant data line, and a data line switching circuit 105. The data line switching circuit 105 comprises an IO shift decoder 108 decoding a column address and position information about a defective data line and an IO selecting section 107 shifting connection between a data input/output pin and a data line replacing a defective data line in accordance with a decoding result. High speed data transfer is realized by performing simultaneously data line selection and redundancy selection based on a column address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundant configuration.

[0002]

2. Description of the Related Art A conventional semiconductor memory device has a redundant memory cell for replacing a defective memory cell in order to rescue the defective memory cell and improve the yield.

In recent years, a wide bus width has been strongly demanded in order to improve a data transfer speed, and a column address tends to become relatively smaller as a data line width becomes larger. In particular, a dynamic random access memory (DR) embedded in a logic circuit aiming at a system-on-chip
AM), it is required that the bus width be changed from 32 bits to 256 bits and the column address be changed from 256 bits to 16 bits.

In a conventional semiconductor memory device, a defective memory cell is relieved by replacing a bit line with a column address. However, when the column address is small, a high remedy rate cannot be expected unless relatively many redundant memory cells are prepared.

For this reason, in recent years, a method of arranging redundant memory cells and redundant data lines connected to the redundant memory cells and replacing defective data lines with redundant data lines has begun to be adopted.

In a logic-embedded DRAM (Dynamic Random Access Memory), the internal bus width is widened so as to be compatible with various bus widths, and the bus width is adjusted to the required bus width in connection with the outside. And a method of selecting using a column address.

Here, an example of a conventional semiconductor memory device 5000 having a redundant configuration will be described with reference to FIG. The semiconductor memory device 5000 receives a memory cell array 500 including a plurality of memory cells arranged in a matrix, a plurality of normal data line pairs 501 connected to the memory cells via sense amplifiers, and a redundant data line pair 502. A row decoder 510 for decoding a row address and selecting in a row direction, a column address decoder 511 for decoding and outputting an input column address, a shift redundancy circuit 512 having position information of a defective data line, and selecting a data line An IO selection circuit 503, a read amplifier / write driver unit 504, and an IO shift circuit 505.

The IO selection circuit 503 selects a data line pair to be used based on the output of the column address decoder 511. Referring to FIG. 65, IO selection circuit 503 includes a plurality of switches. Normal data line pair LIO
(0), / LIO (0),... Are connected to the read amplifier / write driver unit 504, and the redundant data line pair SLIO (0), / SLIO (0) or SLIO is connected.
One of (1) and SLIO (1) is connected to the read amplifier / write driver unit 504.

Read amplifier / write driver section 504
Includes a plurality of read amplifier / write drivers RW (read amplifier R, write driver W). Lead amplifier
By the write driver unit 504, the data of the selected data line pair is transmitted to the internal data lines DB (0),.
, And the data on the redundant internal data line SDB are transmitted to the selected data line pair.

In the IO shift circuit 505, as shown in FIG. 66, the connection between the internal data line and the data input / output pin (external data line) is shifted based on the data line shift method so as to remove the defective data line. . More specifically, the defective data line is replaced with an adjacent data line, and the data line used for the replacement is further replaced with an adjacent data line. By repeating such replacement between adjacent data lines, the last data line is replaced with a redundant data line. As a result, data lines other than the defective data line are connected to the data input / output pins (external data lines) DQ (0) to DQ (n).

In this way, the data of the selected memory cell is output to the outside. During a write operation, data is written to the selected memory cell by the reverse route.

[0012]

However, in such a configuration of the conventional semiconductor memory device, data passes through a switching circuit for switching a data line and a switching circuit for a data line for redundancy replacement. Is delayed.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor memory device capable of performing high-speed data transfer in a semiconductor memory device having a redundant configuration. It is in.

[0014]

According to one aspect of the present invention, a semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in a matrix, and a redundant data line.
A plurality of data lines for reading or writing data from the memory cell array, a plurality of external data lines for exchanging data with the outside, a defective data line included in the external address and the plurality of data lines A data line for simultaneously executing a selection operation of selecting a data line to be coupled to a plurality of external data lines and a shift operation of shifting a connection to a data line to be coupled to the plurality of external data lines in accordance with storage information related to the data line A switching circuit.

Preferably, the plurality of data lines are divided into a plurality of blocks, and the data line switching circuit includes a decoder for decoding an external address and storage information, and a decoder for each of the plurality of blocks and the plurality of external data lines. And a plurality of selection circuits arranged therebetween. Each of the plurality of selection circuits simultaneously performs a selection operation and a shift operation according to the output of the decoder. Each of the plurality of selection circuits shares some data lines with the selection circuits adjacent to each other.

In particular, each of the plurality of selection circuits includes a plurality of transfer gates provided between the corresponding data line and the corresponding external data line, and opened and closed according to the output of the decoder.

A semiconductor memory device according to a further aspect of the present invention includes a memory cell array including a plurality of memory cells arranged in a matrix, and a redundant data line for reading data from or writing data to the memory cell array. A plurality of data lines, and a selection operation of selecting a data line to be coupled to the plurality of external data lines according to an external address;
A data line switching circuit that simultaneously performs a replacement operation for replacing a defective data line included in a data line to be combined with a redundant data line in accordance with the replacement information.

Preferably, the plurality of data lines further include a plurality of normal data lines, and the plurality of normal data lines are divided into a plurality of blocks. The data line switching circuit includes a decoder for decoding an external address and replacement information, and a plurality of selection circuits disposed between each of the plurality of blocks and the plurality of external data lines. Each of the plurality of selecting circuits simultaneously performs the selecting operation and the replacing operation on the redundant data line and the corresponding normal data line.

In particular, each of the plurality of selection circuits includes a plurality of transfer gates provided between the redundant data line and the corresponding normal data line and the corresponding external data line, and opened and closed according to the output of the decoder.

A semiconductor memory device according to a further aspect of the present invention includes a memory cell array including a plurality of memory cells arranged in a matrix and a redundant data line for reading data from or writing data to the memory cell array. A plurality of data lines, a selection operation for selecting a data line to be coupled to an external data line to be used in accordance with a bus width, and an external device to be used in accordance with storage information relating to a defective data line included in the plurality of data lines. A data line switching circuit for simultaneously executing a shift operation for shifting a connection between the data line and the data line coupled thereto.

Preferably, each of the plurality of data lines and the plurality of external data lines is divided into a plurality of blocks, and the plurality of blocks share some of the data lines with adjacent blocks. The switching circuit includes a plurality of switching circuits arranged corresponding to each of the plurality of blocks. Each of the plurality of switching circuits is a mode for switching a connection between a corresponding data line and a corresponding external data line according to the bus width, replacing a defective data line with a shared data line, and responding according to the bus width. The mode belongs to either a mode in which the connection between the external data line and the corresponding data line is shifted or a mode in which the connection between the corresponding data line and the corresponding external data line is shifted according to the bus width.

In particular, each of the plurality of switching circuits includes m nodes, a first gate for selectively switching the connection between the m nodes and the m external data lines according to the bus width,
A second gate for disconnecting the defective data line from the m nodes based on the bus width and the replacement information; and a second data gate among the shared data line and the m nodes based on the bus width and the replacement information. And a third gate selectively connecting one of them.

A semiconductor memory device according to a further aspect of the present invention includes a memory cell array including a plurality of memory cells arranged in a matrix, and first and second redundant data lines and a plurality of normal data lines. A plurality of data lines for reading data from or writing data to, and a plurality of external data lines provided for the plurality of normal data lines, respectively, for transmitting and receiving data to and from the outside, and a bus width. A selection operation for selecting a data line to be coupled to an external data line to be used, and a data line to be coupled to an external data line to be used, according to storage information on defective data lines included in the plurality of data lines. A data line switching circuit for simultaneously executing a shift operation for shifting a connection.

Preferably, the first and second redundant data lines are respectively arranged outside the plurality of normal data lines. The plurality of data lines are arranged in the order of a first redundant data line, each of a plurality of normal data lines, and a second redundant data line, and the plurality of external data lines are divided into a plurality of blocks each of n pieces, The plurality of data lines correspond to the plurality of blocks, respectively, and are arranged in order such that two normal data lines are shared between adjacent blocks (n
+2) Divided into books. The data line switching circuit includes a plurality of switching circuits arranged corresponding to each of the plurality of blocks. Each of the plurality of switching circuits has a first mode in which a defective data line is absent in a corresponding block, and switches a connection between a corresponding normal data line and a corresponding external data line in accordance with a bus width, and a corresponding block. A second mode in which a defective data line is absent in the first mode and the connection between the corresponding external data line and the corresponding data line is shifted toward the first redundant data line according to the bus width.
A third mode in which the defective data line is absent in the corresponding block and the connection between the corresponding external data line and the corresponding data line is shifted toward the second redundant data line according to the bus width, the corresponding block And one of the first redundant data line and the data line shared with the block adjacent to the first redundant data line side of the corresponding (n + 2) data lines, including one defective data line In the fourth mode in which one defective data line is replaced by using and the connection between the corresponding external data line and the corresponding data line is shifted in accordance with the bus width. And the corresponding (n + 2)
One defective data line is replaced by using one of the data line shared with the block adjacent to the second redundant data line side of the two data lines and the second redundant data line, and A fifth mode in which the connection between the corresponding external data line and the corresponding data line is shifted in accordance with the width, and a corresponding block including two defective data lines and among the corresponding (n + 2) data lines , A data line shared between a block adjacent to the first redundant data line side and a data line shared between one of the first redundant data lines and a block adjacent to the second redundant data line side A sixth mode for replacing one defective data line using one of the data line and one of the second redundant data lines and shifting the connection between the corresponding external data line and the corresponding data line according to the bus width. Belonging to one of any of the.

In particular, each of the plurality of switching circuits includes n nodes, and a switch unit for selectively switching the connection between the n nodes and the n external data lines according to the bus width.
Based on the bus width, the replacement information, and the mode to which the corresponding block belongs, the defective data line is disconnected from the n nodes, and n out of the corresponding (n + 2) data lines
And a selection unit for connecting each of the book and the n nodes.

Preferably, in the test mode, each of the plurality of switching circuits is forcibly set to one of the second mode and the third mode which can be switched from the outside.

Preferably, in the test mode, one of the plurality of switching circuits corresponding to the first redundant data line and one corresponding to the second redundant data line are connected to the fourth redundant circuit.
And the fifth mode are forcibly set respectively.

Preferably, in the test mode, each of the plurality of switching circuits is forcibly set to the first mode.

Preferably, each of the plurality of external data lines and the plurality of normal data lines is divided into a plurality of blocks. The data line switching circuit includes a plurality of switching circuits arranged corresponding to the plurality of blocks, respectively. Each of the plurality of switching circuits has a first mode in which a defective data line is absent in a corresponding block, and switches a connection between a corresponding normal data line and a corresponding external data line in accordance with a bus width, and a corresponding block. In the second mode, one defective data line is replaced, and one defective data is replaced by a shift operation using the first redundant data line. In the second mode, one defective data line is included in a corresponding block. 1 by the shift operation using the redundant data line
And a third mode for replacing defective data and a shift operation using the first and second redundant data lines including two defective data lines in a corresponding block.
Any one of the fourth modes for replacing defective data in a book
Belong to one.

In particular, each of the plurality of switching circuits includes n nodes and a switch unit for selectively switching the connection between the n nodes and the n external data lines according to the bus width.
Based on the bus width, the replacement information, and the mode to which the corresponding block belongs, the defective data line is disconnected from the n nodes and the corresponding n normal data lines, the first and second redundant data lines are connected. And a selection unit for connecting each of the n nodes and the n nodes.

Preferably, in the test mode, two of the plurality of switching circuits are forcibly set to the second and third modes, respectively.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings. In the figure,
The same or corresponding parts have the same reference characters allotted, and description thereof will not be repeated.

[First Embodiment] A semiconductor memory device according to a first embodiment will be described. Referring to FIG. 1, a semiconductor memory device 1000 according to the first embodiment
Is a memory cell array MA including a plurality of memory cells arranged in a matrix, a plurality of word lines corresponding to rows and a plurality of bit lines corresponding to columns, a normal data line connected to the memory cells via a sense amplifier. A pair 101, a redundant data line pair 102, a row decoder 103 that decodes an input row address RAD and performs word line selection / activation of a sense amplifier (selection in a row direction) and the like, and decodes an input column address CADd. And column address C
Column address decoder 10 that outputs AD and / CAD
4, a data line switching circuit 105 and a defective data line storage circuit 106 are provided.

The defective data line storage circuit 106 has a configuration for identifying a defective data line. Bad data line storage circuit 1
In the case where a fuse is used as an example of the fuse 06, a defective data line identification signal FS <n: 0> (= FS (0)) indicating the existence and position of the defective data line according to whether the fuse is cut or not cut.
To FS (n)). Note that the components of the defective data line storage circuit 106 are not limited to the fuses whose states change according to disconnection / non-disconnection.

The data line switching circuit 105 includes the IO selection unit 1
07, an IO shift decoder 108, and a read amplifier / write driver unit 109 (IO: Input Outpu
t). IO selecting section 107 outputs defective data line identification signal FS.
(0) to FS (n) and column address CAD, /
The data line pair to be used is selected based on the output (selection signal SEL) of the IO shift decoder 108 that receives the CAD. The selected data line pair is electrically coupled to the read amplifier / write driver RW included in the read amplifier / write driver unit 109.

Referring to FIG. 2, LIO (i), / LIO
(I) shows the normal data line pair as SLIO (k), /
SLIO (k) represents a redundant data line pair (i = 0 to 2n + 1, k = 0, 1).

Of the (2n + 2) data line pairs, (n + 2)
1) The IO selection unit 107 selects (n + 1) pairs of main data line pairs MIO (j) and / MIO (j) (j = 0
To n).

The IO selection section 107 is a quarter selection circuit X0 to Xn, Y0 to Y for selecting one of the four data lines.
n. 1/4 selection circuits X0 to Xn are arranged corresponding to normal data lines LIO (k) (k = 0 to 2n + 1) and redundant data lines SLIO (0), SLIO (1), and 1/4 selection circuits Y0. To Yn are normal data lines /
LIO (k) (k = 0 to 2n + 1) and redundant data lines / SLIO (0) and / SLIO (1) are arranged.

As will be described later, the 1/4 selection circuit X
Each of 0 to Xn and Y0 to Yn has the same configuration.

The 1/4 selection circuit Xi (i = 0 to n) receives the column addresses CAD and / CAD and the shift decoder SXi receiving the defective data line identification signal FS (i).
, One of the four data lines is selectively connected to one main data line MIO (i).

The 1/4 selection circuit Yi (i = 0 to n) receives the column addresses CAD and / CAD and the shift decoder SYi receiving the defective data line identification signal FS (i).
, One of the four data lines and one main data line / MIO (i) are selectively connected based on the selection signal output from the.

More specifically, the 1/4 selection circuit X0 connects one of the normal data lines LIO (0) to LIO (3) to the main data line MIO (0), and Xk indicates normal data lines LIO (2k) to LIO
One of (2k + 3) is connected to main data line MIO
(K) (k = 1 to n-1). And 1/4
The selection circuit Xn includes normal data lines LIO (2n), L
IO (2n + 1) and redundant data lines SLIO (0),
One of SLIO (1) is connected to main data line MIO
(N). The same rules as those of the quarter selection circuits X0 to Xn are also applied to the quarter selection circuits Y0 to Yn.

The shift decoders SXi and SYi are included in the IO shift decoder 108. Note that the shift decoder SYi is deleted, and the output of the shift decoder SXi is reduced to 1 /
The four selection circuits Xi and Yi may be shared.

Read amplifier / write driver section 109
Are read amplifiers R0 to Rn and write driver W0
To Wn. During a read operation, read amplifier Ri differentially amplifies the potential of main data line pair MIO (i), / MIO (i) and outputs the amplified data to data input / output pin DQ (i) (external data line DQ (i)). (I = 0 to n). At the time of write operation,
Data input / output pin DQ (i) (external data line DQ
According to the data of (i), the write driver Wi drives the potential of the main data line pair MIO (i), / MIO (i) (i = 0 to n).

FIG. 3 shows the relationship between the 1/4 selection circuit and the shift decoder. The 選 択 selection circuit Xj shown in FIG. 3 includes transfer gates 110 to 113. In FIG. 3, transfer gates 110 to 113 are connected to normal data lines LIO (i-3) to LIO (i) and main data line MI
O.

When select signals SEL (0) to SEL (3) attain an H level, each of transfer gates 110 to 113 connects the corresponding data line to the main data line. The main data line MIO is connected to the read amplifier / write driver unit 109 shown in FIG.

The potentials of the selection signals SEL (0) to SEL (3) are determined by the shift decoder SX receiving the defective data line identification signal FS (j) and the column addresses CAD and / CAD.
j.

The operation of shift decoders SXi and SYi will be described with reference to FIG. In FIG. 4, the symbol "1" indicates an H level, and "0" indicates an L level.

If FS (i) = 0, SEL (0) = 1 or SEL (1) = 1 according to the column address. If FS (i) = 1, SEL (2) = 1 or SEL (3) = 1 depending on the column address.

An example of the relationship between the defective data line identification signal FS (i) and the defective data line will be described with reference to FIG. In FIG. 5, the symbol “1” indicates the H level, and “0” indicates the L level.
Indicates a level. Normal data line pair LIO (2
k), / LIO (2k) or LIO (2k + 1), /
When LIO (2k + 1) is defective, the defective data line identification signals FS (k) to FS (n) are set to "1" (shift executed), and the others are set to "0" (no shift).

When the normal data line LIO (3) is defective, the signal input to each 1/4 selection circuit is as shown in FIG.
Satisfy the relationship. If the normal data line pair LIO (3) is defective, the defective data line identification signals FS (1) to FS
(N) becomes “1” and FS (0) becomes “0”.

In the 1/4 selection circuits X0 and Y0, the selection signal SEL (0) or SEL (1) becomes "1" and the selection signals SEL (2) and SEL (3) become "0". Meanwhile, 1
In the / 4 selection circuits Xk and Yk, the selection signals SEL (0),
SEL (1) becomes “0” and the selection signal SEL (2) or SEL (3) becomes “1” (k = 1 to n).

The selection status of the data lines will be described with reference to specific examples. Normal data line pair LIO (5), / LIO
(5) is defective and is not used. In this case, the defective data line identification signal FS (i) (i = 0, 1) is at L level and F
S (j) (j = 2 to n) is at the H level.

1/4 selection circuits X0, X1, Y0, Y1
Receive the L-level defective data line identification signal, and the 選 択 selection circuits Xj and Yj (j = 2 to n) receive the H-level defective data line identification signal.

Therefore, the 1/4 selection circuit X0 is connected to the normal data line LIO designated by the column address CAD.
Select either (0) or LIO (1).
The 選 択 selection circuit Y0 is connected to the normal data line / LIO (0) or / LIO designated by the column address CAD.
Select any one of (1). 1/4 selection circuit X1
Selects one of the normal data lines LIO (2) and LIO (3) specified by the column address CAD. The 選 択 selection circuit Y1 has a column address CAD
Normal data line / LIO (2) or /
Select one of LIO (3).

The 1/4 selection circuit X2 has a column address C
One of LIO (6) and LIO (7) specified by AD is selected. The 1/4 selection circuit Y1 outputs / LIO (6) or / L specified by the column address CAD.
Select one of the IOs (7). Therefore, normal data line pair LIO (5), / LIO (5) is not selected.

Thereafter, the 1/4 selection circuit Xk (k = 3 to n-
In 1), one of the normal data lines LIO (2k + 2) or LIO (2k + 3) is selected, and
In the selection circuit Yk (k = 3 to n-1), one of the normal data lines / LIO (2k + 2) or / LIO (2k + 3) is selected.

In the 1/4 selection circuit Xn, one of the redundant data lines SLIO (0) and SLIO (1) is selected, and in the 1/4 selection circuit Yn, the redundant data line / SLIO (0) or / SLIO (1) will be selected.

As described above, according to the semiconductor memory device of the first embodiment, by combining the column address and the replacement information, the replacement of the data line by the data line shift method and the selection of the data line are simultaneously executed. Therefore, high-speed data transfer is realized.

[Second Embodiment] A semiconductor memory device according to a second embodiment will be described. The second embodiment is directed to a semiconductor memory device that performs redundancy replacement by a data line replacement method as an improved example of the first embodiment.

Referring to FIG. 7, a semiconductor memory device 1500 according to the second embodiment includes a data line switching circuit 155 in place of data line switching circuit 105 and a defective data line in place of defective data line storage circuit 106. The storage circuit 156 is provided.

The defective data line storage circuit 156 stores the position information of the defective data line. Bad data line storage circuit 15
In the case where a fuse is used as an example of No. 6, a defective data line replacement signal RS <n: 0> (= RS (0) to RS) indicating replacement information of a defective data line depending on whether the fuse is cut or not cut.
(N)) is output. The defective data line storage circuit 15
The components of No. 6 are not limited to the fuses whose state changes due to disconnection / non-disconnection.

The data line switching circuit 155 is connected to the IO selector 1
57, an IO replacement decoder 158, and a read amplifier
Including the write driver unit 109 (IO: Input Outpu
t). IO selection section 157 outputs defective data line replacement signal RS
A data line pair to be used is selected based on (0) to RS (n) and an output (selection signal SEL) of IO replacement decoder 158 receiving column addresses CAD and / CAD. The selected data line pair is electrically coupled to the read amplifier / write driver RW included in the read amplifier / write driver unit 109.

Referring to FIG. 8, LIO (i), / LIO
(I) shows the normal data line pair as SLIO (k), /
SLIO (k) represents a redundant data line pair (i = 0 to 2n + 1, k = 0, 1).

Of the (2n + 2) data line pairs, (n + 2)
1) A pair of (n + 1) main data lines MIO (j) and / MIO (j) (j = 0)
To n).

The IO selection section 157 is a quarter selection circuit X0 to Xn, Y0 to Y for selecting one of the four data lines.
n. In the second embodiment, the 1/4 selection circuit Xi
(I = 0 to n) are the column addresses CAD and / CA
D and one of the four data lines and one main data line MIO based on the selection signal output from the decoder SZi receiving the defective data line replacement signal RS (i).
(I) is selectively connected. Also, the 1/4 selection circuit Y
i (i = 0 to n) is the column address CAD and / C
AD and a selection signal output from the decoder SWi receiving the defective data line replacement signal RS (i).
One of the data lines and one main data line / MI
O (i) is selectively connected.

The 1/4 selection circuit Xk connects one of the normal data lines LIO (2k) and LIO (2k + 1) and one of the redundant data lines SLIO (0) and SLIO (1) to the main data line MIO (k). Connect to (k =
0-n).

The 1/4 selection circuit Yk includes normal data lines / LIO (2k) and / LIO (2k + 1) and redundant data lines / SLIO (0) and / SLIO (1)
Are connected to the main data line / MIO (k) (k = 0 to n).

The decoders SZi and SWi are included in the IO replacement decoder 158. Note that the decoder SWi is deleted, and the output of the decoder SZi is changed to １ ／ selection circuits Xi and Yi.
And may be shared.

FIG. 9 shows the relationship between the 1/4 selection circuit and the decoder. As described above, the 選 択 selection circuit Xj includes the transfer gates 110 to 113. 1 shown in FIG.
Transfer gate 110 included in / 4 selection circuit Xj
To 113 are data lines XLIO (i-3) to XLIO
(I) and the main data line MIO. Data lines XLIO (i) and XLIO (i-1)
Of redundant data lines SLIO (0) and SLIO
IO (1) is connected to data lines XLIO (i-2) and XL
Each of the IOs (i-3) corresponds to a normal data line.

When select signals SEL (0) to SEL (3) attain an H level, each of transfer gates 110 to 113 connects the corresponding data line to the main data line.

The potentials of selection signals SEL (0) to SEL (3) are determined in decoder SZj receiving defective data line replacement signal RS (j) and column addresses CAD and / CAD.

Regarding the operation of the decoders SZi and SWi,
This will be described with reference to FIG. In FIG. 10, the symbol “1” indicates the H level, and “0” indicates the L level.

If RS (i) = 0, SEL (0) = 1 or SEL (1) = 1 according to the column address. If RS (i) = 1, SEL (2) = 1 or SEL (3) = 1 according to the column address.

An example of the relationship between the defective data line replacement signal RS (i) and the defective data line will be described with reference to FIG. In FIG. 11, the symbol “1” indicates the H level,
“0” represents the L level. Normal data line pair LIO (2k), / LIO (2k) or LIO (2k)
+1) and / LIO (2k + 1) are defective, the defective data line replacement signal RS (k) becomes "1" (perform replacement), and the others are "0" (no replacement).

When the normal data line LIO (3) is defective, the signal input to each 1/4 selection circuit is as shown in FIG.
The relationship of 2 is satisfied. If the normal data line pair LIO (3) is defective, the defective data line replacement signals RS (0), RS
(2) -RS (n) becomes “0” and RS (1) becomes “1”.

1/4 selection circuits Xk, Yk (k = 0, 2
In n), the selection signal SEL (0) or SEL (1) becomes “1”, and the selection signals SEL (2) and SEL (3) become “0”. On the other hand, in the 1/4 selection circuits X1 and Y1,
The selection signals SEL (0) and SEL (1) become “0”, and the selection signal SEL (2) or SEL (3) becomes “1”.

Therefore, in the 1/4 selection circuit X1, the redundant data line SLIO is used instead of the normal data line.
(0) or SLIO (1) is connected to the main data line MIO
It is electrically connected to (1).

In the 1/4 selection circuit Y1, instead of the normal data line, the redundant data line / SLIO (0) or /
SLIO (1) is electrically connected to main data line / MIO (1).

In the 1/4 selection circuit Xk, the normal data line and the main data line MIO are set according to the column address.
(1) is electrically connected to the 1/4 selection circuit Y.
k, the normal data line and the main data line / MIO
It becomes electrically connected to (1) (k = 0, 2-n).

As described above, according to the semiconductor memory device of the second embodiment, the replacement of the data line by the data line replacement method and the selection of the data line are simultaneously executed by combining the column address and the replacement information. Therefore, high-speed data transfer is realized.

[Third Embodiment] A semiconductor memory device according to a third embodiment will be described. In the third embodiment, the number of normal data line pairs is 32 (LIO
(I), / LIO (i); i = 0 to 31), and the number of redundant data line pairs is 1 (SLIO, / SLIO). Also,
As a data line configuration, it is possible to switch between × 32, × 16, and × 8. In the case of a × 16, × 8 configuration, a data line is selected using a column address.

Referring to FIG. 13, a semiconductor memory device 2000 according to the third embodiment includes a plurality of memory cells arranged in a matrix, a plurality of word lines corresponding to rows, and a plurality of bit lines corresponding to columns. , A normal data line pair 101 connected to a memory cell via a sense amplifier, a redundant data line pair 102, and an address RAD (x) according to a command (eg, an act command ACT / precharge command PRE). : 0) to activate a word line or a sense amplifier (row selection operation).

Semiconductor memory device 2000 further includes a read amplifier / write driver section 203 including a read amplifier / write driver RW operating according to commands READ / WRITE (write command, read command), and IO selection circuit Z.
An IO selection unit 204 including 0 to Z7, a redundancy selection signal generation circuit 206, and a data line selection signal generation circuit 207 are provided.

A plurality of read amplifiers / write drivers RW
Includes a plurality of read amplifiers / write drivers RW provided corresponding to the respective data line pairs. The data of the normal data line pair LIO (i), / LIO (i) and the redundant data line pair SLIO, / SLIO are transferred via the read amplifier / write driver unit 203 to the internal data line DB (i) and the redundant internal data, respectively. Transmitted to line SDB.

The data on the internal data line DB (i) and the redundant internal data line SDB are supplied to the normal data line pair LI via the read amplifier / write driver 203, respectively.
O (i), / LIO (i) and redundant data line pair SLI
O, / SLIO.

The IO selection section 204 selects an internal data line to be used according to the bus width (column address) and the presence or absence of redundant use. Hereinafter, the internal data lines DB (i) and the redundant internal data lines SDB will be referred to as internal data lines DB (i),
It is called SDB.

The internal data lines DB (0) to DB (31),
The SDB is divided into eight groups. Each of the internal data lines DB (4), DB (8),..., DB (28) is shared between adjacent blocks.

The IO selection circuit Zi (block i) includes an external data line to be used among the external data lines DQ (4i) to DQ (4i + 3) and internal data lines DB (4 × i) to DB
Of (4 × i + 4), an internal data line to be used is electrically coupled (i = 0 to 6). The IO selection circuit Z7 includes an external data line to be used among the external data lines DQ (28) to DQ (31) and internal data lines DB (28) to DB (3).
1) and the internal data line used in the SDB is electrically coupled. In the following, the same symbols are used for the external data lines and the data input / output pins connected to the external data lines.

The redundancy selection signal generation circuit 206 stores the position of a normal data line requiring redundancy replacement, and generates a decode signal according to the stored content. The decoded signal is called a replacement data line position signal, and its upper bit signal is
EL <7: 0> (= USEL (0) to USEL
(7)), the lower bit signal is changed to LSEL <3: 0> (= L
SEL (0) to LSEL (3)). Signal LSEL
Indicates which of the four data lines is defective,
The signal USEL indicates the presence of a defective data line for each IO selection circuit.

A fuse is used to store the position of the data line that needs to be replaced. The position information is stored by blowing (or not blowing) the fuse in accordance with the position. Note that the configuration of the redundancy selection signal generation circuit 206 is not limited to a fuse.

The data line selection signal generation circuit 207 outputs the column address CAD <1: 0> (= CAD (0), CAD
An address decode signal YSEL <3: 0> (= YSEL (0)) for selecting a data line based on (1))
ＹYSEL (3)).

The relationship between the bus width, the column address and the address decode signal YSEL <3: 0> is as shown in FIG. If the bus width is n (n-bit mode), the address decode signals YSEL (0) to YSEL (3) are "1" regardless of the column address. When the bus width is n / 2 (n / 2 bit mode) and the column address CAD (0) is “0”, the address decode signals YSEL (0) and YSEL (2) are
If it is "1" and the column address CAD (0) is "1", the address decode signals YSEL (1) and Y
SEL (3) becomes "1". Furthermore, the bus width is n / 4
In the case of this (n / 4 bit mode), the column address CA
One of the address decode signals YSEL (0) to YSEL (3) becomes "1" by the combination (four ways) of D (0) and CAD (1).

The relationship between the bus width and the external data lines (data input / output pins) used is as shown in FIG.
If the bus width is n, all external data lines are used. When the bus width becomes n / 2, the external data line DQ
(I) (i = 0, 2, 4,..., N−1) is used. Further, when the bus width becomes n / 4, the external data line DQ
(J) (j = 0, 4, 8,..., N−3) is used. The external data line DQ (j) used when the bus width is n / 2 or n / 4 is not limited to the combination shown in FIG.

An example of the configuration of IO selection circuit Zk included in IO selection section 204 will be described with reference to FIG. IO selection circuit Zk includes an IO switching circuit 210, a redundancy mode decoding circuit 211, and an IO line switching signal generation circuit 212. IO switching circuit 210 includes internal data lines DB (i),
DB (i + 1), DB (i + 2), DB (i + 3) and DB (i + 4) (or SDB) and external data line D
Q (i), DQ (i + 1), DQ (i + 2) and DQ
The connection with (i + 3) is switched.

The switching in the IO switching circuit 210
Selection signal DQS output from O line switching signal generation circuit 212
EL <3: 0> (= DQSEL (0) to DQSEL
(3)) and SDQSEL <3: 0> (= SDQSE
L (0) to SDQSEL (3)).

One example of the IO switching circuit 210 is shown in FIG. The IO switching circuit 210 includes switches 1201 to 120
3, input / output buffers BF0 to BF0 arranged for transfer gates 1205 to 1212 and external data lines DQ (i) to DQ (i + 3), respectively.
F3.

Transfer gates 1205-1212
As shown in FIG. 18, the inverter 220 inverts the control signal received at the node CON, the inverter 221 inverts the output of the inverter 220, the PMOS transistor T0 which is turned on based on the output of the inverter 220, and the inverter which is turned on based on the output of the inverter 221. Including an NMOS transistor T1. When the transistors T0 and T1 are turned on, a signal received at the node IN is transmitted to the node OUT.

Referring to FIG. 17, transfer gate 1
Reference numerals 205 to 1208 denote internal data lines DB (i) to DB
Select whether to use (i + 3). Transfer gate 1205 is connected between internal data line DB (i) and node N
0 in accordance with the selection signal DQSEL (0), and the transfer gate 1206 controls the internal data line DB (i +
1) and the node N1 are coupled according to the selection signal DQSEL (1). Transfer gate 1207 connects internal data line DB (i + 2) and node N2 to select signal DQSE.
L (2) and transfer gate 1208
Couples internal data line DB (i + 3) and node N3 in accordance with selection signal DQSEL (3).

Transfer gates 1209 to 1212
Is used to replace a defective data line using an internal data line DB (i + 4) (or SDB) shifted from an adjacent IO selection circuit. Transfer gate 1
209 couples internal data line DB (i + 4) and node N0 according to selection signal SDQSEL (0), and transfer gate 1210 couples internal data line DB (i + 4)
And node N1 according to selection signal SDQSEL (1). Transfer gate 1211 connects internal data line DB (i + 4) and node N2 to select signal SDQSE.
L (2) and transfer gate 1212
Couples internal data line DB (i + 4) and node N3 according to selection signal SDQSEL (3).

Switches 1201 to 1203 switch the bus wiring according to the bus width. The switch 1201 connects the nodes N1 and A (input / output buffer B) according to the bus width.
F0) or the node B (input / output buffer BF1). Switch 1202 connects node N2 to node A (input / output buffer BF0) or node B (input / output buffer BF2) according to the bus width. Switch 1
203 connects the node N3 to the node A (node N2) or the node B (input / output buffer BF3) according to the bus width.

More specifically, the switches 1201 to 12
03 is switched in the direction shown in FIG. 19 according to the bus width. In the figure, the symbol “A” means that the switch is connected to the node A, and “B” means that the switch is connected to the node B.

When the bus width is in the n-bit mode, node N
0 to N3 are separated from each other. When the bus width is in the n / 2 bit mode, nodes N0 and N1 are connected, and node N
2 and N3 are connected. When the bus width is in the n / 4 bit mode, node N0 and nodes N1, N2 and N3 are all connected.

The switching by the switches 1201 to 1203 can be performed by electrical switching using a transistor.
Switching using metal wiring may be used.

Referring to FIG. 16, redundant mode decode circuit 211 uses status signal (NRM, REM) using upper bit signal (USEL) of the replacement data line position signal.
D, SFT). These signals include information such as whether or not redundant replacement is required, whether a data line shared with an adjacent block is used for redundant replacement, or is shifted.

A block including a defective data line and a signal US
EL <7: 0> and the status signal NR of each block
FIG. 20 shows the relationship between M, RED, and SFT.

If the defective data line belongs to block k (the defective data line is one of the four data lines corresponding to IO selection circuit Zk), signal USEL (k)
~ USEL (7) becomes "1" and the others become "0". When there is no defect, all bits of the signal USEL <7: 0> are “0”.

Each block (IO selection circuit) can take three types of states: a case where there is no defect, a case where there is a defect and shifting, and a case where there is no defect and shifting.

For each block, the corresponding signals NRM, R
One of ED and SFT becomes "1". If the defective data line belongs to the block k, the signal R of the block k
ED becomes "1" (a shift operation is performed for replacement).
In the upper block of the block where the signal RED is "1",
The signal SFT becomes “1” (performs a shift operation), and in the lower block, the signal NRM becomes “1” (performs a normal operation).

FIG. 21 shows an example of the configuration of the redundancy mode decode circuit 211. Redundant mode decode circuit 211
Includes NOR circuits 230 and 235, an AND circuit 232, and an inverter 234. NOR circuit 230 receives signals USEL (k) and USEL (k-1), and receives signal NEL.
Output RM. The AND circuit 232 outputs the signal USEL.
(K), upon receiving USEL (k-1), outputs signal SFT. Inverter 234 inverts signal USEL (k), and NOR circuit 235 receives output of inverter 234 and signal USEL (k−1), and outputs signal RED. When k is 0, the ground voltage Gnd is applied to USEL (k-1).

The operation of the IO line switching signal generation circuit 212 will be described with reference to FIGS. FIG. 22 to FIG.
Reference numeral 4 denotes an input signal to the IO line switching signal generation circuit 212 and output signals DQSEL <3: 0> and SDQSEL <3: 0>.
The relationship is shown. FIG. 22 shows an n / 4 bit mode (bus width is n / 4 bits), FIG. 23 shows an n / 2 bit mode (bus width is n / 2 bits), and FIG. 24 shows an n bit mode (bus width). Correspond to n bits).

FIG. 25 shows the relationship between the position of the defective data line and the signal LSEL <3: 0>. Referring to FIG. 25, internal data line DB to which one block belongs
(I) to internal data line (i + 3) of DB (i + 3)
If k) is bad, the signals LSEL (0) to LSEL
In (3), the signal LSEL (k) becomes “1”.

Referring to FIGS. 22 to 24, if NMR = 1, signals DQSEL (0) to DQSEL (3) take the same value as signals YSEL (0) to YSEL (3), and signal SDQSEL ( 0) to SDQSEL (3) = 0.

If SFT = 1, the signal YSEL (0)
= 1, the signal DQSEL (0) = 0 and the signal DQSEL (0)
QSEL (1) to DQSEL (3) are signals YSEL
It becomes the same value as (1) -YSEL (3), and SDQSEL
(0) = 1, and SDQSEL (1) to SDQSEL
(3) = 0. When YSEL (0) = 0, the signal D
QSEL (0) to DQSEL (3) are signals YSEL
(0) to take the same value as YSEL (3), and the signal SDQS
EL (0) to SDQSEL (3) = 0.

If RED = 1, the signals YSEL and LS
DQSEL (0) to DQSEL depending on EL
(3), signals SDQSEL (0) to SDQSEL (3)
Is determined.

FIGS. 26 and 27 show circuits 260 and 270 included in IO line switching signal generation circuit 212. The circuit 260 shown in FIG. 26 includes a signal DQSEL (j)
And SDQSEL (j) (j = 1, 2, 3). The circuit 270 shown in FIG.
This is a circuit that outputs EL (0) and SDQSEL (0).

The circuit 260 receives the signals RED, YSEL
(J) and NAND circuit 26 receiving LSEL (j)
1. NOR circuit 26 receiving signals NRM and SFT
3. An AND circuit 264 receiving the signal YSEL (j) and the output of the NOR circuit 263, a signal DQSEL receiving the output of the NAND circuit 261 and the output of the AND circuit 264
AND circuit 262 that outputs (j), signals RED and YS
NAND circuit 26 receiving EL (j) and LSEL (j)
5, and an inverter 266 that inverts the output of the NAND circuit 265 and outputs the signal SDQSEL (j).

The circuit 270 includes an inverter 271 receiving and inverting the signal SFT, an inverter 272 receiving and inverting the signal YSEL (0), and a signal NRM and the inverter 272.
NAND circuit 273 receiving the output of
NAND circuit 274 receiving SEL (0) and LSEL (0), output of inverter 271, NAND
AND circuit 275 receiving an output of circuit 273 and an output of NAND circuit 274 and outputting signal DQSEL (0)
including.

The circuit 270 further includes an inverter 276 for inverting the signal NRM, signals SFT and YSEL (0).
Circuit 277 receiving signals RED and YSEL
NAND circuit 27 receiving (0) and LSEL (0)
8, the output of the inverter 276, the NAND circuit 2
An AND circuit 279 receiving an output of 77 and an output of NAND circuit 278 and outputting signal SDQSEL (0) is included.

Here, the operation of semiconductor memory device 2000 will be described by taking as an example a case where “× 8” is designated as the data line configuration. There is a defect in the memory cell corresponding to normal data line LIO (5), and normal data line LI
O (5) is to be replaced.

When act command ACT is input, a word line is activated in accordance with input row address RAD <x: 0>, and data of a memory cell is held in a sense amplifier. All normal data line pairs LIO,
Complementary data signals are transmitted to / LIO and redundant data line pair SLIO, / SLIO.

Next, when a read command READ is input, the read amplifier is activated and data is transferred to the internal data line D.
B, SDB.

Since the data line configuration is “× 8”, the external data line (data input / output pin) used is DQ
(0), DQ (4), DQ (8),..., DQ (28). Therefore, in order to determine eight internal data lines to be used out of the 32 regular internal data lines, a signal based on a 2-bit column address CAD (0), CAD (1) input simultaneously with the read command READ. YSE
L <3: 0> is generated.

Replacement data line position signals USEL, LSEL
Is a fixed signal, which is determined before the column operation. Each IO according to the signals YSEL, USEL, LSEL
The control signal of the selection circuit is switched, and the internal data lines DB, S
DB and external data line DQ are connected.

FIG. 28 shows the state of the control signal in each IO selection circuit. Since the data line to be replaced is LIO (5), redundant replacement is required in the IO selection circuit Z1.
The status signal RED of the IO selection circuit Z1 becomes "1".

In IO selection circuit Z1, internal data line DB (i + 1) shown in FIG. 17 is a data line to be replaced, so that signal DQSEL (1) is fixed at "L". Only when the column address CAD <1: 0> = "01", the signal SDQSEL (1) indicating the replacement destination becomes "H". Otherwise, the signal SDQSEL (1) is “L”
become. Signals DQSEL (0), DQSEL (2), D
The value of QSEL (3) is determined according to the decoding of the column address CAD <1: 0>. The signal SD
QSEL (0), SDQSEL (2), SDQSEL
(3) is fixed at “L”.

Blocks lower than block 1 (IO selection circuit Z1), ie, IO selection circuit Z0, do not need to shift internal data lines. Therefore, the numbers assigned to the internal data lines DB and the external data lines DQ are the same. In the IO selection circuit Z0, the signal NRM is "1". In this block, the signals SDQSEL are all fixed at L, and one of the signals DQSEL is CAD <1:
0> in accordance with 0>.

Block 1 uses internal data line DB (8) shared with block 2 (IO selection circuit Z2) as a redundant data line. For this reason, the upper block 2 uses the internal data line DB (12) shared with the adjacent block.
Use Blocks 3 to 7 (IO selection circuits Z3 to Z)
7) performs the same operation. That is, the connection of the data line is shifted. In the IO selection circuits Z2 to Z7, the status signal SFT is "1".

In FIG. 17, internal data lines DB (i + 4), DB (i + 1) and DB (i +) are connected to nodes N0 to N3.
2), DB (i + 3) are connected in order, and the internal data line DB
(I) is disabled. That is, when the column address CAD <1: 0> = "00", the signal SDQ
SEL (0) is “H”, and signal DQSEL (0) is “L”.
And the internal data line shared with the adjacent block is replaced with the internal data line DB (i). Otherwise, the signal DQSEL follows the column address CAD,
Signal SDQSEL is fixed at “L”.

In the write operation, the data lines are switched as in the read operation. In the IO selection unit 204, the input 8-bit write data is expanded into 32 bits, and the defective data line is replaced with a redundant data line. Then, the write data is written to the memory cell via the sense amplifier.

[Fourth Embodiment] A semiconductor memory device according to a fourth embodiment will be described. In the fourth embodiment, the number of redundant data line pairs is set to 2 (SLIOA, / SL
IOA and) and SLIOB, / SLIOB)
A configuration in which two defective data lines can be replaced at the same time will be described. Note that, similarly to the third embodiment, the number of normal data line pairs is 32 (LIO (i), / LIO (i);
i = 0 to 31), and the data line configuration is ×
32, × 16, and × 8 can be switched, and in the case of a × 16, × 8 configuration, a data line is selected using a column address.

Referring to FIG. 29, a semiconductor memory device 3000 according to the fourth embodiment has a plurality of memory cells arranged in a matrix, a plurality of word lines corresponding to rows, and a plurality of bit lines corresponding to columns. , A normal data line pair 101, a redundant data line pair 102, a row decoder 302, and a read amplifier / write driver unit 303 connected to a memory cell via a sense amplifier. The functions of the row decoder 302 and the read amplifier / write driver 303 shown in FIG.
3 and so detailed description will not be repeated.

The semiconductor memory device 3000 further includes an IO selection section 304 including IO selection circuits ZA0 to ZA7, a bus width selection signal generation circuit 305, and a redundancy selection signal generation circuit 306.
And a data line selection signal generation circuit 307.

Normal data line pair LIO (i), / LI
O (i) and the redundant data line pair SLIOA, / SLIOA
And the data to / from SLIOB and / SLIOB via a plurality of read amplifier / write drivers RW in the read amplifier / write driver unit 303, respectively, to the internal data line DB (i) and the redundant internal data lines SDBA and SBA.
DBB.

The data on the internal data line DB (i) and the data on the redundant internal data lines SDBA and SDBB are transmitted to the normal data line pair LIO (i) and / LIO (i) via the read amplifier / write driver 303, respectively. , Redundant data line pairs SLIOA, / SLIOA and SLIOB, /
Transmitted to the SLIOB.

The IO selection section 304 selects an internal data line to be used according to the bus width (column address) and the presence or absence of redundant use. Hereinafter, the internal data lines DB (i) and the redundant internal data lines SDBA, SDBB are also referred to as internal data lines DB (i), SDBA, SDBB.

The IO selecting section 304 operates according to the third embodiment to replace two defective data lines at the same time.
It has a different configuration from the selection unit 204.

Also in the fourth embodiment, internal data lines DB (0) to DB (31), SDBA and SDBB are
The block is divided into eight sets. Here, the internal data line DB
(3), DB (4), DB (7), DB (8), ..., D
Each of B (27) and DB (28) is shared between adjacent blocks. That is, in the fourth embodiment, two internal data lines are shared between adjacent blocks.

IO select circuit ZA0 is connected to external data line DQ
An external data line used among (0) to DQ (3) and four used among internal data lines DB (0) to DB (4) and SDBA are electrically coupled. IO selection circuit ZA
i (block i) are external data lines DQ (4 × i) to D
The external data line used in Q (4 × i + 3) and the four used internal data lines DB (4 × i−1) to DB (4 × i + 4) are electrically coupled (i = 1). ~ 6).
IO selection circuit ZA7 includes external data lines DQ (28) to DQ (D).
An external data line used in Q (31) is electrically coupled to four used internal data lines DB (27) to DB (31) and SDBB.

The bus width selection signal generation circuit 305 outputs a bus width selection signal BUSSEL <2: 0 according to the setting of the bus width.
> (= BUSSEL (2) to BUSSEL (0)). The relationship between the bus width, the column address and the address decode signal YSEL <3: 0> is as shown in FIG. If the bus width is n, the bus width selection signal BUSSEL (2) is “1” and the remaining BUSS
EL (0) and BUSSEL (1) are “0”.
Similarly, when the bus width is n / 2 and when the bus width is n / 4
In each case, the bus width selection signal BUSS
EL (1) and BUSSEL (0) are set to “1”, and the remaining bus width selection signals are set to “0”.

The relationship between the bus width and the external data lines (data input / output pins) to be used is the same as in the third embodiment, and therefore, detailed description will not be repeated.

The redundancy selection signal generation circuit 306 stores the position of a normal data line requiring redundancy replacement, and generates a decode signal according to the stored content. The decoded signal is called a replacement data line position signal, and its upper bit signal is
ELA <7: 0> (= USELA (0) to USELA
(7)), USELB <7: 0> (= USELB (0)
To USELB (7)). Signal USELA <7: 0
> And USELB <7: 0> indicate the presence of a defective data line in each IO selection circuit. Upper bit signals USELA <7: 0> and USELB <7:
0> will be described in detail later.

On the other hand, the lower bit signal of the replacement data line position signal is represented by LSELA <3: 0> (= LSELA (0) to LSELA (L)).
SELA (3)) and LSELB <3: 0> (= LS
ELB (0) to LSELB (3)). Signal LSE
Each of LA <3: 0> and LSELB <3: 0> indicates which of the corresponding four data lines in the IO selection circuit unit is defective. Lower bit signal L
SELA <3: 0> and LSELB <3: 0> are set according to the lower bit signal LSEL <3: 0> shown in FIG.
Therefore, detailed description will not be repeated.

As a result, upper bit signal USELA <
7: 0> and the lower bit signal LSELA <3: 0> can indicate one defective data line, and the upper bit signal USELB <7: 0> and the lower bit signal LS
ELB <3: 0> indicates another defective data line. In the following, one of the two defective data lines having the smaller index number (i) (that is, the lower one) has the signal USELA <7: 0.
> And LSELA <3: 0>, and the other having the larger index number (i) (that is, the upper side) is the signal USELB <7: 0> and LSELB <3:
0>.

In the following, USELA <7:
0>, USELB <7: 0>, LSELA <3: 0>, and LSELB <3: 0> are simply referred to as USELA, USELB, LSELA, and L
It is also referred to as SELB.

The redundancy selection signal generation circuit 306 uses a fuse in order to store the position of the data line that needs to be replaced, similarly to the redundancy selection signal generation circuit 206 described with reference to FIG. The position information is stored by blowing (or not blowing) the fuse in accordance with the position.
Note that the configuration of the redundancy selection signal generation circuit 306 also
Not limited to fuses.

The data line selection signal generation circuit 307 outputs the column address CAD <1: 0> (= CAD (0), CAD
An address decode signal YSEL <3: 0> (= YSEL (0)) for selecting a data line based on (1))
ＹYSEL (3)).

The relationship between the bus width (n, n / 2, n / 4), the column address CAD <1: 0>, and the address decode signal YSEL <3: 0> has been described in the third embodiment. This is similar to FIG. That is, in the case of the n-bit mode, the address decode signals YSEL (0) to YSEL (3) are "1" regardless of the column address. n
/ 2 bit mode, column address CAD (0)
Is "0", the address decode signal YSEL
If (0) and YSEL (2) are “1” and the column address CAD (0) is “1”, the address decode signals YSEL (1) and YSEL (3) are “1”.
become. Further, in the case of the n / 4 bit mode, combinations of column addresses CAD (0) and CAD (1) (four types)
As a result, the address decode signals YSEL (0) to YSE
One of L (3) becomes “1”.

One example of the configuration of IO selection circuit ZAk included in IO selection section 304 will be described with reference to FIG. IO
The selection circuit ZAk includes an IO switching circuit 310, a redundancy mode decoding circuit 311 and an IO line switching signal generation circuit 312.
including.

The IO switching circuit 310 has an internal data line DB
(I-1) (or SDBA), DB (i), DB (i
+1), DB (i + 2), DB (i + 3) and DB
(I + 4) (or SDBB) and external data line DQ
(I), DQ (i + 1), DQ (i + 2) and DQ
The connection to (i + 3) is switched.

The switching in the IO switching circuit 310
Selection signal DQS output from O line switching signal generation circuit 312
EL <3: 0> (= DQSEL (0) to DQSEL
(3)), SDQSELA <3: 0> (= SDQSELA
A (0) to SDQSELA (3)) and SDQSEL
B <3: 0> (= SDQSELB (0) to SDQSEL
B (3).

In the following, selection signal DQSEL <
3: 0>, SDQSELA <3: 0> and SDQSE
LB <3: 0> are simply referred to as selection signals DQSEL, SDQSELA and SDQSEL.
B.

An example of the IO switching circuit 310 is shown in FIG. The IO switching circuit 310 includes selection circuits 1301 to 130
4, switches 1201-1203 and input / output buffers BF0-BF3 arranged for external data lines DQ (i) -DQ (i + 3), respectively.

The selection circuits 1301 to 1304 perform a shift operation of an internal data line for replacing a defective data line by selecting signals DQSEL <3: 0> and SDQSELA <3: 0.
> And SDQSELB <3: 0>.

The selection circuit 1301 receives the selection signal DQSEL
(0), SDQSELA (0) and SDQSELB
(0), the selection circuit 1302 outputs the selection signals DQSEL (1), SDQSELA (1) and SDQSELA (1).
It operates based on QSELB (1). Similarly, the selection circuit 1303 selects the selection signals DQSEL (2), SDQSE
The selection circuit 1304 operates based on LA (2) and SDQSELB (2), and selects a selection signal DQSEL (3),
It operates based on SDQSELA (3) and SDQSELB (3).

In each selection circuit, selection signal DQSE
One of L, SDQSELA and SDQSELB is set to “1”, and the other two are set to “0”. When the selection signal DQSEL is set to “1”, it indicates that the corresponding internal data line in the same block is used. On the other hand, when performing a shift operation or a replacement operation, the selection signal SDQSELA or SDQSELB is set to “1”, and the internal data lines of the upper or lower adjacent block are used.

Referring to FIG. 33, selection circuits 1301-1
Reference numeral 304 denotes an output node No. and an internal data line DB
(I-1) (or SDBA) and a transfer gate 1306 provided between the output node No and the corresponding one of the internal data lines DB (i) to DB (i + 3). , Output node No. and internal data line DB (i + 4) (or SD
BB) and a transfer gate 1308
And The output node Nos.
Each of the nodes 304 corresponds to the nodes N0 to N3.

Transfer gates 1306 to 1308
Is similar to that shown in FIG. Therefore, transfer gate 1306 electrically couples internal data line DB (i-1) to output node No when corresponding select signal SDQSELA is set to H level ("1"). Similarly, transfer gate 130
7, the internal data line DB (i) when the corresponding selection signal DQSEL is set to the H level (“1”).
-1) to the corresponding one of DB (i + 3) and the output node No. are electrically coupled. Transfer gate 1
Reference numeral 308 denotes an internal data line DB (i) when the corresponding selection signal SDQSELB is set to the H level (“1”).
-1) is electrically coupled to the output node No.

Switches 1201 to 1203 switch the bus wiring according to the bus width. Switches 1201 to 120
Operation 3 is the same as that described in the second embodiment with reference to FIG. 19, and thus detailed description will not be repeated. For example, a bus width selection signal BUSSEL <indicating the bus width
2: 0>, the connections of the switches 1201 to 1203 may be switched.

As a result, as in the second embodiment, n
In the bit mode, nodes N0 to N3 are separated from each other. In the n / 2-bit mode, nodes N0 and N1 are connected, and nodes N2 and N3 are connected. n / 4
In the bit mode, the node N0 and the nodes N1, N2,
N3 are all connected. Also, switches 1201 to
The switching by 1203 may be electrical switching using a transistor or switching using a metal wiring.

Referring again to FIG. 31, redundant mode decode circuit 311 uses the upper bit signals (USELA, USELB) of the replacement data line position signal to output status signals (NRM, SFTA, SFTB, READA, RED).
B, REDAB). These signals indicate that the corresponding IO switching circuit 310 has the following six statuses:
(1) The connection relationship does not change (status signal NRM:
(1)), (2) Shift using internal data lines of adjacent (lower) blocks (status signal SFTA:
(1)), (3) Shift using internal data lines of adjacent (upper) blocks (status signal SFTB:
(1)), (4) includes a defective data line indicated by signal USELA, and performs replacement of the defective data line (status signal REDA: "1"); (5) includes a defective data line indicated by signal USELB; Replace defective data line (status signal REDB: "1"), and (6) 2
It indicates which of the following is included, including replacement of defective data lines (status signal REDAB: “1”).

That is, each block (IO selection circuit)
Can take six types of states depending on the positions of the two defective data lines, three cases where there is no defect, there is no defect but shift, and there is a defect and replacement.

FIG. 34 shows the relationship between each of signals USELA <7: 0> and USELB <7: 0> and the status decode intermediate signal of each block.

Referring to FIG. 34A, signal USELB
When the defective data line is indicated by <7: 0>, the defective data line belongs to the block k (the defective data line is
Any one of four data lines corresponding to IO selection circuit ZAk
Signals USELA (0) to USELA
(K) becomes "1", and the others become "0". When there is no defect, all bits of the signal USELA <7: 0> are “0”.

According to signal USELA <7: 0>, corresponding status decode intermediate signal NR is provided for each block.
One of M1, RED1, and SFT1 is set to “1”.

Specifically, when the defective data line indicated by the signal USELA <7: 0> belongs to the block k, the signal RED1 of the block k becomes "1" (performs a replacement operation). In each of the upper blocks of the block where the signal RED1 is "1", the signal SFT1 becomes "1" (performs a shift operation), and in each of the lower blocks, the signal NRM1 becomes "1" (normal operation). I do).

Referring to FIG. 34 (b), the signal U
When a defective data line is indicated by SELB <7: 0>, when the defective data line belongs to block k, signals USELB (k) to USELB (7) are set to “1”, and the other signals are set to “0”. become. When there is no defect, the signal USEL
All bits of B <7: 0> are “0”.

According to signal USELB <7: 0>, corresponding status decode intermediate signal NR is provided for each block.
One of M2, RED2, and SFT2 becomes "1". When the defective data line indicated by the signal USELB <7: 0> belongs to the block k, the signal RED2 of the block k becomes “1” (performs a replacement operation). Signal R
In each of the lower blocks of the block in which ED2 is "1", the signal SFT2 becomes "1" (performs a shift operation), and in each of the upper blocks, the signal NRM2 becomes "1".
(Normal operation is performed).

FIG. 35 shows the correspondence between these status decode intermediate signals and the six status signals described above.

Referring to FIG. 35, the signal USELA <7:
0> and USELB <7: 0> are associated with the lower and upper sides of the two defective data lines, respectively.
In the status decode intermediate signal, SFT1 = SF
T2 = “1”, SFT1 = RED2 =
Case of “1” and RED1 = SFT2 =
None of the cases of "1" can occur.

Therefore, redundant mode decode circuit 31
1 is a signal USELA <7: 0> and USE for indicating two defective data lines in each block.
Based on the decoding result of LB <7: 0>, status signals NRM, SFTA, SFTB, REDA, RED
One of B and REDAB is set to “1”.

As an example, block 2 and block 6
FIG. 36 shows the result of decoding the status signal of each block when there is a defective data line in FIG.

Referring to FIGS. 36 (a) and 36 (b), defective data lines existing in blocks 2 and 6 are supplied with signals USELA <7: 0> and USELB <
7: 0>. Therefore, the signal USELA
(0) to USELA (2) become “1” and the signal USE
LA (3) to USELA (7) become “0”. on the other hand,
The signals USELB (0) to USELB (5) become “0”, and the signals USELB (6) and USELB (7) become “1”.
become.

According to such signals USELA <7: 0> and USELB <7: 0>, status decode intermediate signals SFT1 and SFT1 in each block according to the relationship shown in FIGS. 34 (a) and 34 (b). RED1, N
RM1, SFT2, RED2, and NRM2 are set.

Further, according to these status decode intermediate signals, status signals NR in each block are obtained.
M, SFTA, SFTB, REDA, REDB, RED
AB is set as shown in FIG.

Referring to FIG. 36 (c), in each of blocks where a defective data line exists (hereinafter, also referred to as a defective block), status signals REDA and RE are provided.
DB is set to "1", and the replacement operation is executed in the block.

In blocks 0 and 1, which are located on the lower side of block 2 which is a defective block, shift using data of an adjacent (lower side) block is performed to replace a defective data line (in block 2). Must be performed, the status signal SFTA is set to "1".
Is set to

Similarly, in block 7 which is located on the upper side of block 6 which is a defective block, in order to replace the defective data line (in block 6), it is adjacent (upper side).
Since it is necessary to perform a shift using the data of the block, the status signal SFTB is set to "1".

On the other hand, in each of block 3, block 4 and block 5 sandwiched between defective blocks, no shift operation or replacement operation is performed, so that status signal NRM is set to "1".

The redundant mode decode circuit 311 is provided in the
35 and a combination of logic gates that can obtain the decoding result shown in FIG. 35, and can be configured in hardware or software.

Next, the operation of IO line switching signal generation circuit 312 will be described with reference to FIGS. FIG.
39 to FIG. 39 show the input signal to the IO line switching signal generation circuit 312 and the output signals DQSEL <3: 0> and SDQSELA <
3: 0> and SDQSELB <3: 0>.

FIG. 37 shows an example in which the n / 4 bit mode is used.
Corresponds to the n / 2-bit mode, and FIG. 39 corresponds to the n-bit mode.

Referring to FIGS. 37 to 39, if NMR = 1, signals DQSEL (0) to DQSEL (3) take the same value as signals YSEL (0) to YSEL (3), and signal SDQSELA ( 0)-SDQSELA (3), SD
QSELB (0) to SDQSELB (3) = 0.

If SFTA = 1, the signal YSEL
When (3) = 1, the signal SDQSELA (3) = 1, and the signals DQSEL (0) to DQSEL (2) take the same value as the signals YSEL (0) to YSEL (2),
SEL (3) = 0. Also, the signal SDQSELA
(0)-SDQSELA (2), SDQSELB (0)
SDQSELB (3) = 0. On the other hand, YSEL
When (3) = 0, the signals DQSEL (0) to DQSEL
(3) takes the same value as the signals YSEL (0) to YSEL (3) and outputs the signals SDQSELA (0) to SDQSELA.
(3), SDQSELB (0) to SDQSELB (3)
= 0.

If SFTB = 1, the signal YSEL
When (0) = 1, the signal SDQSELB (0) = 1, and the signals DQSEL (1) to DQSEL (3) take the same values as the signals YSEL (1) to YSEL (3),
SEL (0) = 0. Also, the signal SDQSELB
(1)-SDQSELB (3), SDQSELA (0)
~ SDQSELA (3) = 0. On the other hand, YSEL
When (0) = 0, signals DQSEL (0) to DQSEL
(3) takes the same value as the signals YSEL (0) to YSEL (3) and outputs the signals SDQSELA (0) to SDQSELA.
(3), SDQSELB (0) to SDQSELB (3)
= 0.

If REDA = 1, the signals YSEL and L
In response to SELA, signals DQSEL (0) to DQSE
L (3) and SDQSELA (0) to SDQSELA
The value of (3) is determined. Also, the signal SDQSELB
(0) to SDQSELB (3) = 0.

LSELA (j) = 1 corresponding to the data line selected by YSEL (j) = 1 (j = 0 to 3)
, DQSEL (j) = 0, SDQSELA
(J) = 1 and SDQSELB (j) = 0. On the other hand, when LSELA (j) = 0, DQSEL
(J) = 1 and SDQSELA (j) = 0.

On the other hand, YSEL (k) = 0 (k:
DQSEL (k) = (0-3)
SDQSELA (k) = 0.

If REDB = 1, signals YSEL and L
DQSEL (0) to DQSEL depending on SELB
(3), signals SDQSELB (0) to SDQSELB
The value of (3) is determined. Also, the signal SDQSELA
(0) to SDQSELA (3) = 0.

LSELB (j) = 1 corresponding to the data line selected by YSEL (j) = 1 (j = 0 to 3)
In the case of, DQSEL (j) = 0, SDQSELB
(J) = 1 and SDQSELA (j) = 0. On the other hand, when LSELB (j) = 0, DQSEL
(J) = 1 and SDQSELB (j) = 0.

On the other hand, YSEL (k) = 0 (k:
DQSEL (k) = (0-3)
SDQSELB (k) = 0.

If REDAB = 1, the signals SDQSELA (0) to SDQSELA (0) to YSEL and LSELA
The value of SDQSELA (3) is determined, and according to signals YSEL and LSELB, signals SDQSELA (0)-
The value of SDQSELB (3) is determined. Note that SDQ
SELA (3) = 0.

More specifically, YSEL (j) = 1 (j = 0
LSEL corresponding to the data line selected by 2)
When A (j) = 1, DQSEL (j) = 0, SD
QSELA (j) = 1. Also, YSEL (i) =
When LSELB (i) = 1 corresponding to the data line selected by 1 (i = 0 to 3), DQSEL (i)
= 0 and SDQSELB (i) = 1.

On the other hand, LSELA (i) = LSELB corresponding to the data line selected by YSEL (i) = 1
If (i) = 0, DQSEL (i) = 1 and S
DQSELA (i) = SDQSELB (i) = 0.

In addition, YSEL (k) = 0 (k: 0 to 3)
DQSEL (k) = SDQS corresponding to the data line
ELA (k) = SDQSELB (k) = 0.

Note that the signals LSELA (j) and LSE
Since LB (i) is associated with the lower and upper sides of the two defective data lines, there is no state where LSELA (j) = LSELB (i) = 1 in the range of i ≦ j. .

The IO line switching signal generation circuit 312 is provided with the configuration shown in FIG.
To the output signal DQSEL <3: 0 as shown in FIG.
>, SDQSELA <3: 0> and SDQSELB <
3: 0> can be configured by hardware using a combination of logic gates that can obtain 3: 0>, or can be configured by software.

Here, the operation of semiconductor memory device 3000 will be described by taking as an example a case where "× 8", that is, the n / 4 bit mode is designated as the data line configuration. A defect exists in a memory cell corresponding to normal data lines LIO (9) and LIO (26), and normal data lines LIO (9) and LIO (26) are defective.
(9) and LIO (26) are to be replaced.

FIG. 40 shows the state of the control signal in each IO selection circuit. Since the defective data line, that is, the normal data line to be replaced exists in each of the blocks 2 and 6, the values of the status signals SFTA, REDA, NRM, REDB, and SFTB in each block are shown in FIG. It will be the same as

Blocks 0 and 1 in which status signal SFTA = "1", ie, IO selection circuit ZA
At 0, ZA1, a shift using data from the lower side is executed. That is, internal data line DB (i + 3) shown in FIG. 32 is replaced by data shifted from the lower side, and thus signal DQSEL (3) is fixed to “0”. Then, the column address CAD <1: 0>
= “11” only, signal SDQSELA indicating replacement destination
(3) becomes “1”. Otherwise, the signal SDQSE
LA (3) becomes “0”. Signal DQSEL (0),
The values of DQSEL (1) and DQSEL (2) are determined according to the decoding of the column address CAD <1: 0>. Note that the signals SDQSELA (0), SDQSEL
A (1), SDQSELA (2), SDQSELB
(0) to SDQSELB (3) are fixed to “0”.

In the block 2 where the status signal REDA = "1", that is, in the IO selection circuit ZA2, the internal data line DB (i + 1) shown in FIG. 32 is the data line to be replaced, so that the signal DQSEL (1) is " It is fixed to 0 ". Then, the column address CAD <1: 0> = “0”
Only when “1”, the signal SDQSELA (1) indicating the replacement destination
Becomes “1”. Otherwise, the signal SDQSELA
(1) becomes “0”. Signal DQSEL (0), DQ
SEL (2) and DQSEL (3) are column addresses C
The value is determined according to the decoding of AD <1: 0>. Note that the signals SDQSELA (0), SDQSELA
(2), SDQSELA (3), SDQSELB (0)
ＳＤSDQSELB (3) is fixed to “0”.

In the block 6 where the status signal REDB = "1", that is, the IO selection circuit ZA6, since the internal data line DB (i + 3) shown in FIG. 32 is the data line to be replaced, the signal DQSEL (3) is " L ”. Then, the column address CAD <1: 0> = “1”
Only when 1 ", the signal SDQSELB (3) indicating the replacement destination
Becomes “H”. Otherwise, the signal SDQSELB
(3) becomes “0”. Signal DQSEL (0), DQ
SEL (1) and DQSEL (2) are column addresses C
The value is determined according to the decoding of AD <1: 0>. The signals SDQSELA (0) to SDQSELA
(3) and SDQSELB (0) to SDQSELB
(2) is fixed to “0”.

Blocks 3 to 5 where status signal NRM = "1", ie, IO selection circuits ZA3 to ZA
In A5, there is no need to shift the internal data lines. Therefore, the numbers assigned to the internal data lines DB and the external data lines DQ are the same. In these blocks, the signals SDQSELA and SDQSLB are all fixed to "0" and one of the signals DQSEL is CAD <1: 0.
>"1".

In the block 7 where the status signal SFTB becomes "1", that is, in the IO selection circuit ZA7, a shift using data from the upper side is performed. In other words, internal data line DB (i) shown in FIG. 32 is replaced by redundant internal data line SDBB, so that signal DQSE
L (0) is fixed to “L”. Then, only when the column address CAD <1: 0> = "00", the signal SDQSELB (0) indicating the replacement destination becomes "1". Otherwise, the signal SDQSELB (0) becomes “0”. The values of the signals DQSEL (1) to DQSEL (3) are determined according to the decoding of the column address CAD <1: 0>. The signals SDQSELA (0) to SDQSEL
A (3), SDQSELB (1)-SDQSELB
(3) is fixed to “0”.

As a result, block 2 (IO selection circuit ZA)
In 2), the internal data line DB (9) which is a defective data line
Are not used, and the internal data line DB (7) shared with the lower block 1 (IO selection circuit ZA1) is used as a redundant data line. That is, the external data line DQ
(9) is connected to the internal data line DB (7).

Accordingly, in lower block 0 and block B1 (IO select circuits ZA0, ZA1), redundant internal data line SDBA and internal data line DB
(3) is used as a redundant data line corresponding to internal data lines DB (3) and DB (7), respectively.

Similarly, block 6 (IO selection circuit ZA)
In (6), the internal data line DB (2
7) is not used, and the internal data line DB (28) shared with the upper block 7 (IO selection circuit ZA7) is used as a redundant data line. That is, external data line DQ (27) is connected to internal data line DB (28).

In response, the upper block 7 (IO
In selection circuit ZA7), redundant internal data line SDB
B is used as a redundant data line corresponding to internal data line DB (28).

The operation of semiconductor memory device 3000 at the time of read operation and write operation is performed according to IO selection circuits ZA0 to ZA.
Except for connection between internal data lines DB, SDBA, SDBB and external data line DQ in A7, the configuration is the same as that of semiconductor memory device 2000 according to the third embodiment, and therefore detailed description will not be repeated.

According to the configuration according to the fourth embodiment, the data line selection circuit and the redundancy replacement circuit are shared, and the shift redundancy method is combined in units of blocks, thereby switching the bus width in a multi-data line configuration. In such a semiconductor memory device, high-speed data transfer can be performed, and two defective data lines can be simultaneously replaced, so that redundancy efficiency can be improved.

Next, as a modified example of the fourth embodiment,
A test mode setting for performing an operation test on the semiconductor memory device according to the fourth embodiment will be described.

[Modification 1 of Fourth Embodiment] In Modification 1 of the fourth embodiment, the IO selection unit 3 shown in FIG.
The configuration of each of the IO selection circuits included in the fourth embodiment differs from that of the fourth embodiment.

An example of the configuration of IO selection circuit ZBk (k: 0 to 7) according to the first modification of the fourth embodiment will be described with reference to FIG.

The IO selection circuit ZBk is different from the IO selection circuit ZAk according to the fourth embodiment in that a redundancy mode decoding circuit 313 is used instead of the redundancy mode decoding circuit 311.
Is different. The configuration of other portions of IO selection circuit ZBk is similar to that of IO selection circuit ZAk, and therefore, detailed description will not be repeated.

Redundant mode decode circuit 313 further receives test mode signals TM1A and TM1B, as compared with redundant mode decode circuit 311.

Test mode signals TM1A and TM1B
Are set to “L”, the redundancy mode decoding circuit 313, like the redundancy mode decoding circuit 311, outputs the status signal (NRM, SRM) of the corresponding block.
FTA, SFTB, REDA, REDB, REDAB)
Generate

Referring to FIG. 42, in the test mode, when an operation test is performed by setting test mode signal TM1A or TM1B to "H", at the same time, LSELA (0) = LSELB (0) = Set to “1” and LSELA (1) to LSELA (3) = LS
ELB (1) to LSELB (3) are set to “0”.
It is assumed that both test mode signals TM1A and TM1B are not set to “H”.

Referring to FIG. 43 (a), redundant mode decode circuit 313 outputs test mode signal TM1A.
When set to “H”, the status signal SFTA is set to “1” in each block. Therefore,
Each IO selection circuit performs a shift operation using an internal data line of an adjacent (lower) block.

On the other hand, referring to FIG. 43 (b), when test mode signal TM1B is set to "H", redundancy mode decode circuit 313 sets status signal SFTB to "1" in each block. I do. Therefore, each IO selection circuit performs a shift operation using an internal data line of an adjacent (upper) block.

Since the structure and operation other than the IO selection circuit are the same as those of the fourth embodiment, detailed description will not be repeated.

The redundant mode decode circuit 313 is provided in FIG.
4. It can be configured as hardware or software using a combination of logic gates that can obtain the decoding results shown in FIGS. 35 and 43.

According to the configuration according to the first modification of the fourth setting embodiment, test mode signal TM1A or TM1
By setting B to "H", the shift operation is forcibly executed in all the blocks, and in response to this, it is confirmed whether or not the output of the external data line is appropriately switched, whereby A test mode for checking the data line switching function in the IO selection circuit can be set.

[Modification 2 of Fourth Embodiment] In Modification 2 of the fourth embodiment, each configuration of the IO selection circuit included in IO selection section 304 shown in FIG. This is different from the fourth embodiment.

An example of the configuration of IO selection circuit ZCk (k: 0 to 7) according to the second modification of the fourth embodiment will be described with reference to FIG.

In comparison with IO selection circuit ZAk according to the fourth embodiment, IO selection circuit ZCk is redundant mode decoding circuit 314 instead of redundant mode decoding circuit 311.
Is different. Other configurations of IO selection circuit ZCk are similar to those of IO selection circuit ZAk, and therefore, detailed description will not be repeated.

Redundant mode decode circuit 314 further receives test mode signal TM2, as compared with redundant mode decode circuit 311.

When test mode signal TM2 is set to "L", redundant mode decode circuit 313 outputs the status signal (NRM, SFTA, SFTB, RETB) of the corresponding block similarly to redundant mode decode circuit 311.
DA, REDB, REDAB).

Referring to FIG. 45, in the test mode, when test mode signal TM2 is set to "H" to execute an operation test, LSELA (0) =
LSELB (0) is set to "1" and LSELA
(1) to LSELA (3) = LSELB (1) to LSE
LB (3) is set to "0".

Referring to FIG. 46, when the test mode signal TM2 is set to "H", the redundancy mode decode circuit 314 outputs the status signal R in the block 0.
EDA is set to "1", and the status signal REDB is set to "1" in block 7. Also,
In the remaining blocks 1 to 6, the status signal NRM is set to "1". As a result, in the block 0 corresponding to the redundant internal data line SDBA, the internal data line DB (0) is set by the redundant internal data line SDBA. Will be replaced. Therefore, external data line DQ (0) and redundant internal data line SDBA are connected. Similarly, in block 7 corresponding to redundant internal data line SDBB, internal data line DB (28) is replaced by redundant internal data line SDBB. Therefore, external data line DQ (28) and redundant internal data line S
DBB is connected.

Further, column address CAD <1: 0>
By inputting "00", both the redundant internal data lines SDBA and SDBB can be simultaneously accessed.

Structures and operations other than the IO selection circuit are the same as those of the fourth embodiment, and therefore detailed description will not be repeated.

The redundancy mode decode circuit 314 is provided in the
4. A hardware configuration or a software configuration can be used by using a combination of logic gates that can obtain the decoding results shown in FIGS. 35 and 46.

According to the structure of the second modification of the fourth embodiment, two redundant internal data lines SDBA and SDB
A test mode for checking whether there is a defect corresponding to B can be set.

[Third Modification of Fourth Embodiment] In the fourth embodiment, in order to replace a defective data line with a redundant internal data line in an IO selection section, the data is programmed in a nonvolatile manner by a fuse or the like. Depending on the position information, bus width setting, and column address related to the defective data line
Connections between the internal data lines and the external data lines are sequentially switched. Therefore, once the program relating to the defective data line is performed, it becomes very difficult to analyze the failure of the internal data line based on the data output to the external data line. Therefore, in the third modification of the fourth embodiment, according to the instruction, the internal data lines DB0 to DB31 and the external data lines DQ0 to DQ corresponding to the normal data line pair are provided.
A test mode for establishing a connection with the G.31 in a predetermined relationship will be described.

In the third modification of the fourth embodiment,
The configuration of each of the IO selection circuits included in the IO selection unit 304 shown in FIG. 29 is different from that of the fourth embodiment.

An example of the configuration of IO selection circuit ZDk (k: 0 to 7) according to the third modification of the fourth embodiment will be described with reference to FIG.

In comparison with IO selection circuit ZAk according to the fourth embodiment, IO selection circuit ZDk is redundant mode decoding circuit 315 instead of redundant mode decoding circuit 311.
Is different. The configuration of other portions of IO selection circuit ZDk is similar to that of IO selection circuit ZAk, and therefore, detailed description will not be repeated.

Redundant mode decode circuit 315 further receives test mode signal TM3 as compared with redundant mode decode circuit 311.

When test mode signal TM3 is set to "L", redundant mode decode circuit 313, like redundant mode decode circuit 311, outputs the status signal (NRM, SFTA, SFTB, RETB) of the corresponding block.
DA, REDB, REDAB).

In the test mode, when an operation test is performed by setting test mode signal TM3 to "H", LSELA <3: 0> and LSELB <3: 0
> May be either “1” or “0” (“Don't care” state).

Referring to FIG. 48, when the test mode signal TM3 is set to "H", the redundancy mode decode circuit 315 sets the status signal NRM to "1" in each of the blocks 0 to 7. .

As a result, in each of blocks 0 to 7, the shift operation and the replacement operation are not performed, and the corresponding internal data line and external data line are connected directly. That is, external data lines DQ0 to DQ31 are connected to internal data lines DB0 to DB3 corresponding to the normal data line pair.
1 respectively.

Structures and operations other than the IO selection circuit are the same as those of the fourth embodiment, and therefore detailed description will not be repeated.

The redundant mode decode circuit 315 is provided in
4. It can be configured as hardware or software using a combination of logic gates that can obtain the decoding results shown in FIGS. 35 and 48.

According to the configuration according to the third modification of the fourth embodiment, a test mode in which an internal data line corresponding to a normal data line pair can be accessed from a predetermined external data line can be set. it can. As a result, even after the information on the defective data line is programmed, the failure analysis can be efficiently executed.

[Fifth Embodiment] A semiconductor memory device according to a fifth embodiment will be described. Also in the fifth embodiment, the number of redundant data line pairs is set to 2 (SLIOA,
/ SLIOA and / SLIOB, / SLIOB) can replace two defective data lines at the same time. Further, similarly to the fourth embodiment, the number of normal data line pairs is set to 32 (LIO (i), / LIO (i); i = 0 to 3).
1), and as data line configurations, × 32, × 1
6, x8 can be switched, and in the case of the x16, x8 configuration, selection of a data line is performed using a column address.

Referring to FIG. 49, the semiconductor memory device 4000 according to the fifth embodiment differs from the semiconductor memory device 3000 according to the fourth embodiment in that the IO selecting unit 30
4 in that an IO selection unit 404 including IO selection circuits ZE0 to ZE7 and a redundancy selection signal generation circuit 406 are provided in place of 4 and the redundancy selection signal generation circuit 306.

The IO selection section 404 selects an internal data line to be used according to the bus width (column address) and the presence or absence of redundant use. IO selecting section 404 has a different configuration from IO selecting section 304 according to the fourth embodiment in order to replace defective data lines by a shift operation using redundant internal data lines SDBA and SDBB in each IO selecting circuit. Have.

In the fifth embodiment, internal data lines DB (0) to DB (31) are divided into eight sets. Further, redundant internal data lines SDBA and SDBB
Is shared between each block.

The IO selection circuit ZE0 is connected to the external data line DQ
An external data line used among (0) to DQ (3) and four used among internal data lines DB (0) to DB (3) and redundant internal data lines SDBA and SDBB are electrically coupled. The IO selection circuit ZAi (block i) includes an external data line to be used among the external data lines DQ (4 × i) to DQ (4 × i + 3) and an internal data line DB (4 × i) to
DB (4 × i + 3) and redundant internal data line SDBA,
Four of the SDBBs to be used are electrically coupled (i.
= 1-7).

Bus width and bus width selection signal BUSSEL <
2: 0>, external data line (data input / output pin) to be used, column address and address decode signal YS
The relationship with EL <3: 0> has already been described, and thus detailed description will not be repeated.

The redundancy selection signal generation circuit 406 stores the position of a normal data line requiring redundancy replacement, and generates a decode signal according to the stored contents. The decoded signal is called a replacement data line position signal, and the upper bit signal
BLOCKA <7: 0> (= UFBLOCKA (0) to
UFBLOCKKA (7)), UFBLOCKB <7: 0
> (= UFFBLOCK (0) to UFBLOCKKB
(7)). Each of the signals UFBLOCKA <7: 0> and UFBLOCKB <7: 0> indicates the presence of a defective data line in IO selection circuit units (block units).

For the lower bit signals of the replacement data line position signal, LSELA <3: 0> and LSELB <3: 0>, which of the four corresponding data lines in the IO selection circuit unit are defective. Indicates

As a result, upper bit signal UFBLOCK
A <7: 0> and lower bit signal LSELA <3: 0>
> Indicates one defective data line, and the upper bit signal UFBLOCKB <7: 0> and the lower bit signal LSELB <3: 0> indicate another other defective data line.

In the fifth embodiment also, one of the two defective data lines having the smaller index number (i) (ie, the lower one) has the signal UFBLOCKKA.
The other, indicated by <7: 0> and LSELA <3: 0>, having the larger index number (i) (ie, the upper side) is the signal UFBLOCKB <7: 0> and L
Let it be indicated by SELB <3: 0>.

When UFBLOCKA <7: 0> and UFBLOCKB <7: 0> are collectively referred to, they are simply referred to as UFBLOCKKA and UFBLOCKKB, respectively.

FIGS. 50 and 51 show the setting of the replacement data line position signal corresponding to the position of the defective data line.

Referring to FIG. 50, the defective data line belongs to block k (the defective data line belongs to IO selection circuit ZA).
k is one of the four data lines)
Signals UFBLOCKKA (k) and UFBLOCKKB
(K) becomes "1", and the others become "0". When there is no defect, the signals UFBLOCKA <7: 0> and UFBLOCKA <7: 0>
All bits of BLOCKB <7: 0> are “0”.

Referring to FIG. 51, if the internal data line (i + k) among the internal data lines DB (i) to DB (i + 3) to which one block belongs is defective, the signal LSELA
Of the signals (0) to LSELA (3), the signal LSELA
(0) to LSELA (k) become "1", and the others become "0". On the other hand, if the internal data line (i + k) is defective, the signals LSELB (k) to LSELB (3) among the signals LSELB (0) to LSELB (3) are “1”.
And the others become "0".

The redundancy selection signal generation circuit 406 uses a fuse in order to store the position of the data line that needs to be replaced, similarly to the redundancy selection signal generation circuit 306 described with reference to FIG. The position information is stored by blowing (or not blowing) the fuse in accordance with the position.
Note that the configuration of the redundancy selection signal generation circuit 406 also
Not limited to fuses.

The structure of the other parts of semiconductor memory device 4000 is similar to that of semiconductor memory device 300 according to the third embodiment.
Since it is the same as 0, detailed description will not be repeated.

An example of the configuration of IO selection circuit ZEk included in IO selection section 404 will be described with reference to FIG. IO
The selection circuit ZEk includes an IO switching circuit 410 and an IO line switching signal generation circuit 412.

The IO switching circuit 410 has an internal data line DB
(I) to DB (i + 3), SABB and SABB,
External data lines DQ (i), DQ (i + 1), DQ (i +
Switch connection between 2) and DQ (i + 3).

The switching in the IO switching circuit 410
Selection signal DQS output from O line switching signal generation circuit 412
ELL <3: 0> (= DQSELL (0) to DQSEL
L (3)), DQSELC <3: 0> (= DQSELC
(0) to DQSELC (3)) and DQSELR <
3: 0> (= DQSELR (0) to DQSELR (3)
Is controlled by

In the following, selection signal DQSELC <
3: 0>, DQSELL <3: 0> and DQSELL
When collectively referring to <3: 0>, they are also simply referred to as selection signals DQSELC, DQSELL, and DQSELR, respectively.

FIG. 53 shows an example of the IO switching circuit 410. The IO switching circuit 410 includes selection circuits 1401 to 140
4, switches 1201-1203 and input / output buffers BF0-BF3 arranged for external data lines DQ (i) -DQ (i + 3), respectively.

The selection circuits 1401 to 1404 perform the shift operation of the internal data line for replacing the defective data line by selecting signals DQSELC <3: 0> and DQSELL <3: 0.
> And DQSELR <3: 0>.

The selection circuit 1401 outputs the selection signal DQSEL
C (0), DQSELL (0) and DQSELR
(0), and the selection circuit 1402 outputs the selection signals DQSELC (1), DQSELL (1) and DQSELC (1).
It operates based on SELR (1). Similarly, the selection circuit 1403 outputs selection signals DQSELC (2), DQSEL
Operate based on L (2) and DQSELR (2),
The selection circuit 1404 outputs selection signals DQSELC (3), D
It operates based on QSELL (3) and DQSELR (3).

In each selection circuit, selection signal DQSEL
One of C, DQSELL, and DQSELL is set to “1”, and the other two are set to “0”. When the selection signal DQSELC is set to “1”, it indicates that the corresponding internal data line in the same block is used. On the other hand, when the redundant internal data line SDBA or SDBB is used for the replacement operation, the selection signal DQSELL or DQSELL is set to “1”.

Referring to FIG. 54, selecting circuits 1401-1 to 140-1
Each of 404 is an output node No. and an internal data line DB.
(I) to corresponding internal data line D among DB (i + 3)
B (j) (j = i to i + 3), a transfer gate 1407, an output node No and an internal data line DB (j-1) (or a redundant internal data line SDBA)
And a transfer gate 1408 provided between the output node No and the internal data line DB (j + 1) (or the redundant internal data line SDBB). The output node Nos.
Respectively.

Transfer gates 1406 to 1408
Is similar to that shown in FIG. Therefore, transfer gate 1406 connects internal data line DB (j-1) (or redundant internal data line SDBA) and output node No when corresponding selection signal DQSELL is set to H level ("1"). Electrically coupled. Similarly, transfer gate 1407 electrically couples internal data line DB (j) to output node No when corresponding select signal DQSELC is set to H level ("1"). Transfer gate 1408 is
When corresponding selection signal DQSELR is set to H level ("1"), internal data line DB (j + 1) (or redundant internal data line SDBB) and output node No are electrically coupled.

Referring again to FIG.
-1203 and input / output buffers BF0-BF3 are the same as those described in the third embodiment, and therefore, detailed description will not be repeated.

Referring again to FIG. 52, IO selection circuit ZE
k, the I / O line switching signal generation circuit 412 includes 1-bit UFBLOCKA (k) and UFBLO corresponding to the corresponding block among the upper bits of the replacement data line position signal.
CKB (k), lower bit LS of replacement data line position signal
ELA <3: 0>, LSELB <3: 0> and the address decode signal YSEL <3: 0> are decoded to select signals DQSELL <3: 0> and DQSELC <3: 0.
> And DQSELR <3: 0>.

The control state in each block (IO selection circuit) corresponds to the corresponding signals UFBLOCKKA and UF
It indicates which of the following four types corresponds to BLOCKB.

(1) No defective data line is included (UFB
LOCKA = UFBLOCKB = "0": control state (A)), (2) A shift operation is performed to the lower side using one redundant data line and using the redundant internal data line SDBA (UFBLOCKA = "1"). , UFBLOCKB =
“0”: control state (B)) (3) Shift operation to the upper side is performed using redundant internal data line SDBB including one defective data line (UFBLOCKA =
“0”, UFBLOCKKB = “1”: control state (C)), and (4) a shift operation is performed using redundant internal data lines SDBA and SDBB including two defective data lines (UFBLOCKA = UFBLOCKKB).
= “1”: control state (D)).

Next, the operation of IO line switching signal generation circuit 412 will be described with reference to FIGS. FIG.
57 to FIG. 57 show input signals to IO line switching signal generation circuit 412 and output signals DQSELC <3: 0> and DQSELL <
3: 0> and DQSELR <3: 0>.

FIG. 55 shows an n / 4-bit mode,
Corresponds to the n / 2-bit mode, and FIG. 57 corresponds to the n-bit mode.

Referring to FIGS. 55-57, in control state (A), signals DQSELC (0) -DQSELC
LC (3) takes the same value as signals YSEL (0) to YSEL (3), and signals DQSELL (0) to DQSELL
(3), DQSELR (0) to DQSELR (3) = 0
become.

[0279]

In control state (B), the corresponding data line for which LSELA (j) = 1 (j: 0 to 3) and the data line lower than the data line are set to the lower side ( (To the SDBA side) with an internal data line. Therefore, Y
When LSELA (j) = 1 corresponding to the data line selected by SEL (j) = 1, DQSELL
(J) = 1 and DQSELC (j) = 0.

On the other hand, a data line higher than the data line is connected to an internal data line without shifting. Therefore, when LSELA (j) = 0 corresponding to the data line selected by YSEL (j) = 1, DQSEL
L (j) = 0 and DQSELC (j) = 1 are set.
In the control state (B), DQSELR
(0) to DQSELR (3) = 0.

[0281]

In control state (C), the corresponding data line for which LSELB (j) = 1 (j: 0 to 3) and the data line higher than the data line are set to the upper side ( (SDBB side) and are connected to internal data lines, respectively. Therefore, Y
When LSELB (j) = 1 corresponding to the data line selected by SEL (j) = 1, DQSELR
(J) = 1 and DQSELC (j) = 0.

On the other hand, the data lines lower than the data line are connected to the internal data lines without shifting. Therefore, when LSELB (j) = 0 corresponding to the data line selected by YSEL (j) = 1, DQSEL
R (j) = 0 and DQSELC (j) = 1 are set.
In the control state (C), DQSELL
(0) to DQSELL (3) = 0.

[0283]

In control state (D), the corresponding data line for which LSELA (j) = 1 (j: 0 to 3) and the data line lower than the data line are set to the lower side ( (To the SDBA side) with an internal data line. Therefore, Y
When LSELA (j) = 1 corresponding to the data line selected by SEL (j) = 1, DQSELL
(J) = 1, DQSELC (j) = 0, and DQSE
LR (j) = 0 is set.

Similarly, corresponding LSELB (j) = 1
The data line set to (j: 0 to 3) and the data line higher than the data line are connected to the internal data lines with a shift operation to the higher side (SDBB side). Therefore, when LSELB (j) = 1 corresponding to the data line selected by YSEL (j) = 1, DQSELR (j) = 1 and DQSELC (j) = 0
And DQSELL (j) = 0.

On the other hand, when both LSELA (j) and LSELB (j) corresponding to the data line selected by YSEL (j) = 1 are “0”, the data line is not shifted. Connected to internal data line. That is, DQSELR (j) = 0, DQSELC (j) =
1 and DQSELL (j) = 0.

The address decode signals YSEL <3: 0> in the remaining bits of the select signals DQSELR, DQSELC and DQSELL, that is, in the corresponding bits.
Bits set to “0” are set to “0”.

Note that signals YLSELA and LSELB
Are associated with the lower side and the upper side of the two defective data lines, respectively, so that the combinations of the positions of the defective data lines in each block are limited to those shown in FIGS.

The IO line switching signal generation circuit 412 operates as shown in FIG.
It can be configured in hardware using a combination of logic gates that can obtain the decoding results shown in .about.58, or can be configured in software.

Here, the operation of semiconductor memory device 3000 will be described by taking as an example a case where "× 8", that is, the n / 4 bit mode is designated as the data line configuration. A defect exists in a memory cell corresponding to normal data lines LIO (9) and LIO (27), and normal data line LIO
(9) and LIO (27) are to be replaced.

FIG. 58 shows the states of control signals in each IO selection circuit. Since the defective data line, that is, the normal data line to be replaced exists in each of the blocks 2 and 6, UFBLOCKA (2) = UFB
LOCKB (6) is set to "1" and the remaining UFBL
OCKA (1), UFBLOCKA (3)-UFBLO
CKA (7), UFBLOCK (0)-UFBLOC
KB (5) and UFBLOCKKB (7) are set to “0”.

The upper bits (UFBLOCKA, UFBLOCKB) of the corresponding replacement data line position signal are all "0", that is, in blocks 0, 1, 3, 4, 5, and 7 where no defective data line exists, There is no need to shift the data lines. Therefore, the numbers assigned to the internal data lines DB and the external data lines DQ are the same. In these blocks, signals SDQSELL and DQSELR are all fixed to “0” regardless of CAD <1: 0>, and one of signals DQSELC is set to C
It becomes "1" according to AD <1: 0>.

In the block 2 in which the upper bit UFBLOCKA of the corresponding replacement data line position signal is "1", that is, in the block 2 in which the lower defective data line exists, FIG.
As shown in (a), when the external data line DQ9 corresponding to the defective data line is selected by CA <1: 0>, the external data line DQ9 is shifted by one to the lower side, and
Are connected to the internal data line DB (8).

As shown in FIG. 59B, the same applies to the case where external data line DQ8 lower than external data line (DQ9) corresponding to a defective data line is selected by CA <1: 0>. When the shift operation is performed, the external data line D
Q8 is connected to redundant internal data line SDBA. That is, the internal data line DB (9), which is a defective data line,
Instead of being directly replaced by the redundant internal data line SDBA, it is replaced by a shift operation.

As described above, when the external data line DQ (9) corresponding to the defective data line or the DQ (8) downstream thereof is to be accessed, that is, when the column address C
When AD <1: 0> = "00" or "01", the selection signals DQSELC (0) to DQSELC (3)
Is set to “0”, and the selection signal DQSELL (0) or DQSELL is used to perform the shift operation on the downstream side.
(1) is set to “1”.

The other external data lines DQ (1
0) or DQ (11) to be accessed, that is, column address CAD <1: 0> = “1”.
In the case of “0” or “11”, the selection signal DQSEL
L, DQSELC, and DQSELR are set in the same manner as a block having no defective data line. That is, signals SDQSELL and DQSELR are all fixed to “0”, and one of signals DQSELC is set to CAD <1:
0> in accordance with 0>.

In the block 6 in which the upper bit UFBLOCKB of the corresponding replacement data line position signal is "1", that is, in the block 6 in which the upper-side defective data line exists, FIG.
As shown in (c), when the external data line DQ27 corresponding to the defective data line is selected by CA <1: 0>, the external data line DQ27 is shifted upward by one and the external data line DQ27 is shifted.
27 is connected to redundant internal data line SDBB. If other external data lines exist above the external data line corresponding to the defective data line in the same block, a similar shift to the upper side is performed for these external data lines. The operation is performed.

As shown in FIG. 59 (d), when external data line DQ26 lower than external data line (DQ27) corresponding to a defective data line is selected by CA <1: 0>, shift is performed. No operation is performed and the external data line D
Q26 is connected to internal data line DB (26).

External data line DQ corresponding to the defective data line
When (27) is to be accessed, that is, when the column address CAD <1: 0> = "11", the selection signals DQSELC (0) to DQSELC (3) are set to "0".
, And the selection signal DQSELR (3) is set to "1" in order to perform the shift operation on the downstream side. If other external data lines exist above the external data line corresponding to the defective data line, the selection signal DQSELL,
DQSELC and DQSELR are set similarly.

The other external data lines DQ (2
4) to DQ (26) to be accessed, that is, column address CAD <1: 0> = "00",
In the case of “01” or “10”, the selection signal DQS
ELL, DQSELC, and DQSELR are set in the same manner as a block having no defective data line. That is,
Signals SDQSELL and DQSELL are all "0"
Fixed and one of the signals DQSELC is CAD <
1: 0>.

As a result, block 2 (IO selection circuit ZA)
In 2), the internal data line DB (9) which is a defective data line
Are not used, and a shift operation using the redundant internal data line SDBA is performed. Similarly, in block 6 (IO selection circuit ZA6), internal data line DB (27), which is a defective data line, is not used and redundant internal data line SD
A shift operation using BB is performed. On the other hand, no shift operation is performed in a block where no defective data line exists.

The operation of semiconductor memory device 4000 at the time of read operation and write operation is performed according to IO selection circuits ZE0 to ZE0.
Except for the connection between internal data lines DB, SDBA, SDBB and external data line DQ in E7, it is the same as semiconductor memory device 2000 according to the third embodiment, and therefore detailed description will not be repeated.

According to the configuration according to the fifth embodiment, the data line selection circuit and the redundancy replacement circuit are shared, and a shift redundancy system is combined in units of blocks to switch the bus width in a multi-data line configuration. In such a semiconductor memory device, high-speed data transfer can be performed, and two defective data lines can be simultaneously replaced, so that redundancy efficiency can be improved. Further, selection signals (DQSELL, DQSEL) in each IO selection circuit are provided.
C, DQSELR) in comparison with the third embodiment,
Can be easily generated.

Further, the number of external data lines connected to the redundant internal data line can be reduced as compared with the configuration in which each internal data line is directly replaced with the redundant internal data line. As a result,
High-speed data transfer can be performed by reducing the parasitic capacitance of the redundant internal data line.

[Modification 1 of Fifth Embodiment] In Modification 1 of the fifth embodiment, the redundant data line pair 102 (SL
(IOA, / SLIOA and SLIOB, / SLIOB)
Is different from that of the fourth embodiment.

Referring to FIG. 60, semiconductor memory device 4100 according to the first modification of the fifth embodiment differs in that redundant data line pair 102 is arranged at the center of memory array MA. In the configuration example of FIG. 60, two redundant data line pairs S
LIOA, / SLIOA and SLIOB, / SLIOB
Are arranged between normal data line pairs LIO15, / LIO15 and LIO16, / LIO16.

The structure of other portions of semiconductor memory device 4100 is the same as that of IO selecting circuit ZAk, and therefore detailed description will not be repeated.

With the configuration according to the first modification of the fifth embodiment, the same effect as that of the fifth embodiment can be obtained.

[Modification 2 of Fifth Embodiment] In Modification 2 of the fifth embodiment, semiconductor memory devices 4000 and 410 according to the fifth embodiment and Modification 1 thereof.
The setting of a test mode for performing an operation test on 0 will be described.

[0309] In Modification 2 of the fifth embodiment,
The configuration of each of the IO selection circuits included in the IO selection unit 404 shown in FIG. 49 is different from that of the fifth embodiment.

An example of the configuration of IO selection circuit ZFk (k: 0 to 7) according to the second modification of the fifth embodiment will be described with reference to FIG.

The IO selection circuit ZFk is different from the IO selection circuit ZEk according to the fifth embodiment in that an IO line switching signal generation circuit 412 is used instead of the IO line switching signal generation circuit 412.
Is different. Other configurations of IO selection circuit ZFk are similar to those of IO selection circuit ZEk, and therefore, detailed description will not be repeated.

[0312] IO line switching signal generation circuit 413 receives test mode signal TM4 as compared with IO line switching signal generation circuit 412.

When test mode signal TM4 is set to "L", IO line switching signal
Similarly to the line switching signal generation circuit 412, the selection signals DQSELL <3: 0>, DQSELC <
3: 0> and DQSELR <3: 0>.

Referring to FIG. 62, in the test mode, when an operation test is performed by setting test mode signal TM4 to "H", LSELA (0) =
LSELB (0) is set to "1" and LSELA
(1) to LSELA (3) = LSELB (1) to LSE
LB (3) is set to "0".

Referring to FIG. 63, when test mode signal TM4 is set to "H", IO line switching signal generation circuit 413 determines that UFBLOCKA (7) = UFBLOCKKB
(0) = "1" and the remaining bits UF
BLOCKA (0)-UFBLOCKA (6), UFB
LOCKKB (1) to UFBLOCKKB (7) are set to "0".

As a result, a shift operation is performed in block 0, and internal data line DB (0) is replaced by redundant internal data line SDBA. Therefore, external data line DQ (0) and redundant internal data line SDBA are connected. Similarly, a shift operation is performed in block 7, and internal data line DB (28) is replaced by redundant internal data line SDBB. Therefore, external data line DQ (28) and redundant internal data line SDBB are connected.

The IO line switching signal generation circuit 413 operates as shown in FIG.
63 and a combination of logic gates that can obtain the decoding results shown in FIG. 63 can be implemented in hardware or software.

As described above, in two of the plurality of blocks, the shift operation using the redundant internal data line SDBA and the shift operation using the redundant internal data line SDBB are forcibly executed, respectively. A test mode allowing direct access to internal data lines SDBA and SDBB can be set.

According to the structure according to the second modification of the fifth embodiment, two redundant internal data lines SDBA and SDB
A test mode for confirming whether there is a defect corresponding to B or whether the data input / output speed changes by using the redundant internal data line can be set.

It should be noted that the embodiment disclosed this time is an example in all respects and is not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description of the embodiments, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0321]

According to the semiconductor memory device of the present invention, in a semiconductor memory device having redundant data lines, the execution of the data line shift redundant system and the selection of the data line specified by the address can be performed simultaneously. Therefore, high-speed data transfer can be performed.

Further, according to the semiconductor memory device of the present invention, in a semiconductor memory device having a redundant data line, a data line replacement operation and a data line selection operation can be performed simultaneously, so that high-speed data transfer is performed. be able to.

Further, according to the semiconductor memory device of the present invention, the data line selection circuit and the redundancy replacement circuit are shared.
By combining the shift redundancy scheme in units of blocks, it becomes possible to perform high-speed data transfer in a semiconductor memory device capable of switching the bus width.

Further, according to the semiconductor memory device of the present invention, the data line selection circuit and the redundancy replacement circuit are shared, and the shift redundancy system is combined in units of blocks.
In a semiconductor memory device having a multi-data line configuration and capable of switching the bus width, high-speed data transfer can be performed, and redundancy efficiency can be increased because two defective data lines can be replaced at the same time. it can.

Further, since the shift operation can be forcibly executed in all the blocks in response to the test mode signal, a test mode for confirming the data line switching function in each switching circuit constituting the data line switching circuit is set. can do.

Further, a test mode for simultaneously accessing both of the two redundant data lines and confirming whether or not there is a defect corresponding to the redundant data line can be set.

Further, even after the storage information relating to the defective data line is programmed, a test mode in which the data lines excluding the redundant data line, ie, the normal data lines, can be respectively accessed from predetermined external data lines is set. Therefore, internal failure analysis can be executed efficiently.

According to the semiconductor memory device of the present invention, the data line selection circuit and the redundancy replacement circuit are shared, and the shift redundancy scheme is combined in units of blocks,
In a semiconductor memory device having a multiple data line configuration and a switchable bus width, two defective data lines can be replaced at the same time, so that redundancy efficiency can be increased. Further, since the shift operation is performed only in the block in which the defective data line exists, the control of the data line switching in the data line switching circuit can be relatively easily performed. Further, the number of external data lines connected to the redundant data lines can be reduced as compared with a configuration in which each data line is directly replaced with a redundant data line. As a result, the parasitic capacitance of the internal redundant data line can be reduced, and high-speed data transfer can be performed.

Further, since a test mode in which the redundant data line can be directly accessed can be set, whether there is a defect corresponding to the redundant data line or whether the data input / output speed changes by using the redundant internal data line. Etc. can be easily confirmed.

[Brief description of the drawings]

FIG. 1 is a semiconductor memory device 10 according to a first embodiment;
It is a block diagram showing the outline of composition of 00.

FIG. 2 is a block diagram illustrating a configuration of an IO selection unit 107 according to the first embodiment.

FIG. 3 is a diagram for explaining a 1/4 selection circuit and a shift decoder according to the first embodiment.

FIG. 4 shows a shift decoder SX according to the first embodiment.
It is a figure for explaining operation of i, SYi.

FIG. 5 is a diagram for explaining a relationship between a defective data line identification signal FS (i) and a defective data line.

FIG. 6 is a diagram showing signals input to the 1/4 selection circuits when the normal data line LIO (3) is defective in the first embodiment.

FIG. 7 shows a semiconductor memory device 15 according to a second embodiment.
It is a block diagram showing the outline of composition of 00.

FIG. 8 is a block diagram illustrating a configuration of an IO selection unit 157 according to a second embodiment.

FIG. 9 is a diagram for describing a 選 択 selection circuit and a decoder according to a second embodiment.

FIG. 10 shows a decoder SZi,
FIG. 9 is a diagram for explaining the operation of SWi.

FIG. 11 is a diagram for explaining a relationship between a defective data line replacement signal RS (i) and a defective data line.

FIG. 12 is a diagram showing signals input to the 1/4 selection circuits when a normal data line LIO (3) is defective in the second embodiment.

FIG. 13 shows a semiconductor memory device 2 according to a third embodiment.
000 is a block diagram showing the outline of the configuration of FIG.

FIG. 14 is a diagram showing a relationship between a bus width, a column address, and an address decode signal YSEL <3: 0>.

FIG. 15 is a diagram showing a relationship between a bus width and an external data line (data input / output pin) to be used.

FIG. 16 is a block diagram illustrating an example of a configuration of an IO selection circuit Zk included in the IO selection unit 204.

17 is a configuration diagram illustrating an example of an IO switching circuit 210. FIG.

FIG. 18 is a circuit diagram illustrating an example of a configuration of a transfer gate.

FIG. 19 is a diagram illustrating a relationship between a bus width and switch switching.

FIG. 20 shows a block including a defective data line and a signal US
FIG. 14 is a diagram showing a relationship between EL <7: 0> and status signals of each block.

FIG. 21 is a circuit diagram showing an example of a configuration of a redundancy mode decoding circuit 211.

FIG. 22 is a diagram for explaining an operation of the IO line switching signal generation circuit 212.

FIG. 23 is a diagram for explaining the operation of the IO line switching signal generation circuit 212.

FIG. 24 is a diagram for explaining the operation of the IO line switching signal generation circuit 212.

FIG. 25 shows a position of a defective data line and a signal LSEL <3:
FIG.

FIG. 26 is a diagram showing a circuit 260 included in the IO line switching signal generation circuit 212.

FIG. 27 is a diagram showing a circuit 270 included in the IO line switching signal generation circuit 212.

FIG. 28 shows a semiconductor memory device 2 according to a third embodiment.
000 is a diagram showing an example of the operation of FIG.

FIG. 29 is a semiconductor memory device 3 according to a fourth embodiment.
000 is a block diagram showing the outline of the configuration of FIG.

FIG. 30 shows bus width setting and bus width selection signal BUSSE.
It is a figure showing the relation with L <2: 0>.

FIG. 31 is a block diagram illustrating an example of a configuration of an IO selection circuit ZAk included in an IO selection unit 304.

32 is a configuration diagram illustrating an example of an IO switching circuit 310. FIG.

FIG. 33 shows a selection circuit 1 included in the IO switching circuit 310.
It is a block diagram which shows an example of each of 301-1304.

FIG. 34 shows a block including a defective data line and a signal US.
It is a figure which shows the relationship between each of ELA <7: 0> and USELB <7: 0>, and the status decode intermediate signal of each block.

FIG. 35 is a diagram showing a correspondence between a status decode intermediate signal and a status signal.

FIG. 36 is a diagram illustrating a decoding result of a status signal of each block when a defective data line exists in blocks 2 and 6;

FIG. 37 is a diagram for explaining the operation of the IO line switching signal generation circuit 312.

FIG. 38 is a diagram for explaining the operation of the IO line switching signal generation circuit 312.

FIG. 39 is a diagram illustrating the operation of the IO line switching signal generation circuit 312.

FIG. 40 is a diagram showing a relationship between a position of a defective data line and a state of a control signal in each IO selection circuit.

FIG. 41 is a block diagram showing an example of a configuration of an IO selection circuit ZBk according to a first modification of the fourth embodiment.

FIG. 42 shows signals LSELA <3: 0> and LS in a test mode according to the first modification of the fourth embodiment.
It is a figure explaining the setting of ELB <3: 0>.

FIG. 43 is a diagram showing setting of a status signal of each block in a test mode according to a first modification of the fourth embodiment.

FIG. 44 is a block diagram showing an example of a configuration of an IO selection circuit ZCk according to a second modification of the fourth embodiment.

FIG. 45 shows signals LSELA <3: 0> and LS in a test mode according to the second modification of the fourth embodiment.
It is a figure explaining the setting of ELB <3: 0>.

FIG. 46 is a diagram illustrating setting of a status signal of each block in a test mode according to a second modification of the fourth embodiment.

FIG. 47 is a block diagram showing an example of a configuration of an IO selection circuit ZDk according to a third modification of the fourth embodiment.

FIG. 48 is a diagram showing setting of a status signal of each block in a test mode according to a third modification of the fourth embodiment.

FIG. 49 shows a semiconductor memory device 4 according to a fifth embodiment.
000 is a block diagram showing the outline of the configuration of the 000.

FIG. 50 is a diagram showing setting of upper bits UFBLOCKA <7: 0> and UFBLOCKB <7: 0> of a replacement data line position signal corresponding to the position of a defective data line.

FIG. 51 shows lower bits LSELA <3: 0> and L of a replacement data line position signal corresponding to the position of a defective data line
It is a figure showing the setting of SELB <3: 0>.

FIG. 52 is a block diagram illustrating an example of a configuration of an IO selection circuit ZEk included in the IO selection unit 404.

FIG. 53 is a configuration diagram illustrating an example of an IO switching circuit 410.

54 shows a selection circuit 1 included in an IO switching circuit 410.
It is a block diagram which shows an example of each of 401-1404.

FIG. 55 is a diagram illustrating the operation of the IO line switching signal generation circuit 412.

FIG. 56 is a diagram for explaining an operation of the IO line switching signal generation circuit 412.

FIG. 57 is a diagram for explaining the operation of the IO line switching signal generation circuit 412.

FIG. 58 is a diagram showing a relationship between a position of a defective data line and a state of a control signal in each IO selection circuit.

FIG. 59 is a conceptual diagram showing a shift operation in a block where a defective data line exists.

FIG. 60 is a block diagram showing an outline of a configuration of a semiconductor memory device 4100 according to a first modification of the fifth embodiment.

FIG. 61 is a block diagram showing an example of a configuration of an IO selection circuit ZFk according to a second modification of the fifth embodiment.

FIG. 62 shows signals LSELA <3: 0> and LS in a test mode according to the second modification of the fifth embodiment.
It is a figure explaining the setting of ELB <3: 0>.

FIG. 63 shows upper bits UFBLOCKA <7: 0> and UFBLOCKKB <of a replacement data line position signal in a test mode according to the second modification of the fifth embodiment.
7: 0> FIG.

FIG. 64 is a block diagram schematically showing a configuration of a conventional semiconductor memory device 5000.

FIG. 65 is a diagram for describing an outline of a configuration of a conventional IO selection circuit 503;

FIG. 66 is a diagram showing an outline of the configuration of a conventional IO shift circuit 505.

[Explanation of symbols]

MA memory cell array, 101, LIO (i), / L
IO (i) Normal data line pair, 102, SLIO
(I), / SLIO (i) redundant data line pair, 103,
202 row decoder, 104 column address decoder, 105 data line switching circuit, 106, 156 defective data line storage circuit, 107, 157, 204, 304,
404 IO selection unit, 108 IO shift decoder, 1
09,203 read amplifier / write driver, RW
Read amplifier / write driver, 158 permutation decoder, X0-Xn, Y0-Yn 1/4 selection circuit, SX0
SXn, SY0 to SYi shift decoder, SZ0
SZn, SW0-SWi decoder, Z0-Z7, ZA
0 to ZA7, ZB0 to ZB7, ZC0 to ZC7, ZD0
To ZD7, ZE0 to ZE7, ZF0 to ZF7 IO selection circuit, 206, 306, 406 redundancy selection signal generation circuit, 207, 307 data line selection signal generation circuit, 21
0 IO switching circuit, 211, 311, 313, 314,
315 redundant mode decode circuit, 212, 312, 4
12,413 IO line switching signal generation circuit, 1000,1
500, 2000, 3000, 4000, 4100 semiconductor memory devices.

Claims (18)

[Claims] A memory cell array including a plurality of memory cells arranged in a matrix; a plurality of data lines including a redundant data line for reading data from or writing data to the memory cell array; A plurality of external data lines for transmitting and receiving data, and a data line to be coupled to the plurality of external data lines in accordance with an external address and storage information on a defective data line included in the plurality of data lines. And a data line switching circuit for simultaneously executing a shift operation for shifting a connection between the plurality of external data lines and the coupled data line. 2. The plurality of data lines are divided into a plurality of blocks, the data line switching circuit includes a decoder for decoding the external address and the storage information, the plurality of blocks and the plurality of external data lines. And a plurality of selection circuits arranged between each of the plurality of selection circuits, wherein each of the plurality of selection circuits shares some data lines with the selection circuits adjacent to each other and according to an output of the decoder. 2. The semiconductor memory device according to claim 1, wherein the selecting operation and the shifting operation are performed simultaneously. 3. Each of the plurality of selection circuits includes a plurality of transfer gates provided between a corresponding data line and a corresponding external data line, and opened and closed according to an output of the decoder. 3. The semiconductor memory device according to claim 1. 4. A memory cell array including a plurality of memory cells arranged in a matrix, a plurality of data lines including a redundant data line, and reading or writing data from the memory cell array; And a plurality of external data lines for transmitting and receiving data, a selecting operation of selecting a data line to be coupled to the plurality of external data lines in accordance with an external address, and a data line to be coupled in accordance with replacement information And a data line switching circuit for simultaneously executing a replacement operation for replacing the defective data line and the redundant data line included in the semiconductor memory device. 5. The plurality of data lines further include a plurality of normal data lines, the plurality of normal data lines are divided into a plurality of blocks, and the data line switching circuit comprises: And a plurality of selection circuits disposed between each of the plurality of blocks and the plurality of external data lines, each of the plurality of selection circuits corresponding to the redundant data line. 5. The semiconductor memory device according to claim 4, wherein said selecting operation and said replacing operation are performed simultaneously on a normal data line. 6. A plurality of transfer circuits each provided between the redundant data line and the corresponding normal data line and a corresponding external data line, and each of the plurality of transfer circuits is opened and closed according to an output of the decoder. 6. The semiconductor memory device according to claim 5, including a gate. 7. A memory cell array including a plurality of memory cells arranged in a matrix, a plurality of data lines including a redundant data line, and for reading data from or writing data to the memory cell array; A plurality of external data lines for transmitting and receiving data, a selection operation of selecting a data line to be coupled to the external data line to be used according to a bus width, and a defective data line included in the plurality of data lines. A semiconductor memory device, comprising: a data line switching circuit that simultaneously performs a shift operation of shifting a connection between the used external data line and the coupled data line in accordance with storage information. 8. Each of the plurality of data lines and the plurality of external data lines is divided into a plurality of blocks, wherein the plurality of blocks share some data lines with an adjacent block, The data line switching circuit includes a plurality of switching circuits arranged corresponding to each of the plurality of blocks, and each of the plurality of switching circuits includes an external circuit corresponding to a corresponding data line according to the bus width. A mode for switching a connection with a data line, a mode for replacing the defective data line with the shared data line, and shifting a connection between the corresponding external data line and the corresponding data line in accordance with the bus width; Or belongs to any state of a mode of shifting a connection between a corresponding external data line and a corresponding data line according to the bus width.
The semiconductor memory device according to claim 7. 9. Each of the plurality of switching circuits includes: a first gate configured to selectively switch connection between the m nodes and the m external data lines according to the bus width; A second gate for disconnecting the defective data line from the m nodes based on the bus width and the replacement information; and the shared data line based on the bus width and the replacement information. 9. The semiconductor memory device according to claim 8, further comprising: a third gate selectively connecting one of said m nodes. 10. A memory cell array including a plurality of memory cells arranged in a matrix, including first and second redundant data lines and a plurality of normal data lines, for reading data from the memory cell array, or for reading data from the memory cell array. A plurality of data lines for writing data, a plurality of external data lines provided corresponding to the plurality of normal data lines, respectively, A connection operation between the external data line to be used and the data line to be coupled is shifted in accordance with a selection operation for selecting a data line to be coupled to the data line and storage information on a defective data line included in the plurality of data lines. A semiconductor memory device comprising: a data line switching circuit that simultaneously performs a shift operation. 11. The first and second redundant data lines are respectively arranged outside the plurality of normal data lines, and the plurality of data lines are respectively a first redundant data line and a plurality of normal data lines. , And a second redundant data line, wherein the plurality of external data lines are divided into a plurality of blocks by n lines, and the plurality of data lines are adjacent to each other corresponding to the plurality of blocks, respectively. The data lines are divided into (n + 2) lines according to the above order such that two normal data lines are shared between the blocks, and the data line switching circuit includes a plurality of switching circuits arranged corresponding to the plurality of blocks, respectively. Each of the plurality of switching circuits has a defective data line absent in a corresponding block, and a normal data line corresponding to the bus width. A first mode for switching a connection to a corresponding external data line, wherein a defective data line is absent in the corresponding block, and the connection between the corresponding external data line and the corresponding data line is adjusted according to the bus width. A second mode for shifting to the first redundant data line side, wherein a defective data line is absent in the corresponding block, and the connection between the corresponding external data line and the corresponding data line is adjusted in accordance with the bus width; A third mode for shifting to the second redundant data line side, wherein the corresponding block includes one defective data line, and is shifted to the first redundant data line side of the corresponding (n + 2) data lines; One of the shared data line and the first redundant data line is replaced with an adjacent block to replace the one defective data line and is adjusted to the bus width. A fourth mode in which the connection between the corresponding external data line and the corresponding data line is shifted, wherein the corresponding block includes one defective data line and includes one of the (n + 2) data lines. Replacing one defective data line with one of the shared data line and the second redundant data line with a block adjacent to the second redundant data line side, and A fifth mode in which the connection between the corresponding external data line and the corresponding data line is shifted in accordance with the above, and the corresponding (n + 2) data including two defective data lines in the corresponding block One of the shared data line and the first redundant data line between a block adjacent to the first redundant data line side and the second redundant data line. The one defective data line is replaced with one of the shared data line and the second redundant data line between a block adjacent to the line side and an external device corresponding to the bus width. 11. The semiconductor memory device according to claim 10, wherein the device belongs to any one of sixth modes in which a connection between a data line and a corresponding data line is shifted. 12. Each of the plurality of switching circuits includes: n nodes; and a switch unit that selectively switches connection between the n nodes and n external data lines according to the bus width. The defective data line is disconnected from the n nodes based on the bus width, the replacement information, and the mode to which the corresponding block belongs, and the corresponding (n +
2. The semiconductor memory device according to claim 11, further comprising: a selection unit for connecting each of the n data lines to the n nodes. 13. 13. In the test mode, each of the plurality of switching circuits is forcibly set to one of the second mode and the third mode that can be switched from the outside. 13. The semiconductor memory device according to claim 1. 14. In the test mode, one of the plurality of switching circuits corresponding to the first redundant data line and one corresponding to the second redundant data line are:
12. The semiconductor memory device according to claim 11, wherein said fourth and fifth modes are forcibly set respectively. 15. The semiconductor memory device according to claim 11, wherein in a test mode, each of said plurality of switching circuits is forcibly set to said first mode. 16. Each of the plurality of external data lines and the plurality of normal data lines is divided into a plurality of blocks, and the data line switching circuit includes a plurality of data lines arranged corresponding to the plurality of blocks, respectively. A switching circuit, wherein each of the plurality of switching circuits has no defective data line in a corresponding block, and switches a connection between a corresponding normal data line and a corresponding external data line in accordance with the bus width. One mode, a second mode including one defective data line in the corresponding block, and replacing the one defective data by a shift operation using the first redundant data line;
Includes one defective data line in the corresponding block,
A third mode in which the one defective data is replaced by a shift operation using the second redundant data line, and the first and second redundancy modes including two defective data lines in the corresponding block; 11. The semiconductor memory device according to claim 10, wherein the semiconductor memory device belongs to any one of a fourth mode in which the two defective data are replaced by a shift operation using a data line. 17. Each of the plurality of switching circuits includes: n nodes; and a switch unit that selectively switches connection between the n nodes and n external data lines according to the bus width. Based on the bus width, the replacement information, and the mode to which the corresponding block belongs, disconnecting the defective data line from the n nodes and corresponding n normal data lines; 17. The semiconductor memory device according to claim 16, further comprising a selection unit for connecting each of the n redundant data lines to said n nodes. 18. The semiconductor memory device according to claim 16, wherein in a test mode, two of said plurality of switching circuits are forcibly set to said second and third modes, respectively.