JP2000101025A - Integrated circuit mounted with magnetic device - Google Patents
Integrated circuit mounted with magnetic deviceInfo
- Publication number
- JP2000101025A JP2000101025A JP10263316A JP26331698A JP2000101025A JP 2000101025 A JP2000101025 A JP 2000101025A JP 10263316 A JP10263316 A JP 10263316A JP 26331698 A JP26331698 A JP 26331698A JP 2000101025 A JP2000101025 A JP 2000101025A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- film
- magnetic element
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体集積回路上
に磁気素子を搭載した集積回路に関する。The present invention relates to an integrated circuit having a magnetic element mounted on a semiconductor integrated circuit.
【0002】[0002]
【従来の技術】例えば、特開平5−101937号公報
により、半導体集積回路上に窒化シリコン等の保護膜を
形成し、該保護膜上に導体膜と呼ばれるコイル部と磁性
薄膜と呼ばれる膜状のコアとを形成し、該コイル部とコ
アとによる磁気素子を半導体集積回路上に形成したもの
が知られている。2. Description of the Related Art For example, according to Japanese Patent Application Laid-Open No. Hei 5-101937, a protective film such as silicon nitride is formed on a semiconductor integrated circuit. It is known that a core is formed and a magnetic element formed by the coil portion and the core is formed on a semiconductor integrated circuit.
【0003】また例えば、実開昭57−195852号
公報により、金属膜片と呼ばれるコイル部と磁性体膜と
呼ばれる膜状のコアとによる磁気素子を半導体集積回路
に並べて形成したものが知られている。For example, Japanese Utility Model Laid-Open Publication No. 57-195852 discloses a magnetic element formed by arranging a magnetic element comprising a coil portion called a metal film piece and a film-shaped core called a magnetic film in a semiconductor integrated circuit. I have.
【0004】[0004]
【発明が解決しようとする課題】上記の特開平5−10
1937号公報により知られている集積回路では、半導
体集積回路上に形成した保護膜上に磁気素子を形成して
いる。半導体集積回路の表面は数層に亘ってパターンが
形成されている。一般にトランジスタ領域は低く、配線
領域は高いため半導体集積回路の表面は凹凸がある。該
半導体集積回路上に保護膜を形成しても、保護膜の厚み
は製造の都合上それほど厚くできないため、半導体集積
回路表面の凹凸の影響により保護膜の表面も凹凸にな
る。通常、磁気素子はトランジスタに比べてはるかに面
積が大きいため、磁気素子を凹凸のある領域に重ねて設
けると、磁気素子を平坦な形状に形成することができず
性能の良い磁気素子の形成が困難になる。SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Laid-Open Publication No.
In an integrated circuit known from Japanese Patent No. 1937, a magnetic element is formed on a protective film formed on a semiconductor integrated circuit. A pattern is formed over several layers on the surface of the semiconductor integrated circuit. Generally, the surface of a semiconductor integrated circuit has irregularities because the transistor region is low and the wiring region is high. Even if a protective film is formed on the semiconductor integrated circuit, the thickness of the protective film cannot be so large for the sake of manufacturing. Therefore, the surface of the protective film is also uneven due to the unevenness of the surface of the semiconductor integrated circuit. Normally, since a magnetic element has a much larger area than a transistor, if the magnetic element is provided over an uneven area, the magnetic element cannot be formed into a flat shape and a high-performance magnetic element can be formed. It becomes difficult.
【0005】一方、上記実開昭57−195852号公
報により知られている集積回路では、半導体集積回路に
並べて磁気素子を形成している。このものでは磁気素子
と半導体集積回路を重ねて配置していないので、集積回
路全体の面積縮小に限界がある。また、磁気素子と半導
体集積回路との間に保護機構が無いので、膜状のコアの
材料が半導体基板を汚染して、半導体集積回路の性能に
悪影響を及ぼすおそれがある。さらに、磁気素子からの
漏えい磁束が、半導体集積回路の動作に悪影響を及ぼす
おそれもある。On the other hand, in the integrated circuit disclosed in Japanese Utility Model Laid-Open No. 57-195852, a magnetic element is formed side by side with a semiconductor integrated circuit. In this case, since the magnetic element and the semiconductor integrated circuit are not arranged so as to overlap each other, there is a limit in reducing the area of the entire integrated circuit. Further, since there is no protection mechanism between the magnetic element and the semiconductor integrated circuit, the material of the film-shaped core may contaminate the semiconductor substrate and adversely affect the performance of the semiconductor integrated circuit. Further, the magnetic flux leaked from the magnetic element may adversely affect the operation of the semiconductor integrated circuit.
【0006】そこで本発明は、上記の問題点に鑑み、上
記不具合なく、磁気素子を半導体集積回路の上方に搭載
した集積回路を提供することを課題とする。In view of the above problems, an object of the present invention is to provide an integrated circuit in which a magnetic element is mounted above a semiconductor integrated circuit without the above problems.
【0007】[0007]
【課題を解決するための手段】上記課題を解決するため
に本発明は、保護膜で覆われた半導体集積回路上に磁気
素子を搭載した集積回路において、上記保護膜上に上面
が平坦になるように絶縁膜を形成し、該絶縁膜の上面
に、半導体集積回路に対して平行なコイル部と、該コイ
ル部と半導体集積回路との間に位置する膜状のコアとで
構成した磁気素子を設けたことを特徴とする。According to the present invention, there is provided an integrated circuit in which a magnetic element is mounted on a semiconductor integrated circuit covered with a protective film, the upper surface of which is flat on the protective film. Element having a coil portion parallel to a semiconductor integrated circuit and a film-shaped core located between the coil portion and the semiconductor integrated circuit on an upper surface of the insulating film. Is provided.
【0008】上面が平坦な絶縁膜を設けることにより、
磁気素子を平坦な形状に形成できるので性能の良い磁気
素子を半導体集積回路の上方に形成することができる。
また、半導体集積回路と磁気素子を重ねて配置するの
で、集積回路全体の面積が小さくなる。更に、半導体集
積回路とコアの間に保護膜が介在するので、半導体集積
回路がコアの材料で汚染されにくい。また、磁気素子を
構成するコイル部と半導体集積回路との間に膜状のコア
が位置するので、コイル部で生じる磁束がコアで遮断さ
れ、半導体集積回路に磁束が影響しにくい。By providing an insulating film having a flat upper surface,
Since the magnetic element can be formed in a flat shape, a high-performance magnetic element can be formed above the semiconductor integrated circuit.
Further, since the semiconductor integrated circuit and the magnetic element are arranged so as to overlap with each other, the area of the entire integrated circuit is reduced. Further, since the protective film is interposed between the semiconductor integrated circuit and the core, the semiconductor integrated circuit is less likely to be contaminated with the core material. Further, since the film-shaped core is located between the coil part constituting the magnetic element and the semiconductor integrated circuit, the magnetic flux generated in the coil part is cut off by the core, and the magnetic flux hardly affects the semiconductor integrated circuit.
【0009】尚、上記磁気素子がコイル部を挟んで上記
コアと対を成す第2の膜状のコアを備えれば、コイル部
で生じる磁束が上下2層のコアで遮断されるので、磁気
素子の性能がさらに良くなり、磁気素子から半導体集積
回路への磁束漏れがさらに少なくなる。If the magnetic element has a second film-shaped core paired with the core with the coil interposed therebetween, the magnetic flux generated in the coil is interrupted by the upper and lower cores. The performance of the element is further improved, and the magnetic flux leakage from the magnetic element to the semiconductor integrated circuit is further reduced.
【0010】[0010]
【発明の実施の形態】図1を参照して、1は本発明によ
る集積回路の一例の断面の一部分であり、通常の半導体
集積回路部2の上方に磁気素子部5を備えている。21
は該半導体集積回路部2の基板であり、単結晶シリコン
から成っている。該基板21の上面にはMOS技術又は
バイポーラ技術によるトランジスタ、抵抗、コンデンサ
等が形成され、更にその上面に適宜の電極及び配線22
が形成されている。そして、該半導体集積回路2の上面
には窒化シリコンから成る保護膜3が被着されている。
本発明では該保護膜3の上面に熱硬化性樹脂であるポリ
イミド等から成る絶縁膜4を形成した。本実施の形態で
は該絶縁膜4を3回に分けて重ねて形成する。絶縁膜4
を形成する際には最初に41で示すレベルまで熱硬化性
樹脂を被着させる。次に磁性材料であるニッケル鉄合金
又はフェライトやアモルファス合金から成る膜状の第1
コア53を形成する。次に、第1コア53の上面より所
定距離上方の42に示すレベルまで熱硬化性樹脂を積層
する。次に、コイル部51と電極及び配線22を接続す
る層間配線52が形成されるよう、絶縁膜4と保護膜3
に縦穴を開設する。次に、アルミニウム又は銅や金から
成るコイル部51と層間配線52とを形成する。該コイ
ル部51は例えば図2に示すように形成する。この後
は、43に示すレベルまで熱硬化性樹脂を重ねて絶縁膜
4を完成させる。本実施の形態では該絶縁膜4の上面に
更にニッケル鉄合金又はフェライトやアモルファス合金
から成る膜状のコア54を形成した。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, reference numeral 1 denotes a part of a cross section of an example of an integrated circuit according to the present invention, which has a magnetic element section 5 above a normal semiconductor integrated circuit section 2. 21
Is a substrate of the semiconductor integrated circuit section 2 and is made of single crystal silicon. Transistors, resistors, capacitors, and the like are formed on the upper surface of the substrate 21 by MOS technology or bipolar technology.
Are formed. A protective film 3 made of silicon nitride is provided on the upper surface of the semiconductor integrated circuit 2.
In the present invention, an insulating film 4 made of a thermosetting resin such as polyimide is formed on the upper surface of the protective film 3. In this embodiment mode, the insulating film 4 is formed three times and overlapped. Insulating film 4
Is formed, a thermosetting resin is first applied to the level indicated by 41. Next, a film-like first material made of a nickel-iron alloy or a ferrite or an amorphous alloy which is a magnetic material is used.
The core 53 is formed. Next, the thermosetting resin is laminated to a level indicated by 42 which is a predetermined distance above the upper surface of the first core 53. Next, the insulating film 4 and the protective film 3 are formed so that an interlayer wiring 52 connecting the coil portion 51 to the electrode and the wiring 22 is formed.
A vertical hole will be established. Next, a coil portion 51 made of aluminum, copper, or gold and an interlayer wiring 52 are formed. The coil portion 51 is formed, for example, as shown in FIG. Thereafter, the thermosetting resin is overlaid to the level indicated by 43 to complete the insulating film 4. In the present embodiment, a film-like core 54 made of a nickel-iron alloy, ferrite, or an amorphous alloy is further formed on the upper surface of the insulating film 4.
【0011】[0011]
【発明の効果】以上の説明から明らかなように、本発明
は、凹凸のある保護膜上に上面が平坦になるように絶縁
膜を形成し、該絶縁膜上に、半導体集積回路に対して平
行なコイル部と、該コイル部と半導体集積回路との間に
位置する膜状のコアとで構成した磁気素子を形成するよ
うにしたので、半導体集積回路の上方に性能の良い磁気
素子を形成することができ、集積回路全体の面積が小さ
くなり、磁気素子から半導体集積回路への磁束漏えいを
なくすことができる。As is apparent from the above description, according to the present invention, an insulating film is formed on an uneven protective film so that the upper surface becomes flat, and a semiconductor integrated circuit is formed on the insulating film. Since a magnetic element composed of a parallel coil part and a film-shaped core located between the coil part and the semiconductor integrated circuit is formed, a high-performance magnetic element is formed above the semiconductor integrated circuit. Thus, the area of the entire integrated circuit is reduced, and leakage of magnetic flux from the magnetic element to the semiconductor integrated circuit can be eliminated.
【図1】本発明の一実施の形態の構成を示す断面図FIG. 1 is a sectional view showing a configuration of an embodiment of the present invention.
【図2】コイル部のパターンを示す平面図FIG. 2 is a plan view showing a pattern of a coil unit.
1 磁気素子を搭載した集積回路 2 半導体集積回路 3 保護膜 4 絶縁膜 5 磁気素子 DESCRIPTION OF SYMBOLS 1 Integrated circuit mounting magnetic element 2 Semiconductor integrated circuit 3 Protective film 4 Insulating film 5 Magnetic element
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小沢 武 神奈川県横浜市旭区中尾二丁目1−25− 526 (72)発明者 馬場 康壽 神奈川県横浜市保土ヶ谷区東川島町86−6 −123 Fターム(参考) 5E070 AB01 AB10 BA20 BB01 BB02 CB12 CB20 DA17 5F038 AZ04 AZ10 EZ20 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Takeshi Ozawa 2-1-2-5-26 Nakao, Asahi-ku, Yokohama-shi, Kanagawa Prefecture (72) Inventor Yasuhisa Baba 86-6-123 Higashikawashima-cho, Hodogaya-ku, Yokohama-shi, Kanagawa Prefecture F-term (Reference) 5E070 AB01 AB10 BA20 BB01 BB02 CB12 CB20 DA17 5F038 AZ04 AZ10 EZ20
Claims (2)
磁気素子を搭載した集積回路において、上記保護膜上に
上面が平坦になるように絶縁膜を形成し、該絶縁膜の上
面に、半導体集積回路に対して平行なコイル部と、該コ
イル部と半導体集積回路との間に位置する膜状のコアと
で構成した磁気素子を設けたことを特徴とする磁気素子
を搭載した集積回路。In an integrated circuit having a magnetic element mounted on a semiconductor integrated circuit covered with a protective film, an insulating film is formed on the protective film so that an upper surface is flat, and an upper surface of the insulating film is An integrated circuit mounted with a magnetic element, comprising: a magnetic element including a coil portion parallel to the semiconductor integrated circuit and a film-shaped core located between the coil portion and the semiconductor integrated circuit. .
コアと対を成す第2の膜状のコアを有することを特徴と
する請求項1記載の磁気素子を搭載した集積回路。2. The integrated circuit according to claim 1, wherein the magnetic element has a second film-shaped core that forms a pair with the core with a coil portion interposed therebetween.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10263316A JP2000101025A (en) | 1998-09-17 | 1998-09-17 | Integrated circuit mounted with magnetic device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10263316A JP2000101025A (en) | 1998-09-17 | 1998-09-17 | Integrated circuit mounted with magnetic device |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2000101025A true JP2000101025A (en) | 2000-04-07 |
Family
ID=17387796
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10263316A Pending JP2000101025A (en) | 1998-09-17 | 1998-09-17 | Integrated circuit mounted with magnetic device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2000101025A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002164512A (en) * | 2000-11-28 | 2002-06-07 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
JP2005534184A (en) * | 2002-07-25 | 2005-11-10 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Planar inductance |
US7714410B2 (en) | 2007-05-11 | 2010-05-11 | Seiko Epson Corporation | Semiconductor device |
-
1998
- 1998-09-17 JP JP10263316A patent/JP2000101025A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002164512A (en) * | 2000-11-28 | 2002-06-07 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
JP2005534184A (en) * | 2002-07-25 | 2005-11-10 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Planar inductance |
US7714410B2 (en) | 2007-05-11 | 2010-05-11 | Seiko Epson Corporation | Semiconductor device |
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