JP2000100783A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of abnormal discharging of plasma by performing either whether to put the interval between electrodes in a specified range or whether to put the frequency of a high frequency at a specified value as the dry etching conditions, where forming a connection hole. SOLUTION: When forming a connection hole on a conductive layer through the insulating film of a wafer 203 by introducing a gas into a reaction chamber, and applying a high frequency between electrodes 201 and 202 placed in parallel from a high-frequency power source 204, and performing etching, either whether to put the interval 205 between electrodes in the range of about 8 to 12 mm or whether to put the frequency of high frequency at about 380 kHz is selected. By doing it this way, even with a multilayer wiring structure where a connection hole is made in the second or third conductive layer, the etching to form a connection hole becomes possible without generating abnormal discharging of the plasma.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, wherein a connection hole is formed by using a dry etching method.
The present invention relates to formation on the conductive layer through the insulating film without causing abnormal plasma discharge.

[0002]

2. Description of the Related Art A conventional method for manufacturing a semiconductor device is shown in FIG.
As shown in FIG. In FIG. 1, 101 is a conductive layer,
102 is an insulating film, 103 is a resist, and 104 is a connection hole. FIG. 5 shows an RIE type dry etching apparatus in which a gas is introduced into a reaction chamber, a high frequency is applied between electrodes placed in parallel, the gas is turned into plasma, and etching is performed.
01 is an application electrode, 502 is a ground electrode, 503 is a wafer,
Reference numeral 504 denotes a high-frequency power supply, and reference numeral 505 denotes a distance between electrodes.

In FIG. 1, a conductive layer 101 is formed above a Si substrate by, for example, an impurity layer of a silicon substrate, polycrystalline Si (PolySi) doped with an impurity, a metal, or an alloy thereof. The insulating film 102 is formed thereon by, for example, a silicon dioxide film formed by a chemical vapor deposition method using monosilane and oxygen, or a silicon oxide film formed by thermal oxidation and a BPSG containing boron or phosphorus by vapor phase growth. A connection hole 104 for making an electrical connection with the conductive layer 101 is formed thereon, and a photoresist pattern 103 having a hole diameter of, for example, 0.6 μm is formed on the insulating film 102 (FIG. 1A). Using the photoresist pattern 103 as a mask, the connection hole 104 is formed on the conductive layer 101 through the insulating film 102 by a dry etching method (FIG. 1B).

[0005] In FIG. 5, in the dry etching method of the connection hole 104, the distance 505 between the applied electrode 501 and the ground electrode 502 in the reaction chamber is set to, for example,
At 1.6 mm, a process gas such as CF4 is introduced into the reaction chamber.
20 sccm and CHF3 20 sccm and Ar 200
sccm, and the pressure in the apparatus is set to, for example, 200 mTorr.
r, the gas is turned into plasma under the condition that the high frequency is 13.56 MHz and the applied voltage is 800 W, for example, and the hole diameter is 0.6, for example.
μm, the etching rate is 483.9 nm / mi
n, uniformity 5.8%, selectivity to poly-Si 13.
94.

[0005] With the reduction in design rules, in the multilayer wiring, a connection hole for making an electrical connection with the conductive layer is repeatedly formed every time a conductive layer and an insulating film are formed. In a multilayer wiring structure formed in a third conductive layer, abnormal discharge of plasma is more likely to occur during dry etching for forming a connection hole. The abnormal discharge of the plasma has a serious problem that it is extremely difficult to reduce the yield because the discharge falls from the plasma to the conductive layer and breaks and breaks the wiring, or generates particles and causes processing failure of the connection hole.

As one of these remedies, it is conceivable not to adopt a multi-layer wiring structure or to reduce the length and thickness of a conductive layer which increases the interlayer capacitance. Not.

[0007] As one of remedies, a self-bias (V) generated at the time of dry etching for forming a connection hole is considered.
An apparatus in which dc) is extremely small, for example, an ECR type, helicon type or ICP type etching apparatus capable of separating and controlling a high frequency (plasma source) for generating plasma and a high frequency (ion source) for drawing ions into a wafer. However, at present, there is no device that can stabilize the connection hole by etching the insulating film, has good reproducibility, and is inexpensive, which is not practical.

As one of the remedies, in order to reduce the self-bias (Vdc) generated at the time of dry etching for forming a connection hole in an RIE type dry etching apparatus, it is necessary to extremely reduce a high frequency applied voltage. It is conceivable that the magnitude of the applied voltage and the etching rate are in a proportional relationship, and the decrease in the etching rate results in an extremely small number of wafers that can be processed per unit time. There is no stability of discharge, it is impossible to supply stably, with good reproducibility, and it is not realistic for mass production.

[0009]

SUMMARY OF THE INVENTION However, the present invention has been made to solve the above problems, and has been described under dry etching conditions.
By selecting an electrode spacing distance in the range of 8 to 12 mm or a high frequency of 380 KHz, an abnormal discharge of plasma does not occur and an etching method for forming a connection hole is provided. The equipment you are using
It is intended to stably, reproducibly, and inexpensively improve electrical characteristics, yield, and reliability, and aim at practical use and stable supply of a fine semiconductor device.

[0010]

According to a method of manufacturing a semiconductor device of the present invention, at least a step of forming a conductive layer of a semiconductor element on a semiconductor substrate; a step of forming an insulating film on the conductive layer; A step of forming a photoresist pattern on the insulating film with a connection hole for making an electrical connection with the layer, using the photoresist pattern as a mask, using a dry etching method to dry the connection hole without causing abnormal plasma discharge. It is formed over the conductive layer through an insulating film.

The method of manufacturing a semiconductor device according to the present invention is the dry etching method, wherein a gas is introduced into a reaction chamber, a high frequency is applied, the gas is turned into plasma, and the insulating film is etched. It is characterized by using.

In the method of manufacturing a semiconductor device according to the present invention, in the dry etching method, the distance between the electrodes may be 8 to 12;
It is characterized in that a range of mm is used.

In the method of manufacturing a semiconductor device according to the present invention, in the dry etching method, a high frequency of 380 K
Hz is used.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a main part showing an embodiment of a semiconductor device of the present invention, wherein 101 is a conductive layer, 102 is an insulating film, 103 is a resist, and 104 is a connection hole. FIG. 2 is a cross-sectional view of a main part showing an embodiment of the semiconductor device of the present invention, in which gas is introduced into a reaction chamber, high frequency is applied between electrodes placed in parallel, the gas is turned into plasma, and etching is performed. Is an application electrode, 201 is an applied electrode, 202 is a ground electrode, 203 is a wafer, 204
Is a high frequency power supply, and 205 is a distance between electrodes.

In FIG. 1, the conductive layer 101 is formed above a Si substrate by, for example, an impurity layer of a silicon substrate, polycrystalline Si (PolySi) doped with an impurity, a metal, or an alloy thereof. The insulating film 102 is formed thereon.
Is formed of, for example, a silicon dioxide film formed by chemical vapor deposition using monosilane and oxygen, or a silicon oxide film formed by thermal oxidation and BPSG containing boron or phosphorus by vapor growth. The connection holes 104 for making electrical connection with the conductive layer 101 are formed thereon, and the photoresist pattern 103 is formed on the insulating film 102 with a hole diameter of, for example, 0.6 μm (FIG. 1A). Using the photoresist pattern 103 as a mask, the connection hole 104 is formed on the conductive layer 101 through the insulating film 102 by a dry etching method (FIG. 1B).

In FIG. 2, in the dry etching method of the connection hole 104, the electrode distance 205 between the applied electrode 201 and the ground electrode 202 in the reaction chamber is set to, for example, 1
0 mm, process gas is introduced into the reaction chamber, for example, CF4 20
sccm, CHF3 20sccm and Ar 200sc
cm, and the pressure in the apparatus is set to, for example, 200 mTorr.
When the gas is turned into plasma and etching is performed under the conditions that a high frequency of 400 KHz and an applied voltage of 800 W are applied, for example, the hole diameter becomes 0.6 μm.
At this time, the etching rate was 450.3 nm / min, the uniformity was 3.8%, and the selectivity with respect to poly Si was 14.31.

The method of manufacturing a semiconductor device as described above is directed to an etching method for forming a connection hole in which an abnormal discharge of plasma does not occur even in a multilayer wiring structure in which a connection hole is formed in a second or third conductive layer. With the equipment currently in use, stable, reproducible, inexpensive, and improved electrical characteristics, yield, and reliability have been achieved, and the practical application and stable supply of fine semiconductor devices has become possible. According to the present invention, the conductive layer 2
It goes without saying that the present invention can be applied to the formation of the connection hole of the multilayer wiring of the first layer or more.

The above is a description of the first embodiment.

FIG. 3 is a sectional view of an essential part showing an embodiment of a semiconductor device of the present invention. Reference numeral 301 denotes LOCOS (selective oxidation, Locoal Oxidation of Silicon, hereinafter LOCOS).
302, an oxide film, 303, a gate electrode conductive layer, 304, a source / drain region conductive layer, 305, an insulating film, 306, a resist, and 307, a connection hole. FIG.
FIG. 3 is a cross-sectional view of a main part showing an embodiment of a semiconductor device of the present invention, in which gas is introduced into a reaction chamber, high frequency is applied between electrodes placed in parallel, gas is turned into plasma, and etching is performed. An RIE type dry etching apparatus, 401 is an applied electrode, 402 is a ground electrode, 403 is a wafer, 404 is a high frequency power supply, and 405 is a distance between electrodes.

In FIG. 3, the LOCOS3
After forming the oxide film 01, the oxide film 302 is formed on the entire surface.
The gate electrode conductive layer 303 is formed thereon, for example, as a poly-Si conductive layer, and its thickness is, for example, 0.2 μm. With the structure, the source / drain region conductive layer 304 is formed by implanting ions using the gate electrode conductive layer 303 as a mask, and the oxide film 302 other than the gate electrode conductive layer 303 is formed.
Is removed by hydrofluoric acid etching. The insulating film 30 is formed thereon.
5 is, for example, a silicon dioxide film formed by a chemical vapor deposition method using monosilane and oxygen, a film thickness of 0.1 μm, and phosphorus silicate glass formed thereon by a chemical vapor deposition method using monosilane, oxygen and phosphine; 0.8 μm
Formed. The photoresist pattern 306 is formed thereon.
Are patterned on the gate electrode conductive layer 303 and the source / drain region conductive layer 304, for example, with a hole diameter of 0.6 μm. Using the patterned photoresist pattern 306 as a mask, the connection hole 307 is formed on the gate electrode conductive layer 303 and the source / drain region conductive layer 304 through the insulating film 305 using a dry etching method. I have.

In FIG. 4, in the dry etching method of the connection hole 307, the electrode distance 405 between the applied electrode 401 and the ground electrode 402 in the reaction chamber is set to, for example, 1
0 mm, process gas is introduced into the reaction chamber, for example, CF4 20
sccm, CHF3 20sccm and Ar 200sc
cm, the internal pressure of the apparatus is set to, for example, 200 mTorr, the high-frequency frequency is set to, for example, 13.56 MHz, and the applied voltage is set to, for example, 800 W.
In this case, the etching rate was 432.7 nm / min, the uniformity was 4.2%, and the selectivity with respect to poly Si was 15.26.

The method of manufacturing a semiconductor device in this manner is an etching method for forming a connection hole in which an abnormal discharge of plasma does not occur even in a multilayer wiring structure in which a connection hole is formed in a second or third conductive layer. With the equipment currently in use, stable, reproducible, inexpensive, and improved electrical characteristics, yield, and reliability have been achieved, and the practical application and stable supply of fine semiconductor devices has become possible. According to the present invention, the conductive layer 2
It goes without saying that the present invention can be applied to the formation of the connection hole of the multilayer wiring of the first layer or more.

The above is a description of the second embodiment.

The embodiment of the present invention has been described with reference to the drawings.
Example explained. However, the present invention is not limited to this, and the conditions for forming the connection hole by the dry etching method are as follows: the electrode distance is in the range of 8 to 12 mm, and the high frequency is 380.
At KHz, by choosing one of these,
It goes without saying that it is possible to provide an etching method for forming a connection hole that does not cause abnormal discharge of plasma.

[0025]

As described above, according to the present invention, the formation of connection holes in a conductive layer in a multilayer wiring of a semiconductor device such as a miniaturized LSI using a dry etching method is performed by an abnormal discharge of plasma. Has the effect of preventing disconnection of wiring, preventing defective processing of connection holes, improving long-term reliability related to electrical characteristics and quality, and stabilizing mass production, and enabling stable supply of fine semiconductor devices. It is.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a schematic sectional view showing a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 ... Conductive layer 102 ... Insulating film 103 ... Resist 104 ... Connection hole 201 ... Applying electrode 202 ... Ground electrode 203 ... Wafer 204 ... High frequency power supply 205 ... Electrode interval distance 301 LOCOS 302 oxide film 303 gate electrode conductive layer 304 source / drain region conductive layer 305 insulating film 306 resist 307 connection hole 401 ... Applied electrode 402 ... Ground electrode 403 ... Wafer 404 ... High frequency power supply 405 ... Distance between electrodes 501 ... Applied electrode 502 ... Ground electrode 503 ... Wafer 504 ... High frequency power supply 505 ・ ・ ・ Distance between electrodes

Claims (4)

[Claims] 1. A step of forming at least a conductive layer of a semiconductor element on a semiconductor substrate, a step of forming an insulating film on the conductive layer, and forming a connection hole for making an electrical connection with the conductive layer. Forming a photoresist pattern thereon, using the photoresist pattern as a mask, forming the connection hole on the conductive layer through the insulating film without causing abnormal plasma discharge using a dry etching method. Semiconductor device manufacturing method. 2. The dry etching method according to claim 1, wherein a gas is introduced into the reaction chamber, a high frequency is applied, the gas is turned into plasma, and the insulating film is etched. 2. The method for manufacturing a semiconductor device according to claim 1. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the distance between the electrodes is in a range of 8 to 12 mm in the dry etching method. 4. The method of manufacturing a semiconductor device according to claim 2, wherein a high frequency of 380 KHz is used in said dry etching method.