JPH05291247A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a tapered step on a sidewall of an interlayer connecting hole, largely forming the diameter of an opening upper part, forming a smooth tapered state, and to prevent disconnection of an upper interconnection layer by inserting an etching step of a resist film on the way of etching the hole. CONSTITUTION:As a first step, a resist film 3 having a predetermined shape is formed on at least one interlayer insulating film 20 formed on a substrate 1. Then, as a second step, with the film 3 as a mask the film 20 is etched to the midway of its thickness by first anisotropic dry etching. Then, as a third step, the film 3 is etched only for a predetermined time by second anisotropic dry etching, Thereafter, as a fourth step, the film 20 is etched only for a predetermined time by third anisotropic dry etching. Then, as a fifth step, the film 3 is removed, and subsequently as a sixth step, a heat treatment is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a contact hole or a through hole of a semiconductor device, that is, an interlayer connecting hole is formed, and in particular, a side wall portion of the interlayer connecting hole has a smooth taper. Relates to a method of forming.

[0002]

2. Description of the Related Art Reactive ion etching (RIE) has been widely used to form fine contact holes or through holes in an interlayer insulating film of a semiconductor device.

When the object to be etched is etched by the reactive ion etching method, for example, the reactive ion etching method is performed by using the patterned resist film on the upper surface of the silicon oxide film formed on the silicon substrate as a mask. In this case, the etching cross section of the silicon oxide film is usually very steep. When such an etching method is used for forming a contact hole, the deposited film thickness becomes extremely thin at the step of the etching cross section during the subsequent deposition of the metal wiring layer, which causes disconnection of the metal wiring layer and lowers the yield. And may shorten the life.

As a method of tapering a contact hole, a method of forming a taper above the opening by isotropic etching and then opening to the bottom by anisotropic dry etching, or an etching rate of a resist film and an interlayer insulating film A method of opening a contact hole while controlling the ratio (selection ratio, which is the ratio of both etching rates) has been proposed.

7 (a) to 7 (c), Japanese Patent Laid-Open No. 63-86.
An example of a conventional method for forming a contact hole disclosed in Japanese Patent No. 522 will be described. Source / on silicon substrate 1
The drain regions 6-1 and 6-2 are formed, and the gate electrode 8 is formed via the gate insulating film 7, and BPSG (on each of the source / drain regions 6-1 and 6-2 and the gate electrode 8 is formed). An interlayer insulating film 2 made of boron-doped phosphorus silicon glass) is formed, and a patterned resist film 3 is formed on the upper surface of the interlayer insulating film 2 (FIG. 7).
(A)). Next, the source / drain regions 6-1 and 6
-2, the taper 9 is formed on the above-mentioned interlayer insulating film 2 by isotropic etching (FIG. 7B), and then the contact hole (interlayer connection hole) 4 is opened by anisotropic dry etching. (Fig. 7 (c)).

[0006]

However, in the method of forming the tapered contact hole described above, when the element is miniaturized, interlayer insulation between the wiring layer formed on the tapered portion 9 and the gate electrode 8 is achieved. The film 2 becomes thin, and the breakdown voltage is insufficient, which causes a defect in the integrated circuit.

It is an object of the present invention to form a tapered step on the side wall of an interlayer connection hole, to form a large diameter at the upper portion of the opening and to form a smooth tapered shape. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which contributes to prevention of disconnection of the upper wiring layer and obtains stable high yield.

[0008]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a resist film having a predetermined shape on an interlayer insulating film consisting of at least one layer formed on a substrate. And a second anisotropic dry etching using the resist film as a mask to etch the interlayer insulating film to the middle of the film thickness, and a second anisotropic dry etching. A third step of etching the resist film for a predetermined time by dry etching, a fourth step of etching the interlayer insulating film for a predetermined time by third anisotropic dry etching, and the resist film And a sixth step of performing heat treatment are sequentially included.

[0009]

In the present invention, during the etching of the interlayer connection hole,
By inserting a resist film etching process and performing heat treatment after processing the contact hole, the opening upper part of the interlayer connection hole can be formed in a wide and smooth taper shape, and the step coverage of the upper wiring layer can be formed. Can be improved and contributes to the prevention of disconnection.

[0010]

1 to 6 are imitative sectional structure views of a forming structure in each step for explaining an embodiment of a method for manufacturing a semiconductor device of the present invention.

First, an interlayer insulating film 20 consisting of two layers of a silicon oxide film (SiO ₂ ) 2-1 and a boron-doped phosphorus silicon glass (BPSG) film 2-2 is formed on a silicon substrate 1.
Then, a resist film 3 is formed by coating on the upper surface of the interlayer insulating film 20 to form a resist pattern 3a for opening a contact hole (first step: FIG. 1).

Next, the interlayer insulating film 20 is etched by the first anisotropic dry etching (plasma treatment) using the resist film 3 having the resist pattern 3a as a mask. As the first anisotropic dry etching, reactive ion etching (RIE) is used, and the contact hole 4
Etch halfway. For example, a mixed gas of CHF ₃ and O ₂ is used as an etching gas, and the mixing ratio is CHF ₃
/ O ₂ = 100/20 sccm, pressure 50 mTorr,
When the RF power is 1200 W, the cross-sectional shape of the contact hole 4 is formed almost vertically. Contact hole 4
It is necessary to form the cross-sectional shape vertically in the vicinity of the bottom portion in order to maintain the pattern processing accuracy, but it is desirable to form a tapered shape that widens toward the upper portion of the opening except in the vicinity of the sidewall bottom portion. By changing the mixing ratio of the etching gas, the etching rate of the interlayer insulating film 20 with respect to the resist is changed, so that the contact hole 4 can be tapered. For example, after performing vertical processing under the above etching conditions, the gas flow rate ratio CHF ₃ / O ₂ = 80/15
0sccm, pressure 50mTorr, RF power 1000W
In this case, the cross-sectional shape of the contact hole 4 is tapered upward and vertically downward. Since the vertical and taper processes can be continuously performed, they are referred to as first anisotropic dry etching (second process: FIG. 2).
Even in the step of tapering by changing the etching conditions as described above and changing the etching rate ratio between the resist film 3 and the interlayer insulating film 2 as the workpiece, a vertical hole below the interlayer connection hole 4 is also formed. However, the reason why the etching process proceeds vertically as it is is that the etching is performed by anisotropic etching and that the etching rates of the bottom portion and the tapered portion are equal to each other or that the bottom portion is faster than the tapered portion.

Next, only the resist film 3 is etched for a predetermined time by second anisotropic dry etching. As the second anisotropic dry etching, it is necessary that the resist film 3 can be etched with good controllability. For example, when RIE is used and O ₂ is used as the etching gas, the flow rate is 150 sccm, the pressure is 80 mTorr,
When the RF power is 800 W, the lateral etching amount of the resist pattern 3a is 0.03 μm / min, and the one side is 0.1
When the resist is recessed by μm, the resist etching time may be 3.3 minutes. However, in the RIE apparatus, the silicon oxide film or the silicon nitride film is mainly etched in many cases, and the reaction product attached to the inner wall of the chamber affects the base substrate during the etching of the silicon oxide film or the silicon nitride film. It is rare to mix the processing of these materials with the resist pattern because of the possibility. In the case of the above resist etching conditions,
30 Å / min for silicon oxide film, 15 for P-type silicon substrate
Etched at a rate of Å / min. As the second anisotropic dry etching, another device needs to be used when such an influence on the base cannot be tolerated. For example, when a plasma etching apparatus is used, in order to recede the resist pattern by 0.1 μm in the same manner as above, it is necessary to use O ₂
Flow rate 100 sccm, pressure 0.3 Torr, RF power 2
Etching may be performed at 00W for 75 seconds. In this way, a resist receding region is formed at the peripheral edge of the upper surface of the contact hole 4 (third step: FIG. 3).

Next, the remaining interlayer insulating film 20 is etched by third anisotropic dry etching. As the third anisotropic dry etching, the same RIE as that of the first anisotropic dry etching is used. For example, a mixed gas of CHF ₃ and O ₂ is used as an etching gas, and the flow rate thereof is CHF ₃ /
O ₂ = 100/10 sccm, pressure 50 mTorr, R
F power is 1200 W. Under this condition, the etching rate ratio of the silicon oxide film to the silicon substrate 1 is about 10 or more, and the amount of digging of the silicon substrate 1 due to overetching of the interlayer insulating film 20 is small. Further, by performing the third anisotropic dry etching, the projection 5 of the step formed in the middle of the side wall of the contact hole 4 in the previous step is rounded and tapered by the ion sputtering effect (fourth). Process: FIG. 4).

Next, after removing the unnecessary resist film 3 by an ashing device or the like (fifth step: FIG. 5),
By performing heat treatment at 850 ° C. for 30 minutes, for example, in a nitrogen gas atmosphere, a reflow effect of the BPSG film 2-2 occurs, and a tapered shape above the contact hole opening is formed smoothly (sixth step: FIG. 6).

In the method of this embodiment having the above-described steps, the etching step of the resist film 3 is inserted during the etching of the contact hole 4 so that the upper opening of the contact hole 4 is wide and tapered. As shown in the conventional example of FIG. 2, the step coverage of the upper wiring layer can be formed without forming a thin portion in the interlayer insulating film between the wiring layer and the electrode or a deep dug in the substrate. The property can be improved and it can contribute to the prevention of disconnection.

Although the present invention has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment and can be variously modified without departing from the scope of the invention. is there. For example, in the above embodiment,
Although the case where the contact hole 4 is used as the interlayer connection hole has been described as an example, if the silicon substrate 1 in FIGS. 1 to 6 is replaced with a wiring layer, the same can be applied to the through hole. In the above embodiment, the silicon oxide film 2-1 is used.
Although the inter-layer insulating film 20 composed of two layers of the BPSG film 2-2 and the BPSG film 2-2 is used, the same applies to an inter-layer insulating film composed of one layer. Further, the heat treatment step of the sixth step may be combined with the annealing treatment after the impurity ion implantation in the compensation diffusion step for the junction after processing the contact hole 4.

[0018]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the interlayer insulating film is etched by using the anisotropic dry etching method with the resist film having a predetermined shape as a mask. When forming the interlayer connection hole by
By inserting a resist film etching step during the etching of the interlayer connection hole, the opening upper part of the interlayer connection hole can be formed in a wide and tapered shape. Further, after removing the resist film, heat treatment is performed. Since the taper shape of the upper part of the opening of the interlayer connection hole can be smoothed, the step coverage of the upper wiring layer can be improved, which can contribute to the prevention of disconnection, and as a result, the yield can be improved. ..

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional structure diagram in each step of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a schematic cross-sectional structure diagram in each step of an embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a schematic cross-sectional structure diagram in each step of an embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a schematic cross-sectional structure diagram in each step of an embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a schematic cross-sectional structure diagram in each step of the embodiment of the method for manufacturing the semiconductor device of the present invention.

FIG. 6 is a schematic cross-sectional structure diagram in each step of an embodiment of the method for manufacturing a semiconductor device of the present invention.

7A to 7C are schematic cross-sectional structural views in a conventional contact hole taper forming method.

[Explanation of symbols]

1 ... silicon substrate, 2 ... interlayer insulation film, 2-1 ... silicon oxide film (SiO _2), 2-2 ... boron added phosphorus silicon glass (BPSG) film, 3 ... resist film, 3a ... resist pattern, 4 ... Contact holes, 5 ... Tip of step, 6-1 and 6-2 ... Source / drain regions, 7 ... Gate insulating film, 8 ... Gate electrode, 9 ... Taper (isotropic etching), 20 ... Contact hole.

Claims (1)

[Claims] A resist film having a predetermined shape is formed on an interlayer insulating film made of at least one layer formed on a substrate, and the first anisotropic dry etching is used to form the resist film. A second step of etching the interlayer insulating film to the middle of its thickness using the mask as a mask, a third step of etching the resist film for a predetermined time by a second anisotropic dry etching, and a third step. By anisotropic dry etching, the fourth step of etching the interlayer insulating film for a predetermined time, the fifth step of removing the resist film, and the sixth step of heat treatment are sequentially included. A method of manufacturing a semiconductor device, comprising: