JP2000090686A - Circuit for counting number of rewrite operation of nonvolatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the reliability of stored count of rewrite operation by minimizing deterioration of cell. SOLUTION: The circuit for counting the number of times of rewrite operation comprising an EEPROM cell gate voltage generating circuit 44 for memory, n write/read circuits 15-17, and n EEPROM cells 41-43 for memory counts rewrite operation of a flash type EEPROM and stores the count. The EEPROM cell gate voltage generating circuit for memory brings the n EEPROM cells into rewritable state at the time of writing a new data of the flash type EEPROM. The n write/read circuits output a number of rewriting times read-out signal at the time of reading out the number of rewriting times. The n EEPROM cells for memory are used for writing a data wherein the data is written into one EEPROM cell for memory every time when the data of the flash type EEPROM is rewritten and the data is written into X cells within a plurality of EEPROM cells for memory when rewriting is performed X (X=1-n) times.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flash type EE
The present invention relates to a circuit for counting the number of times of rewriting (erasing and writing) of a PROM and for storing the counted value.

[0002]

2. Description of the Related Art A rewriting operation in a flash EEPROM is performed by writing data after erasing all the memory cells and transferring charges into and out of a floating gate.

FIG. 9 shows an EEPROM at the time of writing and erasing.
FIG. 3 is a diagram showing a state of a cell. The general operation of writing and erasing will be briefly described with reference to FIG. In the figure,
First, at the time of writing, VPP (high voltage) is applied to G (gate).
Is applied, and GND is connected to S (source). At this time, when charges are injected into the floating gate, VDD is connected to the drain to generate a channel (current path).

As described above, VPP (high voltage) charges are applied to the gate, so that charges in the channel pass through the oxide film below the floating gate and are accumulated in the floating gate. This allows the V of the EEPROM cell to be
The t value is set to VDD or more.

If it is not desired to write data, D (drain) is opened to prevent generation of a channel. Therefore, no charge is stored in the floating gate.
On the other hand, at the time of erasing, GND is connected to G (gate) and S
VPP (high voltage) is applied to (source), and the electric charge of the floating gate is released by the potential difference.

[0006] At this time, the electric charge moves beyond the oxide film.
During normal operation, VPP is applied to both S (source) and G (gate).
Since no (high voltage) application is performed, neither injection nor discharge of the charge of the floating gate is performed. That is, it is known that the deterioration of the memory cell of the flash EEPROM is caused by the deterioration of the oxide film due to the movement of the electric charge at the time of writing and erasing.

For this reason, it is known that every time rewriting is performed, the floating gate and the gate oxide film of the memory cell are stressed and deteriorated, and eventually cause erasing or writing failure.

Therefore, by storing and observing the number of times of rewriting, the correlation between the deterioration of the flash EEPROM cell and the number of times of rewriting can be easily evaluated, and the history of the number of times of rewriting which has been returned as an erase / write failure can be found. effective.

FIG. 6 is a diagram showing an example of a conventional memory circuit for counting the number of rewrites. 6 is a flash type EEPROM and control circuit 1 which is normally used, an n-bit counter 66, and an n-bit EEPROM cell as a storage memory cell. 68.

First, normally, when reading data from the flash EEPROM and the control circuit 1, data at an address specified by the address signal 2 is output to the data bus 8 by the read signal 3. Flash type EE
When rewriting data in the PROM and the control circuit 1, the state of the memory cell at the time of erasing shown in FIG. 9 is released to release charges from the floating gate.

At the same time, the rewriting number storage cell 68
Through the storage cell data bus 67 and the counter 66
To be stored. Thereafter, the stored value of the counter 66 is
One is counted up by the counter clock signal 69 output during the erasing period (while the erasing signal 4 is being output). Further, the EEPROM cell in the rewrite count storage cell 68 is erased by the storage cell erase signal 81 by setting the cell at the time of erasure in FIG.

Next, when writing new data into the flash EEPROM and the control circuit 1, the write signal 5
The value of the data bus 8 is written to the address specified by the address signal 2. At the same time, the rewriting number storage cell 6
8, a counter 6 according to a memory cell write signal 80 is provided.
The n-bit data counted up in 6 is written through the storage cell data bus 67.

Next, when reading the number of times of rewriting of the flash EEPROM and the control circuit 1, the value of the number-of-times-of-rewriting storage cell 68 is output to the number-of-times-of-rewriting output signal 65 by the number-of-times-of-rewriting reading signal 48.

FIG. 7 schematically shows the operation flow of FIG. FIG. 8 shows the number of rewrites and the state of the rewrite number storage cell 68 in the circuit of FIG. The operation of the rewrite count storage cell 68 and the stress caused by erasing / writing of the memory cell will be briefly described below with reference to FIGS.

In the conventional example, since the number of rewrites is counted using a counter as described above, the stored data is weighted by a binary number as shown in FIG. Therefore, as shown in FIG.
Each time the rewriting (erasing-writing) of the ROM and the control circuit 1 is performed once, the rewriting number storage cell 33 also
Erase-write must be performed once.

As an example for realizing the above functions, there is the invention of Japanese Patent Application Laid-Open No. 4-255997 (Prior art 1). However, the prior art 1 does not specifically describe the circuit, that is, the specific solution is not clear. Moreover,
In the first prior art, as described above, each time the flash EEPROM and the control circuit 1 are rewritten, the memory cell of the rewrite frequency storage cell 68 is also erased / written.

Therefore, the EEPROM cell in the rewrite number storage cell 68 also deteriorates, and has the same reliability as the flash type EEPROM and the memory cell of the control circuit 1. Further, although there is no specific circuit description in the prior art example 1, according to such a concept, if the erase-write operation is not performed on the rewrite number storage cell 68, the erase-write operation is performed. Count management of the number of times of writing cannot be realized.

Therefore, since the erase control circuit and the write control circuit are actually incorporated, there is a problem that the circuit becomes complicated.

An object of the present invention is to provide a circuit for counting the number of times of rewriting of a nonvolatile memory in which the deterioration of cells is minimized and the reliability of the stored number of times of rewriting is improved.

[0020]

SUMMARY OF THE INVENTION In order to solve the above-mentioned object, a non-volatile memory for counting the number of rewrites of a flash EEPROM and storing the count value is provided in a circuit for counting the number of rewrites of a nonvolatile memory according to the present invention. Circuit for counting the number of times of rewriting, wherein the number of times of rewriting is changed every time a rewriting operation is performed.
Writing is performed one by one in the R cell, and writing is performed only once for one EEPROM cell for storing the number of rewritings.

The flash type EEPROM has a storage EEPROM cell gate voltage generation circuit, n write / read circuits, and n storage EEPROM cells.
A counting circuit for counting the number of rewrites of the OM nonvolatile memory and storing the count value, wherein the storage EEPROM cell gate voltage generation circuit writes new data of the flash EEPROM. The n number of storage EEPROM cells are set to be in a writable state. The n number of write / read circuits output a rewrite number read signal when reading the number of rewrites, and the n number of storage EEPROM cells are:
For writing data, one EEPROM for storage is used every time rewriting of the flash EEPROM is performed once.
Data is written to the ROM cell, and rewriting is performed by X (X =
.., N) times, a plurality of storage E
X cells out of the EPROM cells are written, the data of the storage EEPROM cell is output as a cell read signal, and the value of the cell read signal indicates the number of rewrites.

Each of the n write / read circuits has a plurality of storage EEPROM cells in parallel, and is connected in parallel to each of the write / read circuits when rewriting data in the flash EEPROM and the control circuit. In addition, data is read from or written to each of the storage EEPROM cells.

In the present invention, in particular, the method of storing the number of rewrites is performed by writing (filling) the EEPROM cells for storing the number of rewrites one by one each time a rewrite operation is performed. Therefore, only one write operation is performed on the EEPROM cell for storing the number of times of rewriting, the deterioration of the cell is minimized, and the reliability of the stored value of the number of times of rewriting is improved.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a diagram showing a first embodiment of a flash EEPROM and a count and storage circuit for n times of rewriting of a control circuit 1 of the present invention.
FIG. 2 shows a timing chart of main signals in FIG. In FIG. 1, a counting circuit for counting the number of times of rewriting of a nonvolatile memory according to the present invention is a flash type EEPROM.
It is for rewriting of the OM and the control circuit 1, and includes a timing generation circuit 7, a control signal generation circuit 6, and a storage EEPROM.
It comprises an M cell gate voltage generation circuit 44, n write / read circuits 15-17, and n storage EEPROM cells 41-43.

The timing generation circuit 7 is for generating a basic pulse. The timing generation circuit 7 includes an edge detection circuit 10 for generating a pulse in a period A shown in FIG.
1. an edge detection circuit 12 that generates a pulse in period C;
An OR circuit 9 is provided.

However, this is merely an embodiment, and may be constituted by other circuits such as a clock synchronous circuit. The flash EEPROM and the control circuit 1 are for storing a program or data by a user, and are shown in a block diagram in FIG. 1 for easy explanation.

Normally, when reading data from the flash EEPROM and the control circuit 1, the data at the address specified by the address signal 2 is read by the read signal 3.
Output to the data bus 8. In this case, since the erase signal 4 and the write signal 5 are not output, the rewriting frequency counting circuit of the present invention does not operate.

Next, the operation of counting the number of rewrites will be described. Rewriting of data in the flash EEPROM and the control circuit 1 is performed by an erase-write operation. First, the operation at the time of the first rewriting will be described. When erasing data in the flash EEPROM and the control circuit 1, the flash EEPROM is controlled by the erase signal 4.
The data in the ROM and the control circuit 1 are erased. At the same time, the timing generation circuit 7 generates basic pulses for periods A, B, and C shown in FIG.

The control signal generation circuit 6 first outputs a precharge signal 47 based on these basic pulses. Next, the control signal generating circuit 6 generates the cell read signal 53 and the latch clock signal 46 shown in FIG. 2 from the basic pulse.

The memory EEPROM cell gate voltage generation circuit 44 outputs a VDD voltage to the cell gate signal 70 in response to the cell read signal 53. Therefore, the EE for storage
PROM cells 41 to 43 are turned on, and signal lines 35 to 37 are turned on.
Becomes L level (GND level).

The write / read circuits 15 to 17 include precharge circuits 29 to 31 and amplifiers 32 to 34, respectively.
, Latches 71 to 73, AND circuits 23 to 25, and analog switches 26 to 28. The precharge circuits 29 to 31 precharge the signal lines 35 to 37. The amplifiers 32 to 34 are turned on by the cell read signal 53, and the read signals 18 to 20 all go to L level.

The latches 71 to 73 latch the values of the read signals 18 to 20 according to the latch clock signal 46.
Next, when newly writing data in the flash EEPROM and the control circuit 1, a write signal 5 is output, and the value of the data bus 8 is written to the address specified by the address signal 2. At the same time, the storage EEPROM cell gate voltage generation circuit 44 outputs VPP (high voltage) to the cell gate signal 70 by the write signal 5 as shown in FIG. 2 to make the storage EEPROM cells 41 to 43 writable.

At this time, the AN of the write / read circuit 15
The write signal 5 and the VDD 49 are input to the D circuit 23, output an H level, and the analog switch 26 is turned on.

Therefore, the signal line 35 of the precharge circuit 29
Goes to H level, and the storage EEPROM cell 41 has H level.
The level is written. A of the write / read circuit 16
The write signal 5 and the output (L level) of the latch 71 are input to the ND circuit 24, the L level is output, and the analog switch 27 is turned off. Therefore, the precharge circuit 3
0 signal line 36 is in the open state, and the storage EEPR
The value of the OM cell 42 does not change.

Similarly, the values after the storage EEPROM cell 42 do not change. As a result of such an operation, the EEPROM for storage
Data is written only in the OM cell 41, that is, only in one cell.

Next, the operation at the time of the second rewriting will be described. The operations of the timing generation circuit 7 and the control signal generation circuit 6 have been described above and will not be described.

EEPR for storage at the end of the first rewrite
Only the OM cell 41 is at the H level. At the time of erasing in the second rewriting operation, the values of the storage EEPROM cells 41 to 43 are latched in the same manner as in the first rewriting operation.
Latch. Therefore, only latch 71 is set to the H level.

Next, at the time of writing, the data in the latches 71 to 73 are stored in the storage EEPROM cells 42 to 43 in a shifted form, similarly to the first rewriting operation. In the example of FIG. 1, there is no storage EEPROM cell corresponding to the value of the latch of the write / read circuit 17.

As a result of such an operation, when rewriting is performed twice, only two of the storage EEPROM cells 41 and 42 are written. The same operation as described above is performed in the third and subsequent rewriting operations. Therefore, X (X = 1, 2, 3
..., N) times when EE for storage is performed
X cells of the PROM cells are written (filled).

Next, the operation of reading the number of rewrites will be described. When reading the number of rewrites, a rewrite number read signal 48 is output. At this time, the precharge signal 47 and the cell read signal 53 output waveforms as shown in FIG. 2 by the timing generation circuit 7 and the control signal generation circuit 6.

The operation of the timing generation circuit 7 and the control signal generation circuit 6 is different from the operation at the time of erasing at the time of rewriting described above in that the latch clock signal 46 is not output, as can be seen from the configuration of FIG. Therefore, the description is omitted.

When the precharge signal 47 is output, the signal lines 35 to 37 are precharged. EEPR for storage
The OM cell gate voltage generation circuit 44 applies the VD to the cell gate signal 70 as shown in FIG.
Outputs the D voltage. At the same time, the amplifiers 32-34 are also turned on by the cell read signal 53, so that the storage EEPROM
The data of the cells 41 to 43 are read by the cell read signals 18 to 2.
Output to 0. By monitoring the values of the read signals 18 to 20, the number of rewrites can be observed.

FIG. 3 is an outline of the operation flow of the embodiment according to FIG. FIG. 4 shows the number of rewrites and the state of the storage EEPROM cells 41 to 43 in the circuit of FIG.

The operation of the storage EEPROM cells 41 to 43 and the stress caused by erasing and writing of the memory cells will be briefly described below with reference to FIGS. In the figure, once rewriting (erasing-writing) of the flash EEPROM and the control circuit 1 is performed once, the operation flow of FIG. 3 is executed, and as shown in FIG.
Data is written only to the ROM cell (41).

Next, when rewriting is performed again, writing is performed on the storage EEPROM cell (42) of FIG. At this time, the write operation is also performed on the storage EEPROM cell (41), but since the data has already been written, the charge is not taken in or out of the floating gate.

In this way, rewriting is performed X times (arbitrary value)
When implemented, the storage EEPROM cells (41-43)
Are written (filled out).

(Embodiment 2) FIG. 5 shows a second embodiment of the present invention. This embodiment corresponds to the storage EEPROM cells 41 to 43 in the first embodiment shown in FIG.
And the newly added storage EEPROM cells 60 to 63
To the respective storage EEPROM cell control circuits 15 to
17 is connected in parallel.

Therefore, the configuration of the internal circuits of the storage EEPROM cell control circuits 15 to 17 in FIG. 1 is changed. That is, the storage EEPROM cell control circuit 15
Are precharge circuits 29 and 54 and amplifiers 32 and 56
And the read signal 1 through the OR circuit 76.
8 is to be taken out. EEPROM for storage
The cell control circuit 15 has been described.
The same applies to the OM cell control circuits 16 and 17. In the second embodiment, a plurality of Es
By arranging the EPROM cells in parallel with the respective storage EEPROM cell control circuits 15 to 17, the reliability of the stored rewrite count value can be made higher than in the first embodiment.

The configuration of this embodiment includes a control signal generation circuit and a timing generation circuit 7 and a storage EEPROM.
The function of the M cell gate voltage generation circuit 44 is the same as that of FIG. The only difference between the embodiments shown in FIGS. 1 and 5 is the internal circuits of the write / read circuits 15-17.

Therefore, the description of the same parts as in FIG. 1 is omitted, and only the operation of the write / read circuit 15 when rewriting data in the flash EEPROM and the control circuit 1 will be described below.

Flash EEPROM and Control Circuit 1
When the data of the storage EEPROM cell 41 is erased by the precharge signal 47 and the cell read signal 53,
Is output to a signal line 74, and the value of the storage EEPROM cell 60 is output to a signal line 75. Next, the signal line 74,
The data 75 is ORed by the OR circuit 76, is output as the read signal 18, and is latched and latched by the latch clock 46.

Next, when newly writing data in the flash EEPROM and the control circuit 1, a write signal 5 is output, and the value of the data bus 8 is written to the address specified by the address signal 2. At the same time, according to the write signal 5, the output of the preceding latch is connected to the storage E connected in parallel.
Write to EPROM cells 41,60.

As described briefly above, the storage EEPR
By connecting OM cells in parallel, for example, EEPRO for storage
Even if one of the floating gates M41 and M60 loses its charge due to some cause (missing of retention), if one of them is normal, the stored count value shows a correct value.

[0054]

As described above, according to the present invention,
Since only the write operation is performed on the storage EEPROM cell that stores the number of rewrites, there is no deterioration. Therefore, the reliability of the count value of the number of times of rewriting of the flash EEPROM used by the user can be improved. E for storage
Since the EPROM cell is not erased, an erasing circuit becomes unnecessary, and the circuit can be prevented from becoming complicated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart of main signals according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an operation flow of the first embodiment of the present invention.

FIG. 4 is a diagram showing the number of times of rewriting and the state of an EEPROM cell for storing the number of times of rewriting in the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention.

FIG. 6 is a diagram showing an example of a conventional rewrite count storage circuit.

FIG. 7 is a schematic diagram of an operation flow of a conventional rewrite count storage circuit.

FIG. 8 is a diagram showing the number of times of rewriting and the state of an EEPROM cell for storing the number of times of rewriting in a conventional circuit for storing the number of times of rewriting.

FIG. 9 is a diagram showing a state of an EEPROM cell at the time of writing and erasing;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 flash type EEPROM and control circuit 2 address signal 3 read signal 4 erase signal 5 write signal 6 control signal generation circuit 7 timing generation circuit 8 data bus 15-17 write / read circuit 18-20 read signal 23-25 AND circuit 29-31 Precharge circuits 32 to 34 Amplifiers 41 to 43, 60 to 63 EEPROM cell for storage 44 EEPROM cell gate voltage generation circuit for storage 71 to 73 Latch

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[Procedure amendment]

[Submission date] August 20, 1999 (1999.8.2
0)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction contents]

[0020]

In order to achieve the above object, a nonvolatile memory rewrite count circuit according to the present invention counts the number of rewrites of a flash EEPROM and stores the count value. a counting circuit of the number of times of rewriting of, each time carrying out the rewriting operation, by writing one by one in the number of times of rewriting memory for EEP ROM cell, is performed stores the number of rewrites, writing, the number of times of rewriting the memory EEPROM cells Is performed only once for one cell.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction contents]

Further, it has an EEPROM cell gate voltage generation circuit for storing the number of rewrites , n write / read circuits, and n EEPROM cells for storing the number of rewrites, and counts the number of rewrites of the nonvolatile memory of the flash EEPROM. and, a counting circuit of the number of times of rewriting of the nonvolatile memory for storing the counted value, the number of rewrites Symbol <br/>憶用EEPROM cell gate voltage generation circuit, when writing new data in the flash type EEPROM, the n The EEPROM cell for storing the number of times of rewriting is set to be in a writable state. The n write / read circuits output a number-of-times-of-rewriting read signal when reading the number of times of rewriting , and the n number of EEPROMs for storing the number of times of rewriting.
The M cell is for writing data, and is a flash type EE
Each time the PROM is rewritten once, data is written into one storage EEPROM cell. When the rewriting is performed X (X = 1, 2, 3,..., N) times, a plurality of rewriting times are stored. X cells among the EEPROM cells for writing are written, the data of the EEPROM cell for storing the number of rewrites is output as a cell read signal, and the value of the cell read signal indicates the number of rewrites.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0022

[Correction method] Change

[Correction contents]

Each of the n write / read circuits has a plurality of EEPROM cells for storing the number of times of rewriting in parallel, and when rewriting data in the flash EEPROM and the control circuit, the n write / read circuits are connected in parallel to the respective write / read circuits. Data is read from or written to each connected EEPROM cell for storing the number of times of rewriting .

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction contents]

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a diagram showing a first embodiment of a flash EEPROM and a count and storage circuit for n times of rewriting of a control circuit 1 of the present invention.
FIG. 2 shows a timing chart of main signals in FIG. In FIG. 1, a counting circuit for counting the number of times of rewriting of a nonvolatile memory according to the present invention is a flash type EEPROM.
It is for rewriting of the OM and control circuit 1, and includes a timing generation circuit 7, a control signal generation circuit 6, an EEPROM cell gate voltage generation circuit 44 for storing the number of rewrites , n write / read circuits 15 to 17, and n Rewriting times
It is composed of EEPROM cells 41 to 43 for storing numbers .

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0030

[Correction method] Change

[Correction contents]

The EEPROM cell gate voltage generation circuit 44 for storing the number of times of rewriting outputs a VDD voltage to the cell gate signal 70 in response to the cell read signal 53. Therefore, the EEPROM cells 41 to 43 for storing the number of times of rewriting are turned on, and the signal lines 35 to 37 are at L level (GND level).

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0032

[Correction method] Change

[Correction contents]

The latches 71 to 73 latch the values of the read signals 18 to 20 according to the latch clock signal 46.
Next, when newly writing data in the flash EEPROM and the control circuit 1, a write signal 5 is output, and the value of the data bus 8 is written to the address specified by the address signal 2. At the same time, EEPROM for rewriting frequency storage
As shown in FIG. 2, the M cell gate voltage generation circuit 44 applies VPP (high voltage) to the cell gate signal 70 by the write signal 5.
Outputs, EEPROM cell 41 to rewrite frequency storage
43 is set in a writable state.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0034

[Correction method] Change

[Correction contents]

Therefore, the signal line 35 of the precharge circuit 29
Becomes the H level, and the H level is written into the EEPROM cell 41 for storing the number of times of rewriting . The write signal 5 and the output (L level) of the latch 71 are input to the AND circuit 24 of the write / read circuit 16 and output at the L level, and the analog switch 27 is turned off. Thus the signal line 36 of the precharge circuit 30 is in an open state, writing
The value of the EEPROM cell 42 for storing the number of changes does not change.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction contents]

Similarly, the values after the EEPROM cell 42 for storing the number of times of rewriting do not change. The results of such behavior, writing
Only the EEPROM cell 41 for storing the number of replacements , ie, 1
Only written to cells.

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0037

[Correction method] Change

[Correction contents]

Only the EEPROM cell 41 for storing the number of rewrites at the end of the first rewrite is at the H level.
At the time of erasing the second rewriting operation, the EEPROM cells 41 to 4 for storing the number of rewriting times are stored similarly to the first rewriting operation.
The value of 3 is latched in latches 71-73. Therefore, only latch 71 is set to the H level.

[Procedure amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction contents]

Next, at the time of writing, the data in the latches 71 to 73 is written in a shifted form, as in the first rewriting operation .
It is stored in EEPROM cells 42 to 43 for storing the number of times of replacement . In the example of FIG. 1, there is no EEPROM cell for storing the number of times of rewriting corresponding to the value of the latch of the write / read circuit 17.

[Procedure amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction contents]

As a result of such an operation, when rewriting is performed twice, only two cells, EEPROM cells 41 and 42 for storing the number of rewriting times , are written. The same operation as described above is performed in the third and subsequent rewriting operations. Therefore, X (X
= 1, 2, 3,..., N) times, X cells among the EEPROM cells for storing the number of times of rewriting are written (filled).

[Procedure amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction contents]

When the precharge signal 47 is output, the signal lines 35 to 37 are precharged. The EEPROM cell gate voltage generation circuit 44 for storing the number of times of rewriting outputs the VDD voltage to the cell gate signal 70 as shown in FIG. To ON also amplifiers 32 to 34 by the cell read signal 53 at the same time, to write conversion
The data of the EEPROM cells 41 to 43 for storing the number of times
Output to cell read signals 18-20. By monitoring the values of the read signals 18 to 20, the number of rewrites can be observed.

[Procedure amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction contents]

FIG. 3 is an outline of the operation flow of the embodiment according to FIG. FIG. 4 shows the number of rewrites and the states of the EEPROM cells 41 to 43 for storing the number of rewrites in the circuit of FIG.

[Procedure amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0044

[Correction method] Change

[Correction contents]

The operation of the storage EEPROM cells 41 to 43 and the stress caused by erasing and writing of the memory cells will be briefly described below with reference to FIGS. In the figure, the rewriting of the flash EEPROM and the control circuit 1 - the the (erase writing) is performed once, and executes the operation flow of FIG. 3, the number of rewrites SL <br/>憶用in FIG. 1, as shown in FIG. 4 Data is written only to the EEPROM cell (41).

[Procedure amendment 16]

[Document name to be amended] Statement

[Correction target item name] 0045

[Correction method] Change

[Correction contents]

Next, when rewriting is performed again, writing is performed on the storage EEPROM cell (42) of FIG. At this time, the write operation is also performed on the EEPROM cell (41) for storing the number of times of rewriting, but since the data has already been written, the charge is not taken in and out of the floating gate.

[Procedure amendment 17]

[Document name to be amended] Statement

[Correction target item name] 0046

[Correction method] Change

[Correction contents]

In this way, rewriting is performed X times (arbitrary value)
In this case, X of the EEPROM cells (41 to 43) for storing the number of times of rewriting are written (painted).

[Procedure amendment 18]

[Document name to be amended] Statement

[Correction target item name] 0047

[Correction method] Change

[Correction contents]

(Embodiment 2) FIG. 5 shows a second embodiment of the present invention. This embodiment includes a number of rewriting the memory EEPROM cells 41 through 43 in the first embodiment shown in FIG. 1, EE for the newly added number of times of rewriting memory
The PROM cells 60 to 63 are connected in parallel to respective EEPROM cell control circuits 15 to 17 for rewriting .

[Procedure amendment 19]

[Document name to be amended] Statement

[Correction target item name] 0048

[Correction method] Change

[Correction contents]

Therefore, the rewriting frequency storage E shown in FIG.
The configuration of the internal circuits of the EPROM cell control circuits 15 to 17 is different. That is, the EEPROM for storing the number of times of rewriting
The OM cell control circuit 15 includes precharge circuits 29 and 54
And amplifiers 32 and 56 in parallel, and the readout signal 18 is extracted through an OR circuit 76. Although the EEPROM cell control circuit 15 for storing the number of rewrites has been described above, the same applies to the EEPROM cell control circuits 16 and 17 for storing the number of rewrites . In the second embodiment, a plurality of rewrite frequency storage EEPROMs
EEPROM for storing the number of rewrites for each OM cell
By providing the cell control circuits 15 to 17 in parallel, it is possible to increase the reliability of the stored rewrite count value as compared with the first embodiment.

[Procedure amendment 20]

[Document name to be amended] Statement

[Correction target item name] 0049

[Correction method] Change

[Correction contents]

As the configuration of this embodiment, the functions of the control signal generation circuit and timing generation circuit 7 and the EEPROM cell gate voltage generation circuit 44 for storing the number of times of rewriting are as follows.
It is the same as that of FIG. The difference in the configuration between the embodiment of FIG. 1 and FIG.
Is only an internal circuit.

[Procedure amendment 21]

[Document name to be amended] Statement

[Correction target item name] 0051

[Correction method] Change

[Correction contents]

Flash EEPROM and Control Circuit 1
In the case of erasing the data, the precharge signal 47 and the cell read signal 53 are used to store the rewrite frequency
The value of OM cell 41 is output to the signal line 74, rewriting times
The value of the number storage EEPROM cell 60 is output to a signal line 75. Next, the data on the signal lines 74 and 75 are
Is output to the read signal 18 and latched by the latch clock 46.

[Procedure amendment 22]

[Document name to be amended] Statement

[Correction target item name] 0052

[Correction method] Change

[Correction contents]

Next, when newly writing data in the flash EEPROM and the control circuit 1, a write signal 5 is output, and the value of the data bus 8 is written to the address specified by the address signal 2. At the same time, the output of the previous-stage latch is rewritten in parallel by the write signal 5.
The data is written into the EEPROM cells 41 and 60 for storing the number of times .

[Procedure amendment 23]

[Document name to be amended] Statement

[Correction target item name] 0053

[Correction method] Change

[Correction contents]

[0053] above, simply it has been described, writing for example by connecting the rewrite frequency Symbol <br/>憶用EEPROM cells in parallel
Even if the charge of one of the floating gates of the EEPROMs 41 and 60 for changing the number of charges is lost due to some cause (holding loss), if one of them is normal,
The stored count indicates the correct value.

[Procedure amendment 24]

[Document name to be amended] Statement

[Correction target item name] 0054

[Correction method] Change

[Correction contents]

[0054]

As described above, according to the present invention,
EEPROM for storing the number of times of rewriting for storing the number of times of rewriting
Since only the write operation is performed on the M cell, there is no deterioration. Therefore, flash EEP used by users
The reliability of the count value of the number of times of rewriting of the ROM can be improved.
Further, since the EEPROM cell for storing the number of times of rewriting is not erased, an erasing circuit becomes unnecessary, and the circuit can be prevented from becoming complicated.

[Procedure amendment 25]

[Document name to be amended] Statement

[Correction target item name] Brief description of drawings

[Correction method] Change

[Correction contents]

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart of main signals according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an operation flow of the first embodiment of the present invention.

FIG. 4 is a diagram showing the number of rewrites and the state of an EEPROM cell for storing the number of rewrites according to the first embodiment of the present invention;

FIG. 5 is a circuit diagram showing a second embodiment of the present invention.

FIG. 6 is a diagram showing an example of a conventional rewrite count storage circuit.

FIG. 7 is a schematic diagram of an operation flow of a conventional rewrite count storage circuit.

FIG. 8 is a diagram showing the number of times of rewriting and the state of an EEPROM cell for storing the number of times of rewriting in a conventional circuit for storing the number of times of rewriting.

FIG. 9 is a diagram showing a state of an EEPROM cell at the time of writing and erasing;

[Description of Signs] 1 Flash EEPROM and control circuit 2 Address signal 3 Read signal 4 Erase signal 5 Write signal 6 Control signal generation circuit 7 Timing generation circuit 8 Data bus 15-17 Write / read circuit 18-20 Read signal 23-25 AND circuit 29-31 Precharge circuit 32-34 Amplifier 41-43, 60-63 EEPROM for storing rewrite frequency
OM cell 44 EEPROM cell gate voltage generation circuit for storing the number of rewrites 71 to 73 Latch

Claims (3)

[Claims] 1. A circuit for counting the number of rewrites of a flash EEPROM and storing the count, the number of rewrites of a non-volatile memory, wherein the number of rewrites is stored every time a rewrite operation is performed. The writing is performed by writing the EEPROM cells one by one.
A circuit for counting the number of rewrites of a nonvolatile memory, wherein the circuit is performed only once for a cell. 2. A flash EEPROM comprising a storage EEPROM cell gate voltage generation circuit, n write / read circuits, and n storage EEPROM cells.
The rewriting frequency counting circuit of the non-volatile memory counts the number of rewriting times of the non-volatile memory, and stores the count value. The storage EEPROM cell gate voltage generation circuit generates n
N write / read circuits output a rewrite count read signal when reading the number of rewrites, and the n storage EEPROM cells store data Each time the rewriting of the flash EEPROM is performed once, data is written to one storage EEPROM cell, and the rewriting is performed by X (X = 1, 2, 3,...,
When n) times are performed, X cells out of the plurality of storage EEPROM cells are written, the data of the storage EEPROM cells is output as a cell read signal, and the value of the cell read signal indicates the number of rewrites. Circuit for counting the number of rewrites of a nonvolatile memory. 3. The n write / read circuits each have a plurality of storage EEPROM cells in parallel, and are connected in parallel to each of the write / read circuits when rewriting data in the flash EEPROM and the control circuit. 3. The circuit according to claim 2, wherein data is read from or written to each of the storage EEPROM cells.