JP2000215697A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately determine deterioration in a memory cell. SOLUTION: This memory device comprises a timing control circuit 1, a memory circuit 9, a high voltage control circuit 10, a voltage control circuit 11, a data comparison circuit 12 and a write data hold circuit 13. The write data hold circuit 13 holds the value to be stored in the memory cell of the memory circuit 9. The stored value is compared with the value stored in the memory cell of the memory circuit 9 in the data comparison circuit 12 and when comparison value is different, an alarm signal is output. In this case, the voltage control circuit 11 supplies a voltage different from the voltage level applied during the ordinary read operation to the word line connected to the control gate of the memory cell of the memory circuit 9. Thereby, a read operation for detecting deterioration is performed only once and an alarm signal is output when the memory cell is deteriorated and moreover the normal value of the memory cell is held during output of the alarm signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device in which immediately after rewriting of a memory cell, reading is performed under stricter conditions than in normal reading, and a deterioration state is determined.

[0002]

2. Description of the Related Art Conventionally, in this type of nonvolatile semiconductor memory device, for example, there is an example in which a floating gate formed on a silicon substrate accumulates electric charges and stores information.
In this example, the state in which the information is erased and the state in which the information is written (appropriately referred to as erase / write) are as follows.
The charge is stored in the floating gate and realized in a state higher than the threshold when the control gate is used as a reference.
This is realized in a state where the charge accumulated in the floating gate is extracted and the threshold value is lower than the threshold value with respect to the control gate.

Next, the erasing / writing will be described. FIG. 3 is an equivalent circuit diagram showing the state of the memory cell at the time of erasing / writing, and FIG. 4 is a characteristic diagram when erasing / writing is repeated for the memory cell. FIG. 5 is a diagram for explaining a threshold voltage distribution when erasing / writing is performed.

[0004] Information is erased, for example, by referring to FIGS.
As shown in FIG. 2, a high voltage VC (for example, 1
0 to 20 V) and the drain D is set to the ground (GND) level, whereby charges are accumulated in the floating gate F via the tunnel oxide film. When charges are accumulated in the floating gate, the threshold voltage as viewed from the control gate G increases (for example, 6 to 9 V). As a result, when reading is performed by applying a voltage (for example, 5 V) to the control gate G, no current flows between the source and the drain. That is, the information of the logical value “0” is written.

To write information having a logical value of “1”, a high voltage VD (for example, 10 to 20 V) is applied to the drain D.
And the control gate G is set to the ground (GND) level to discharge the charge stored in the floating gate F. When charge is extracted from the floating gate F, the threshold voltage seen from the control gate G decreases (for example, 1
３3V). Therefore, a voltage (for example, 5) is applied to the control gate G.
When reading is performed by applying V), a current flows between the source and the drain. That is, the information of the logical value “1” is written.

In such a nonvolatile semiconductor memory device,
Due to the repetition of erasing / writing, the element deterioration gradually progresses, and eventually, there is a characteristic that erasing / writing cannot be performed. FIG. 4 shows the deterioration characteristics of the erasing / writing.
The difference in threshold value due to writing becomes smaller.

In the following example, a state where the threshold voltage is high will be referred to as an erase state, and a state where the threshold voltage is low will be referred to as a write state. As described above, in the non-volatile semiconductor memory device, the erasing / writing cannot be repeated finally. Therefore, in general, the number of times of writing is limited by the sample evaluation, and the operation is guaranteed within the number of times of writing. ing. In this case, the fact that normal erasing / writing cannot be performed means that internal information is lost. In order to prevent the use of the non-volatile semiconductor memory device in which the erasing / writing cannot be performed, various methods for judging and displaying the life of the memory cell have been considered.

As a conventional technique for determining the life of a memory cell, for example, an example disclosed in Japanese Patent Application Laid-Open No. H10-112192 “Semiconductor Storage Device” is known. In this conventional example, although the deterioration is determined based on the threshold value, a different control gate voltage is applied to the memory cell whose value has been rewritten, and the reading is performed twice. When the result of the two readings is different, the memory cell deterioration is detected.

FIG. 5A shows this conventional example.
FIG. 5C shows a threshold voltage distribution when data is normally erased, and FIG. 5C shows a threshold voltage distribution when data is normally written. This corresponds to the state in FIG. 4 where the number of rewrites is small and the memory cell is not deteriorated. FIG. 5B shows a threshold voltage distribution when erasing is performed on the deteriorated memory cell, and FIG. 5D shows a case where writing is performed on the deteriorated memory cell. 3 shows the threshold voltage distribution at this time. This corresponds to a state in which the memory cell is deteriorated by repeatedly performing rewriting in FIG.

In any of these states, the threshold voltage in the erase / write state slightly varies due to the variation in the characteristics of the memory cell itself. As described above, due to the deterioration of the memory cell, the threshold value at the time of erasing gradually decreases, and the threshold value at the time of writing gradually increases.

Using this change characteristic, the deterioration of the memory cell is determined based on the change in the threshold value at the time of erasing / writing. In a normal read operation, a read operation is performed by applying a gate voltage of a voltage V1 lower than the threshold voltage when normal erasing is performed and higher than the voltage Vcc applied to the control gate. Next, reading is performed by applying a gate voltage of a voltage V2 which is higher than the threshold voltage when writing is normally performed and lower than the voltage Vcc.

When erasing or writing is performed when the memory cell is not deteriorated, the result of applying voltage V1 to the control gate to perform reading is equal to the result of applying voltage V2 to the control gate and performing reading. Become.

When the memory cell is deteriorated, the voltage V1
Is applied to the control gate to perform reading and the voltage V
2 is applied to the control gate and the result of reading is different. Thereby, the deterioration of the memory cell can be detected.

In the conventional example of Japanese Patent Application Laid-Open No. 10-55691, "Non-volatile semiconductor memory", the control gate voltage is gradually changed, reading is repeatedly performed, and the threshold value of the memory cell is determined. Writing is performed until a normal value is held.

Further, in the example of JP-A-7-45084, a counter is provided for counting the number of rewrites for each data write address. When the number of rewrites reaches a predetermined count value, if there is a rewrite request for this address, the address is switched to rewrite to a spare address to extend the life of the memory. That is, in the case where rewriting to a specific address frequently occurs with respect to rewriting to another address, it is possible to prevent the memory cell of a specific address from becoming unusable due to the end of its life. I have.

[0016]

In such a conventional non-volatile semiconductor memory device, when detecting deterioration of a memory cell, it is necessary to apply different voltages to the control gate and perform two readings. Further, if the memory cell has already stopped functioning normally at the time of erasing / writing, this inoperability cannot be detected. In other words, there is a disadvantage that it is not possible to detect that deterioration has occurred after the normal value is held in the memory cell.

For example, when writing to a certain memory cell, first, after erasing the memory cell, writing is performed. However, when a memory cell is not functioning properly and erasing has been performed but writing has not been performed normally, actually, even though writing has been performed on that memory cell, Is in the state where only the erasure has been performed. At this time, if the threshold voltage after erasing is sufficiently high and higher than the voltage V1, the voltage V1 is obtained even though the memory cell is not functioning properly.
Is applied to the control gate to perform reading and the voltage V
2 is applied to the control gate and the result of reading is equal, and it cannot be detected that the memory cell is not functioning properly.

The present invention has been made to solve the above-mentioned problems in the prior art, and makes it possible to accurately determine the state of deterioration of the nonvolatile memory, and as a result, it is possible to use the nonvolatile memory efficiently. The purpose of the present invention is to provide a non-volatile semiconductor memory device. In particular, the present invention achieves the following object together with the accurate determination of the deterioration state. (1) Readout for deterioration detection needs to be performed only once. (2) Output a warning signal when the memory cell is deteriorated. (3) When the alarm signal is output, the normal value in the memory cell is held.

[0019]

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention comprises an electrically rewritable semiconductor memory element and selectively writing data to the semiconductor memory element. A write data holding circuit for holding a value to be stored in the semiconductor storage element, and a value stored in the write data holding circuit and a value stored in the semiconductor storage element. And a data comparison circuit for comparing

In the comparison of the data comparison circuit, when the value stored in the write data holding circuit is different from the value stored in the semiconductor storage element, an alarm signal is output.

Further, the semiconductor memory device further comprises a voltage controller for supplying a voltage different from a voltage level applied during a normal read operation to a word line connected to a control gate of the semiconductor memory element.

Further, a counter for counting the number of rewrites is provided for each address for writing data to the semiconductor memory element, and an alarm signal is issued when the number of rewrites in the counter reaches a predetermined count value. There is an output configuration. Also, when the number of rewrites in the counter reaches a predetermined count value, an alarm signal is output, and when there is a rewrite request for the address that output the alarm signal, the address is rewritten to a spare address. Is switched.

Further, a read signal, a write signal, and a precharge signal are inputted as the storage processing means,
A timing controller for controlling data write / read timing, a Y decoder for selecting a bit line, an address latch for holding an address signal,
An X decoder for selecting a word line; an input / output buffer data latch circuit for buffering input / output of write / read data; a sense amplifier for amplifying and outputting a read data signal; A write circuit for outputting data corresponding to the write data held by the output buffer data latch circuit, a multiplexer for setting the write data at a position selected by the Y decoder, and control of a memory cell in the semiconductor memory device for writing And a high voltage control unit for applying a high voltage to the gate.

The nonvolatile semiconductor memory device of the present invention having such a configuration holds a value stored in a memory cell in a semiconductor storage element, and compares the held value with a value stored in the memory cell by a data comparison circuit. Compare and output an alarm signal when the value of the comparison is different. At this time, a voltage different from the voltage level applied during the normal read operation is supplied to the word line connected to the control gate of the memory cell.

That is, a value to be written to a memory cell in a semiconductor memory element is stored in a write circuit in advance, and immediately after a write operation is performed on the memory cell,
Reading is performed from the memory cell under stricter conditions than during normal reading, and the state of deterioration is determined by comparing whether the written value matches the read value.

In this way, it is possible to accurately determine the state of deterioration of the nonvolatile memory. That is, reading for deterioration detection is required only once. In addition, an alarm signal can be output when the memory cell is deteriorated,
The normal value in the memory cell can be held when the alarm signal is output, and as a result, the nonvolatile memory can be used efficiently.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention. In FIG. 1, the nonvolatile semiconductor memory device includes a read signal (rea)
d), a write signal (write), and a precharge signal (precharge) are input, and data (dat)
a) a timing control unit 1 for controlling write / read timing, a Y decoder 2 for selecting a bit line, an address latch unit 3 for holding (latch) an address signal (address), and selecting a word line. And an input / output buffer data latch circuit 5 for buffering (latch) input / output of write / read data (data).

The nonvolatile semiconductor memory device has a sense amplifier 6 for amplifying and outputting a read data signal.
A write circuit 7 for outputting data corresponding to the write data held by the input / output buffer data latch circuit 5 to the multiplexer 8, and a multiplexer 8 for setting the write data at a position selected by the Y decoder 2. A memory unit 9 in which data is written / read by applying a voltage to a control gate of a memory cell;
A high voltage control unit 10 for applying a high voltage to a control gate of a memory cell in the memory unit 9 for performing writing is provided.

Further, in this nonvolatile semiconductor memory device, a voltage control section 11 for applying an arbitrary voltage to the control gate when detecting a deterioration state, and an arbitrary voltage applied to the control gate by the voltage control section 11 By doing so, the value read from the memory unit 9 is compared with the value held by the write data holding circuit 13, and when the data is different, an alarm signal S1 is output.
4 and a write data holding circuit 13 for holding a value written in the memory unit 9.

Next, the operation of this embodiment will be described. First, at the time of writing, a write signal (write)
Is input to the timing control unit 1, and the write address data (address) is further stored in the address latch unit 3.
(Address port). Further, the write data (data) is stored in the input / output buffer data latch circuit 5.
(Input / output port). At this time, the latch signal from the timing control unit 1 is output to the address latch unit 3 and the input / output buffer data latch circuit 5, and the write address (address) is stored in the address latch unit 3.
And the write data is held by the input / output buffer data latch circuit 5.

The input / output buffer data latch circuit 5
Is output to the write circuit 7, and outputs data corresponding to the write data to the multiplexer 8. Further, the write address data held by the address latch unit 3 is output to the Y decoder 2 and the X decoder 4, and the write address (addres
The word line s) is selected, and the multiplexer 8 sets the write data input from the write circuit 7 at the position selected by the Y decoder 2. A control signal is output from the timing control unit 1 to the high voltage control unit 10,
The high voltage control unit 10 applies a high voltage to the control gate of the memory cell in the memory unit 9 to which the writing is performed, and the writing is performed.

Next, at the time of reading, a read signal (re
ad) is input to the timing controller 1, and read address data is input to the address port. Read address data is held in the address latch unit 3,
The read address data held here is selected through the Y decoder 2, the X decoder 4, and the multiplexer 8 to select a word line and a bit line. A control signal is output from the timing control unit 1 to the voltage control unit 11. The voltage output from the voltage control unit 11 is applied to a control gate of a memory cell of the memory unit 9 that performs reading. Read data (signal) based on the designated read address data is amplified by the sense amplifier 6 and sent to the input / output port through the input / output buffer data latch circuit 5.

Next, the operation of the main part corresponding to the present invention will be described. Hereinafter, FIG. 3 (the state of the memory cell at the time of erasing / writing) and FIG.
A description will be given with reference to FIG. 5 (characteristics when writing is repeated) and FIG. 5 (threshold voltage distribution when erasing / writing is performed). FIG. 2 is a diagram for explaining a control gate voltage applied when deterioration is detected.

Due to the life of the memory section 9, the value stored in the memory cell cannot be read even when reading is performed by applying a predetermined voltage to the control gate. For example, as shown in FIG. 5, when erasing is performed, if the threshold voltage of the memory cell is lower than the control gate voltage at the time of reading, a current flows between the source and the drain. Therefore, the data of the logical value “1” is stored, and the memory cell has reached the end of its life. Then, when rewriting is repeated, the threshold value of the memory cell changes as shown in FIG. Using this change characteristic, it can be determined that the memory cell will reach the end of its life.

For example, reading is performed by applying a voltage higher than the control gate voltage applied during normal reading to the erased memory cell. That is, read is performed by applying the control gate voltage at the time of deterioration detection shown in FIG. 5 to the control gate. If normal reading cannot be performed by this reading, it is determined that the memory cell will soon reach the end of its life. At this point, the lost value can still be read out normally by applying the control gate voltage during normal reading. That is, the data held in the memory unit 9 does not disappear.

The judgment (detection of deterioration) that the memory cell reaches the end of its life will be specifically described. First, the memory unit 9
When an erasing / writing request is made to any of the addresses, the write data holding circuit 13 fetches and holds input data to be stored in the memory cell from outside. Next, immediately after erasing / writing to an arbitrary address, reading is performed by applying a control gate voltage at the time of detection of deterioration from the voltage control unit 11. The read value and the write value held by the write data holding circuit 13 are compared with the data comparison circuit 1.
Compare with 2. If the read value differs from the write value in this comparison, an alarm signal S14 is output to the outside. The alarm signal S14 allows, for example, a CPU (not shown) to recognize that the memory section 9 is about to reach the end of its life.

Conversely, in the case of this reading, the deterioration can be detected similarly for the value at the time of writing. In this case, by applying a voltage lower than the control gate voltage applied during normal reading and performing reading, reading can be performed under more strict conditions than during normal reading. The procedure of the deterioration detection is the same as the procedure of strictly reading the condition for the erased value, except that the control gate voltage value at the time of the deterioration detection is different.

Whether to use the deterioration detection in the reading or the deterioration detection in the writing is determined by previously determining which of the erasing failure and the writing failure in the memory section 9 occurs first. In addition, both deterioration detections are performed, and the deterioration detection in the previously detected reading or the deterioration detection in the writing is performed.
The deterioration detection may be determined.

As described above, it is possible to determine whether the value stored in the memory unit 9 has been normally stored. Further, the deterioration state of the memory cell (memory section 9) that has been erased / written can be accurately determined. In this case, the stored data needs to be read only once.

In such deterioration detection processing, an extra read (or write) operation for confirming the stored value is required. The operation in this case does not cause the deterioration of the memory cell to progress. When erasing / writing is performed on a memory cell, holes / charges are injected into a floating gate by applying a high voltage to a control gate or a drain.

FIG. 2 is an equivalent circuit showing the state of a memory cell when erasing / writing is performed. At the time of erasing / writing, charges move between the floating gate F and the drain D. Repeatedly rewriting,
Although the number of traps in the tunnel oxide film increases and the memory cell deteriorates, the charge does not move at the time of reading. Therefore, the deterioration of the memory cell due to the increase in the number of readings is extremely small as compared with the erasing / writing. No consideration is necessary.

Next, another embodiment will be described. In this embodiment, in the above-described Japanese Patent Application Laid-Open No. 7-45084 (when a rewrite request for this address is issued when the number of rewrites reaches a predetermined count value, rewriting to a spare address is performed). To increase the life of the memory). That is, there is a concern that the memory cell may be degraded due to unnecessary reading that rewriting to a specific address frequently occurs with respect to rewriting to another address, and it is necessary to perform reading. To save a certain amount of time, a separate counter is provided, and rewriting is counted by this counter. The deterioration state is detected only when the count value is equal to or more than a predetermined number. That is, deterioration is detected every fixed number of times of rewriting, and deterioration detection is performed every time rewriting exceeds a certain number of times.

In this case, in the configuration of FIG. 1, at the time when the data comparison circuit 12 outputs the alarm signal S14, the rewrite request for this address is switched to a spare address. This address switching is performed by detecting the actual state of deterioration by applying the control gate voltage at the time of deterioration detection as described above, without making a determination based on the number of rewrites. Therefore, it is possible to more accurately detect the actual deterioration state.

[0044]

As is apparent from the above description, according to the nonvolatile semiconductor memory device of the present invention, the value stored in the memory cell in the semiconductor memory element is held, and the held value and the value stored in the memory cell are stored. Is compared with a data comparison circuit, and when the comparison value is different, an alarm signal is output. At this time, a voltage different from the voltage level applied during the normal read operation is supplied to the word line connected to the control gate of the memory cell.

As a result, the state of deterioration of the nonvolatile memory can be accurately determined. That is, reading for deterioration detection is required only once. In addition, an alarm signal can be output when the memory cell is deteriorated, and a normal value in the memory cell can be maintained when the alarm signal is output, thereby enabling efficient use of the nonvolatile memory. Become.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a control gate voltage applied at the time of detecting deterioration in the embodiment.

FIG. 3 is an equivalent circuit diagram showing a state of a memory cell at the time of erasing / writing.

FIG. 4 is a characteristic diagram when erasing / writing is repeated for a memory cell.

FIG. 5 is a diagram for explaining a threshold voltage distribution when erasing / writing is performed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Timing control part 2 Y decoder 3 Address latch part 4 X decoder 5 I / O buffer data latch circuit 6 Sense amplification part 7 Writing circuit 8 Multiplexer 9 Memory part 10 High voltage control part 11 Voltage control part 12 Data comparison circuit 13 Writing Data holding circuit S14 Alarm signal

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[Procedure amendment]

[Submission Date] November 26, 1999 (1999.11.
26)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

[Title of the Invention] Nonvolatile semiconductor memory device

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device in which immediately after rewriting of a memory cell, reading is performed under stricter conditions than in normal reading, and a deterioration state is determined.

[0002]

2. Description of the Related Art Conventionally, in this type of nonvolatile semiconductor memory device, for example, there is an example in which a floating gate formed on a silicon substrate accumulates electric charges and stores information.
In this example, the state in which the information is erased and the state in which the information is written (appropriately referred to as erase / write) are as follows.
The charge is stored in the floating gate and realized in a state higher than the threshold when the control gate is used as a reference.
This is realized in a state where the charge accumulated in the floating gate is extracted and the threshold value is lower than the threshold value with respect to the control gate.

Next, the erasing / writing will be described. FIG. 3 is an equivalent circuit diagram showing the state of the memory cell at the time of erasing / writing, and FIG. 4 is a characteristic diagram when erasing / writing is repeated for the memory cell. FIG. 5 is a diagram for explaining a threshold voltage distribution when erasing / writing is performed.

[0004] Information is erased, for example, by referring to FIGS.
As shown in FIG. 2, a high voltage VC (for example, 1
0 to 20 V) and the drain D is set to the ground (GND) level, whereby charges are accumulated in the floating gate F via the tunnel oxide film. When charges are accumulated in the floating gate, the threshold voltage as viewed from the control gate G increases (for example, 6 to 9 V). As a result, when reading is performed by applying a voltage (for example, 5 V) to the control gate G, no current flows between the source and the drain. That is, the information of the logical value “0” is written.

To write information having a logical value of “1”, a high voltage VD (for example, 10 to 20 V) is applied to the drain D.
And the control gate G is set to the ground (GND) level to discharge the charge stored in the floating gate F. When charge is extracted from the floating gate F, the threshold voltage seen from the control gate G decreases (for example, 1
３3V). Therefore, a voltage (for example, 5) is applied to the control gate G.
When reading is performed by applying V), a current flows between the source and the drain. That is, the information of the logical value “1” is written.

In such a nonvolatile semiconductor memory device,
Due to the repetition of erasing / writing, the element deterioration gradually progresses, and eventually, there is a characteristic that erasing / writing cannot be performed. FIG. 4 shows the deterioration characteristics of the erasing / writing.
The difference in threshold value due to writing becomes smaller.

In the following example, a state where the threshold voltage is high will be referred to as an erase state, and a state where the threshold voltage is low will be referred to as a write state. As described above, in the non-volatile semiconductor memory device, the erasing / writing cannot be repeated finally. Therefore, in general, the number of times of writing is limited by the sample evaluation, and the operation is guaranteed within the number of times of writing. ing. In this case, the fact that normal erasing / writing cannot be performed means that internal information is lost. In order to prevent the use of the non-volatile semiconductor memory device in which the erasing / writing cannot be performed, various methods for judging and displaying the life of the memory cell have been considered.

As a conventional technique for determining the life of a memory cell, for example, an example disclosed in Japanese Patent Application Laid-Open No. H10-112192 “Semiconductor Storage Device” is known. In this conventional example, although the deterioration is determined based on the threshold value, a different control gate voltage is applied to the memory cell whose value has been rewritten, and the reading is performed twice. When the result of the two readings is different, the memory cell deterioration is detected.

FIG. 5A shows this conventional example.
FIG. 5C shows a threshold voltage distribution when data is normally erased, and FIG. 5C shows a threshold voltage distribution when data is normally written. This corresponds to the state in FIG. 4 where the number of rewrites is small and the memory cell is not deteriorated. FIG. 5B shows a threshold voltage distribution when erasing is performed on the deteriorated memory cell, and FIG. 5D shows a case where writing is performed on the deteriorated memory cell. 3 shows the threshold voltage distribution at this time. This corresponds to a state in which the memory cell is deteriorated by repeatedly performing rewriting in FIG.

In any of these states, the threshold voltage in the erase / write state slightly varies due to the variation in the characteristics of the memory cell itself. As described above, due to the deterioration of the memory cell, the threshold value at the time of erasing gradually decreases, and the threshold value at the time of writing gradually increases.

By utilizing this change characteristic, two types of judgment electric
By using the pressure, the deterioration of the memory cell is determined based on the change in the threshold value at the time of erasing / writing. the first
To lower than the threshold voltage when erasing is performed normally, and to read a high determination voltage V1 than the voltage Vcc applied to the control gate is applied as a gate voltage. Then, normally higher than the threshold voltage when the write is performed, and performs reading by applying a low determination voltage V2 than the voltage Vcc as the gate voltage.

When erasing or writing is performed when the memory cell is not deteriorated, the result of applying voltage V1 to the control gate to perform reading is equal to the result of applying voltage V2 to the control gate and performing reading. Become.

When the memory cell is deteriorated, the voltage V1
Is applied to the control gate to perform reading and the voltage V
2 is applied to the control gate and the result of reading is different. Thereby, the deterioration of the memory cell can be detected.

In the conventional example of Japanese Patent Application Laid-Open No. 10-55691, "Non-volatile semiconductor memory", the control gate voltage is gradually changed, reading is repeatedly performed, and the threshold value of the memory cell is determined. Writing is performed until a normal value is held.

Further, in the example of JP-A-7-45084, a counter is provided for counting the number of rewrites for each data write address. When the number of rewrites reaches a predetermined count value, if there is a rewrite request for this address, the address is switched to rewrite to a spare address to extend the life of the memory. That is, in the case where rewriting to a specific address frequently occurs with respect to rewriting to another address, it is possible to prevent the memory cell of a specific address from becoming unusable due to the end of its life. I have.

[0016]

In such a conventional non-volatile semiconductor memory device, when detecting deterioration of a memory cell, it is necessary to apply different voltages to the control gate and perform two readings. Further, if the memory cell has already stopped functioning normally at the time of erasing / writing, this inoperability cannot be detected. In other words, there is a disadvantage that it is not possible to detect that deterioration has occurred after the normal value is held in the memory cell.

For example, when writing to a certain memory cell, first, after erasing the memory cell, writing is performed. However, when a memory cell is not functioning properly and erasing has been performed but writing has not been performed normally, actually, even though writing has been performed on that memory cell, Is in the state where only the erasure has been performed. At this time, if the threshold voltage after erasing is sufficiently high and higher than the voltage V1, the voltage V1 is obtained even though the memory cell is not functioning properly.
Is applied to the control gate to perform reading and the voltage V
2 is applied to the control gate and the result of reading is equal, and it cannot be detected that the memory cell is not functioning properly.

The present invention has been made to solve the above-mentioned problems in the prior art, and makes it possible to accurately determine the state of deterioration of the nonvolatile memory, and as a result, it is possible to use the nonvolatile memory efficiently. The purpose of the present invention is to provide a non-volatile semiconductor memory device. In particular, the present invention achieves the following object together with the accurate determination of the deterioration state. (1) Readout for deterioration detection needs to be performed only once. (2) Output a warning signal when the memory cell is deteriorated. (3) When the alarm signal is output, the normal value in the memory cell is held.

[0019]

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention comprises an electrically rewritable semiconductor memory element and selectively writing data to the semiconductor memory element. A write data holding circuit for holding a value to be stored in the semiconductor storage element, and a threshold value provided to a control gate of the semiconductor storage element.
A voltage control unit for supplying a voltage for detecting deterioration of the
The above value was written to the semiconductor storage element from the path
Later, the value stored in the write data holding circuit and the value before
Read by the deterioration detection voltage from the voltage control unit.
And a data comparator circuit for comparing the been has been stored in the semiconductor memory device value, according to the data comparison circuit
As a result of the comparison, the value stored in the write data
When the value stored in the conductor storage element differs from the
Signal is output .

The comparison by the comparison circuit is performed by the semiconductor memory.
For each write address of data to the storage element,
A counter that counts the number of replacements is provided.
Has reached a predetermined count value
It is a configuration that is sometimes performed .

Further, the comparison by the comparison circuit is performed by
For each data write address to the conductor storage element
Is provided with a counter that counts the number of rewrites.
The configuration is such that the counter is rewritten every time the number of times exceeds a certain number .

Further, the address at which the alarm signal was output is
To a spare address when a rewrite request
It is configured to perform switching for rewriting .

The nonvolatile semiconductor memory device of the invention having such a structure, holds a value stored in the memory cells in the semiconductor memory device, and a value stored in the held value with the memory cell data comparison circuit Compare and output an alarm signal when the value of the comparison is different. At this time, a voltage different from the voltage level applied during the normal read operation is supplied to the word line connected to the control gate of the memory cell.

[0024] That is, the value to be written to the memory cells in the semiconductor memory device, it is stored in advance in the write circuit, immediately after performing the write operation on the memory cells,
Reading is performed from the memory cell under stricter conditions than during normal reading, and the state of deterioration is determined by comparing whether the written value matches the read value.

In this way, the state of deterioration of the nonvolatile memory can be accurately determined. That is, reading for deterioration detection is required only once. In addition, an alarm signal can be output when the memory cell is deteriorated,
The normal value in the memory cell can be held when the alarm signal is output, and as a result, the nonvolatile memory can be used efficiently.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention. In FIG. 1, the nonvolatile semiconductor memory device includes a read signal (rea)
d), a write signal (write), and a precharge signal (precharge) are input, and data (dat)
a) a timing control unit 1 for controlling write / read timing, a Y decoder 2 for selecting a bit line, an address latch unit 3 for holding (latch) an address signal (address), and selecting a word line. And an input / output buffer data latch circuit 5 for buffering (latch) input / output of write / read data (data).

[0027] The sense amplifier section 6 non-volatile semiconductor memory device, for amplifying and outputting a signal of the read data
A write circuit 7 for outputting data corresponding to the write data held by the input / output buffer data latch circuit 5 to the multiplexer 8, and a multiplexer 8 for setting the write data at a position selected by the Y decoder 2. A memory unit 9 in which data is written / read by applying a voltage to a control gate of a memory cell;
A high voltage control unit 10 for applying a high voltage to a control gate of a memory cell in the memory unit 9 for performing writing is provided.

Furthermore, the non-volatile semiconductor memory device, applied a voltage control unit 11 for applying an arbitrary voltage to the control gate when detecting the deterioration state, an arbitrary voltage to the control gate by the voltage control unit 11 By doing so, the value read from the memory unit 9 is compared with the value held by the write data holding circuit 13, and when the data is different, an alarm signal S1 is output.
4 and a write data holding circuit 13 for holding a value written in the memory unit 9.

Next, the operation of this embodiment will be described. First, at the time of writing, a write signal (write)
Is input to the timing control unit 1, and the write address data (address) is further stored in the address latch unit 3.
(Address port). Further, the write data (data) is stored in the input / output buffer data latch circuit 5.
(Input / output port). At this time, the latch signal from the timing control unit 1 is output to the address latch unit 3 and the input / output buffer data latch circuit 5, and the write address (address) is stored in the address latch unit 3.
And the write data is held by the input / output buffer data latch circuit 5.

The input / output buffer data latch circuit 5
Is output to the write circuit 7, and outputs data corresponding to the write data to the multiplexer 8. Further, the write address data held by the address latch unit 3 is output to the Y decoder 2 and the X decoder 4, and the write address (addres
The word line s) is selected, and the multiplexer 8 sets the write data input from the write circuit 7 at the position selected by the Y decoder 2. A control signal is output from the timing control unit 1 to the high voltage control unit 10,
The high voltage control unit 10 applies a high voltage to the control gate of the memory cell in the memory unit 9 to which the writing is performed, and the writing is performed.

[0031] Next, at the time of reading, the read signal (re
ad) is input to the timing controller 1, and read address data is input to the address port. Read address data is held in the address latch unit 3,
The read address data held here is selected through the Y decoder 2, the X decoder 4, and the multiplexer 8 to select a word line and a bit line. A control signal is output from the timing control unit 1 to the voltage control unit 11. The voltage output from the voltage control unit 11 is applied to a control gate of a memory cell of the memory unit 9 that performs reading. Read data (signal) based on the designated read address data is amplified by the sense amplifier 6 and sent to the input / output port through the input / output buffer data latch circuit 5.

[0032] Next, the operation of the main part corresponding to the present invention. Hereinafter, FIG. 3 (the state of the memory cell at the time of erasing / writing) and FIG.
Description will be made with reference again to FIG. 5 (characteristics when writing is repeated) and FIG. 5 (threshold voltage distribution when erasing / writing is performed). FIG. 2 is a diagram for explaining a control gate voltage applied when deterioration is detected.

The memory section 9 cannot read the value stored in the memory cell due to its life even if a predetermined voltage is applied to the control gate to perform reading. For example, as shown in FIG. 5, when erasing is performed, if the threshold voltage of the memory cell is lower than the control gate voltage at the time of reading, a current flows between the source and the drain. Therefore, the data of the logical value “1” is stored, and the memory cell has reached the end of its life. Then, when rewriting is repeated, the threshold value of the memory cell changes as shown in FIG. Using this change characteristic, it can be determined that the memory cell will reach the end of its life.

[0034] For example, to read by applying a voltage higher than the control gate voltage applied during normal read to the memory cell subjected to erase. That is, reading is performed by applying the control gate voltage V1 at the time of deterioration detection shown in FIG. 5 to the control gate. If normal reading cannot be performed by this reading, it is determined that the memory cell will soon reach the end of its life. At this point, the lost value can still be read out normally by applying the control gate voltage during normal reading. That is, the memory unit 9
Will not be lost.

[0035] illustrating a determination that the memory cell reaches the lifetime (detection of deterioration) in detail. First, the memory unit 9
When an erasing / writing request is made to any of the addresses, the write data holding circuit 13 fetches and holds input data to be stored in the memory cell from outside. Next, immediately after erasing / writing to an arbitrary address, reading is performed by applying the control gate voltage V1 for deterioration detection from the voltage control unit 11. The read value and the write value held by the write data holding circuit 13 are compared by the data comparison circuit 12. If the read value differs from the write value in this comparison, an alarm signal S14 is output to the outside. The alarm signal S14 allows, for example, a CPU (not shown) to recognize that the memory section 9 is about to reach the end of its life.

[0036] For the case of this reading, similarly for the value at the time of writing to the contrary, it is possible to detect the deterioration. In this case, by applying a voltage V2 lower than the control gate voltage applied during normal reading and performing the reading, reading can be performed under stricter conditions than during normal reading. The procedure of the deterioration detection is the same as the procedure of strictly reading the condition for the erased value, except that the control gate voltage value at the time of the deterioration detection is different.

The deterioration detection in the reading, or the use of either of the deterioration detection in writing, erasing failure of the memory unit 9, both the writing failure is determined in advance determine occur first. In addition, both deterioration detections are performed, and the deterioration detection in the previously detected reading or the deterioration detection in the writing is performed.
The deterioration detection may be determined.

[0038] Thus, the value of the memory in the memory unit 9 is to allow determination of whether that successfully stored. Further, the deterioration state of the memory cell (memory section 9) that has been erased / written can be accurately determined. In this case, the stored data needs to be read only once.

In such a deterioration detection process, an extra read (or write) operation for confirming the stored value is required. The operation in this case does not cause the deterioration of the memory cell to progress. When erasing / writing is performed on a memory cell, holes / charges are injected into a floating gate by applying a high voltage to a control gate or a drain.

FIG . 2 is an equivalent circuit showing the state of the memory cell when erasing / writing is performed. At the time of erasing / writing, charges move between the floating gate F and the drain D. Repeatedly rewriting,
Although the number of traps in the tunnel oxide film increases and the memory cell deteriorates, the charge does not move at the time of reading. Therefore, the deterioration of the memory cell due to the increase in the number of readings is extremely small as compared with the erasing / writing. No consideration is necessary.

Next, another embodiment will be described. In this embodiment, in the above-described Japanese Patent Application Laid-Open No. 7-45084 (when a rewrite request for this address is issued when the number of rewrites reaches a predetermined count value, rewriting to a spare address is performed). To increase the life of the memory). That is, there is a concern that the memory cell may be degraded due to unnecessary reading that rewriting to a specific address frequently occurs with respect to rewriting to another address, and it is necessary to perform reading. To save a certain amount of time, a separate counter is provided, and rewriting is counted by this counter. The deterioration state is detected only when the count value is equal to or more than a predetermined number. Also, rewriting
Every time the number of times exceeds a predetermined number.

In this case, in the configuration of FIG. 1, at the time when the alarm signal S14 is output from the data comparison circuit 12, the rewrite request for this address is switched to a spare address. This address switching is performed by detecting the actual state of deterioration by applying the control gate voltage at the time of deterioration detection as described above, without making a determination based on the number of rewrites. Therefore, it is possible to more accurately detect the actual deterioration state.

[0043]

As is apparent from the above description, according to the nonvolatile semiconductor memory device of the present invention, the value stored in the memory cell in the semiconductor memory element is held, and the held value and the value stored in the memory cell are stored. Is compared with a data comparison circuit, and when the comparison value is different, an alarm signal is output. At this time, a voltage different from the voltage level applied during the normal read operation is supplied to the word line connected to the control gate of the memory cell.

[0044] As a result, it is possible to accurately determine the deterioration condition of the non-volatile memory. That is, reading for deterioration detection is required only once. In addition, an alarm signal can be output when the memory cell is deteriorated, and a normal value in the memory cell can be maintained when the alarm signal is output, thereby enabling efficient use of the nonvolatile memory. Become.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a control gate voltage applied at the time of detecting deterioration in the embodiment.

FIG. 3 is an equivalent circuit diagram showing a state of a memory cell at the time of erasing / writing.

FIG. 4 is a characteristic diagram when erasing / writing is repeated for a memory cell.

FIG. 5 is a diagram for explaining a threshold voltage distribution when erasing / writing is performed.

[Description of Signs] 1 Timing control unit 2 Y decoder 3 Address latch unit 4 X decoder 5 I / O buffer data latch circuit 6 Sense amplification unit 7 Write circuit 8 Multiplexer 9 Memory unit 10 High voltage control unit 11 Voltage control unit 12 Data Comparison circuit 13 Write data holding circuit S14 Alarm signal

Claims (6)

[Claims] 1. A non-volatile semiconductor storage device comprising: an electrically rewritable semiconductor storage element; and a storage processing unit for selectively writing / reading the semiconductor storage element. A non-volatile memory, comprising: a write data holding circuit that holds a value stored in the semiconductor memory device; and a data comparison circuit that compares a value stored in the write data holding circuit with a value stored in the semiconductor storage element. Semiconductor memory device. 2. The comparison of the data comparison circuit, wherein an alarm signal is output when a value stored in the write data holding circuit is different from a value stored in the semiconductor storage element. Nonvolatile semiconductor memory device. 3. A voltage control unit for supplying a voltage different from a voltage level applied during a normal read operation to a word line connected to a control gate of the semiconductor memory element. The nonvolatile semiconductor memory device according to claim 1. 4. A counter for counting the number of rewrites for each data write address for the semiconductor memory element, and an alarm signal is issued when the number of rewrites in the counter reaches a predetermined count value. 2. The non-volatile semiconductor storage device according to claim 1, wherein the output is performed. 5. An alarm signal is output when the number of rewrites by the counter reaches a predetermined count value, and when a rewrite request is made to an address that outputs the alarm signal, a spare address is set. 5. The nonvolatile semiconductor memory device according to claim 4, wherein switching for rewriting is performed. 6. A timing control unit which receives a read signal, a write signal, and a precharge signal and controls data write / read timing, as a storage processing unit, a Y decoder for selecting a bit line, An address latch unit for holding an address signal, an X decoder for selecting a word line, an input / output buffer data latch circuit for buffering input / output of write / read data, and an amplifying read data signal A sense amplifier for outputting the data corresponding to the write data held by the input / output buffer data latch circuit; a multiplexer for setting the write data at a position selected by the Y decoder; In a semiconductor memory device that performs writing 2. The non-volatile semiconductor memory device according to claim 1, further comprising: a high voltage control unit for applying a high voltage to a control gate of the memory cell.