JPS63268200A - Nonvolatile memory - Google Patents

Abstract

PURPOSE:To detect abnormality of a threshold voltage by providing a means to supply a first gate voltage internally generated to obtain corresponding read data, and a means to obtain a read data corresponding to a second gate voltage supplied externally. CONSTITUTION:After the end of writing, if a reading is normally executed by means of a specific voltage VS generated by a gate voltage setting part 103, the low threshold voltage VTW of a storing use TR 109 is lower than the VS. Then, a voltage in a value lower than the VS by a marginal value alpha is supplied to a terminal Vcg to execute reading. And, if the reading is normal, the VTW is understood to have a margin of the value alpha or more. Accordingly, by attaining a supply voltage whose output terminal OUT is in L-level, the value of the VTW can be measured. After the end of an erasing action, a reading action is executed by supplying a voltage higher than the terminal Vcg by a marginal value beta. If the erasing action is normal, a high threshold VTE is understood to have a margin of beta or more. This operation is repeated, and the value of the VTE can be measured by attaining a supply voltage whose output terminal OUT is in H-level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to non-volatile memories, and more particularly to test circuits for writable and erasable non-volatile memories.

[Conventional technology]

Conventionally, a programmable and erasable nonvolatile memory (hereinafter simply referred to as EPOM) has a function of erasing stored data, a function of writing data to be stored, and a function of reading stored data. ing. FIG. 2 shows this type of EPROM. Typically, an EPROM has several thousand addresses and a memory capacity ranging from tens of thousands to hundreds of thousands of bits, but for the sake of simplicity, here we will explain how one address is 1 bit, and the EPaOM is 280M (referred to as EBPROM) which can be erased from memory.

As shown in FIG. 2, a memory cell section 201. Gate voltage setting unit 202 during i-input and erasing. Gate voltage setting section 203 during reading. Data line voltage setting unit 204 during writing and erasing. Sense amplifier 205, output data ra, chi 2
Consists of 06. When erasing this EBPROM, GS
The signal becomes "H" level, and the selection transistors 207 and 208 in the memory cell section 201 are turned on.

Next, the 1cE signal becomes "H" level, the gate voltage setting section 202 outputs the vPP potential (usually 12V to 30V), and the data line voltage setting section 204 outputs the GND potential.These potentials are each floating. This applied voltage is applied to the gate type storage transistor 209, and a strong electric field is formed between the gate and source of the storage transistor 209.

Due to this strong electric field, electrons induced above the energy barrier between the silicon surface and the oxide film are injected into the floating gate through the tunnel oxide film. This electron injection continues while the E signal is at the 1H level, and when the E signal goes to the L level, the electrons are trapped by the floating gate and held, and the C8 signal goes to the L level to complete the erasing.

At this time, the threshold voltage of the memory transistor (hereinafter simply V
It is abbreviated as T. ) is higher due to the electrons being dragged to the 70-teating gate. (Hereafter, this VT
is called VTE. Usually, it is about +6v to +8v. ) Next, when writing to the EEPROM of 207., the C8 signal is at the "H" level, and the selection transistor 207.
208 is turned on. Next, the W signal becomes "H" level, the gate voltage setting section 202 outputs the GND potential, and the data line voltage setting section 204 outputs the VPP potential. These potentials are respectively applied to the storage transistor 209, and this applied voltage causes the storage transistor 2
A strong electric field is formed between the gate and source of 09. 1 (However, the direction is opposite to that during erasing.) Due to this strong electric field, some of the electrons trapped in the floating gate are induced to have an energy higher than the energy barrier between the floating gate and the oxide film. is rejected to the source through the tunnel oxide film. (Conversely, this can also be thought of as hole injection into the floating gate.) The hole injection continues while the W signal is at the V″H″ level, and the W signal goes to the “L” level.
When the C8 signal is set to the L level, it is trapped in the floating gate and held in the holding state (electrons are empty), and the write operation is completed by setting the C8 signal to the L level.

At this time, the V of the storage transistor is low due to the holes trapped in the floating gate. (Hereinafter, this VT will be referred to as VTW.) Usually -2V~
It is about -4v. ) Next, when reading this EEPROM storage data, C
8 signal becomes "H" level, selection transistor 2
07 and 208 are in the on state.

Next, the R signal becomes 1H'' level, and the gate voltage setting section 203 (resistor r, +P channel type transistor 21
0 on-resistance) and (resistance r2 + N-channel transistor 2110 on-resistance)
Outputs s. This specific voltage vs is set to a voltage between vTw and VTK of the storage transistor 209. (Usually OV to 5V) This specific voltage vs is applied to the gate of the memory transistor 209, but if the seven memory transistors 209 are higher than this specific voltage vs,
In the erased state, the storage transistor 209 does not turn on, so the data line is not connected to GND. Conversely, if the VT of the storage transistor 209 is lower than this specific voltage vs., the storage transistor 209 is turned on in the written state, so the data line is connected to GND. The ungrounded state or grounded state of the data line described above corresponds to two states in which current does not flow or flows through the resistor r3 depending on the ■DD voltage applied to the data line by the sense amplifier 205, and the difference between these states is are detected as the presence or absence of a voltage drop, and the stored data 11'' and V
Output as "0". This output data is latched by the latch circuit 206, and the reading is completed by setting the C8 signal to the "L" level.

In addition to the above-mentioned basic functions, there is a verify function that confirms whether or not writing or erasing has been reliably executed when writing or erasing is executed.

This is to read and confirm the data immediately after writing or erasing is completed, and the above-mentioned basic functions are executed continuously (writing operation + reading operation, or erasing operation + reading operation).

[Problem that the invention seeks to solve]

The conventional EFROM described above has a busy VTW + V when writing and erasing are executed in a certain writing time and erasing time.
It is not possible to confirm what value TK has reached. In other words, even if you use the verify function mentioned above, you can confirm that data has been written or erased, but
(2) It is only possible to confirm that the frost or VTE has become higher or lower than the above-mentioned specific voltage Vs, and it is not possible to know what the vTw and (2) TEO values are.

As mentioned above, since the memory capacity of an EFROM is usually tens of thousands to hundreds of thousands of bits, some bits may have an abnormal value of VTW*VTE due to manufacturing variations or defects. Among these abnormal bits, the bits where vTW > vsl and vTE > Vs can be detected by the verify function, but if VTW < VS and VTE > VS
IVTWVSI and 1vTr, Vs
Bits with insufficient l values have the disadvantage of being undetectable since the value of VTW + VTE is unknown. In addition, the difference between Vs and V Tws VIE described above, IVs −Vrt
vl and U IVTE-Vs l if:, there is a close relationship with the ability to retain illumination data or erased state,
Generally (Vs - Vrw) + (VTE - Vs)
It can be said that the retention capacity is high when the value is large, but v'rw t
Since the value of VTE is not known, it has the disadvantage that it is difficult to quantitatively understand the retention capacity.

The purpose of the present invention is to enable detection of the value of EPROMOVrw and VTE, to detect bits in which the value of VTW+VTB is abnormal, and to more reliably guarantee the ability to retain written data or erased state. That's true.

[Means for solving problems]

In the EFROM of the present invention, when reading written data, a first gate voltage generated inside the chip is applied to the gate of the transistor that stores and holds the written data. means for obtaining read data corresponding to the gate voltage of the chip; means for applying a second gate voltage supplied from outside the chip to obtain read data corresponding to the second gate voltage; and means for switching the two gate voltages.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a one-address, one-bit EEFROM according to an embodiment of the present invention. (The number of addresses and bits has been minimized to simplify the explanation, and it is of course possible to think of it in terms of multiple addresses and multiple bits.)
The EEFROM of this embodiment has a memory cell section 101. A gate voltage setting section 102 for writing and erasing, a gate voltage setting section 103 for reading. Data line voltage setting unit 104 during writing and erasing. Sense amplifier 105. The output data latch 106 is further provided with a terminal vcg for supplying a second gate voltage from the outside.

Basic functions of the EEFROM of this embodiment: Erase function of permanently stored data 1. The function of writing data to be stored and the function of reading stored data operate in exactly the same manner as in the conventional example described above.

However, when reading data, by setting the T signal to the "H" level, the storage transistor uses the voltage supplied to the 70g terminal from the outside instead of the specific voltage s generated by the internal gate voltage setting section 103. It is possible to apply it to 109 cases. Therefore, vTt- of the storage transistor 109 can be detected by repeatedly performing read operations while changing the voltage value supplied to the 70g terminal.

For example, when checking whether writing can be performed normally, a normal read operation is performed immediately after the write operation. (This is the above-mentioned verify operation, and is readout using the specific voltage ■s generated by the gate voltage setting unit 103.) vf of the storage transistor 109
If f is less than the specific voltage s, the storage transistor is turned on, the sense amplifier 105 detects the stain current path, and the output of the output terminal OUT becomes the %S l-i" level. It can be seen that it is in a writing state.

Next, a value lower than the above-mentioned specific voltage Vs by the required margin value α, slender vs-α, is supplied to the terminal Vcg,
A read operation is performed by setting the T signal to ``H'/level. If vTw is lower than ■s−α, the output terminal O
It can be confirmed that the output of the UT is now at the "H" level, that the write operation is performed normally, and that vTw has a margin greater than the α value. If necessary, a lower value can be applied to the terminal v
cg, repeats the read operation, and outputs the output terminal OU.
By determining the supply voltage at which the T output rises to the 1L level, a value of 77W can be measured.

Also, when confirming whether or not erasing can be performed normally, confirmation can be made in the same manner as when writing described above.

That is, after performing an erase operation, one normal read operation is performed to confirm that VTE is 76 or higher.

Next, the terminal vcg is supplied with a value vs+β which is higher than the required margin value β compared to (1)8, and the T signal is set to the "H" level to perform a read operation.

If the VTR has a higher value than v8+β, the output terminal OUT
The output is at the "L" level, confirming that the erase operation is performed normally and that VTE has a margin greater than the β value.Furthermore, ■ A value higher than 8+β is supplied to the terminal vcg. By repeating the read operation, the output of the output terminal OUT becomes 2.
The value of VTE can be measured by determining the supply voltage that reaches the "H" level.

〔Effect of the invention〕

As explained above, in the present invention, the gate voltage to be applied to the storage transistor 109 during reading can be externally supplied, and by adjusting the supply voltage, VTW t VT
E t-can be measured. This means that v'
rw l V TF! It has the effect of detecting abnormal lots or products, and when used, vTw
, detect the address (word) where VTE is abnormal,
It can be used to take measures such as prohibiting use.

Moreover, the value of v'rw t VTE is the above-mentioned α value, β
It can be confirmed that there is a margin of value, so the VT of the memory transistor can be adjusted to the α value or β value, and the aging time (
Destruction occurs when electrons or holes are lost. It can be calculated from experiments such as accelerated tests. ) has the effect of making it possible to guarantee retention. In addition, K is the write time if the value of v'rw t VTI is different from the value assumed at the time of design;
It is also possible to adjust the value of VTW*vTg by increasing or decreasing the erase time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. 101.201...""Memory cell part, 102°20
2... Gate voltage setting section (during writing and erasing),
103.203...Gate voltage setting unit (at the time of reading), 104,204...Data line voltage setting unit, 105.205...Sense amplifier, 106
, 206... Output data latch circuit, 107,
108°207.208...Selection transistor, 109°209...Floating gate storage transistor, 110,112,210...
...P-channel transistor, 111, 113,
211°°°°°. N-channel transistor. ``''';',?'・, Agent: Susumu Uchihara, Patent Attorney, 1cg

Claims (1)

[Claims] When reading the written data, a first gate voltage generated inside the chip is applied to the gate of the transistor that stores the written data, and corresponds to the first gate voltage. In a nonvolatile memory having means for obtaining read data, the written data is written by applying a second gate voltage different from the first gate voltage to the gate of the transistor that stores and holds the written data. What is claimed is: 1. A nonvolatile memory characterized in that it is provided with means for reading out data stored in the memory.