JP4172699B2 - Nonvolatile semiconductor memory - Google Patents

Description

[Industrial application fields]
The present invention relates to a nonvolatile semiconductor memory, and more particularly to a nonvolatile semiconductor memory that erases data in units of blocks.
[Prior art]
In recent years, a flash memory is often used as a semiconductor memory used for a memory card or a silicon disk. This flash memory is a kind of non-volatile memory, and is required to retain data regardless of whether power is turned on.
By the way, a NAND flash memory that is often used in the above-described device is a memory cell when a memory cell is changed from an erased state (logic value = 1) to a written state (logic value = 0). However, when the memory cell is changed from the written state (0) to the erased state (1), it cannot be performed in units of the memory cell, and a predetermined erase unit composed of a plurality of memory cells. You can only do this. Such a batch erase operation is generally called “block erase”.
Due to the characteristics as described above, in a device using a NAND flash memory, when data is written, a block erased area is searched and new data is written in the detected empty area.
Therefore, in a device using a NAND flash memory, it is required that the written data is retained for a long time even after the power is turned off, and the block erased area is retained in an erased state for a long time after the power is turned off. The
[Problems to be solved by the invention]
However, when reading or writing to a certain memory cell is performed, the state of another memory cell that shares the bit line with this memory cell may change. This phenomenon is called a disturb phenomenon, and it is known that the occurrence rate is increased by repeating the write / erase operations on the memory cells. When the state of the memory cell changes due to the disturb phenomenon, the data once written not only changes with time, but also disturbs the normal writing operation.
In addition to the disturb phenomenon, if the power supply is unexpectedly cut off during the block erase, the erase state of the memory cell to be erased may be incomplete. Even in such a case, a normal writing operation is hindered for the same reason as described above.
As a countermeasure against such a problem, Japanese Patent Laid-Open No. 2001-243122 diagnoses the state of an erased block before actually writing data.
However, this measure improves the reliability of writing. However, since the processing such as reading the data written in the memory cell of the erased block is performed before writing, there is a problem that the writing time may become long. there were.
Therefore, in the present invention, by providing a function for inspecting an erased block in the nonvolatile semiconductor memory, the reliability of data stored in the nonvolatile semiconductor memory can be improved while suppressing a decrease in write efficiency. It is an object to provide a conductive semiconductor memory.
[Means for Solving the Problems]
The nonvolatile semiconductor memory according to the present invention is
A plurality of memory cell groups in which a plurality of memory cells are connected in series;
A plurality of word lines connected to gates of one memory cell constituting the memory cell group;
A switch element connected to the memory cell group;
Detecting means for detecting that the memory cell group is in a non-conductive state;
By simultaneously turning on the switch elements and connecting the plurality of memory cell groups connected by the word line to the detection unit,
All the memory cells selected by the word line from the plurality of memory cell groups can be detected to be in the erased state or one or more in the written state.
Here, the nonvolatile semiconductor memory according to the present invention is a memory in which writing and reading are processed in units of pages, and erasing is processed in units of blocks composed of a plurality of pages. Further, the “simultaneously on state” means that there is a period in which the plurality of memory cell groups connected by the word line are all connected to the detecting means, that is, a period in which the switch elements are simultaneously turned on. If so, the start and end of the on (conduction) state need not be simultaneous. Further, “all memory cells selected by the word line from the plurality of memory cell groups are in an erased state” means that all the memory cell groups connected to the detecting means are in a non-conductive state. If one or more memory cell groups are turned on, they do not fall under the “all erased state”. In addition, “one or more is in a writing state” means that one or more memory cell groups are in a conductive state.
In addition, the nonvolatile semiconductor memory according to the present invention is
The switch element is configured to be turned on during the process of storing the data to be written to the memory cell group in the data holding means for holding the data to be written to the memory cell constituting the memory cell group.
DETAILED DESCRIPTION OF THE INVENTION
[Description of schematic configuration of NAND flash memory]
FIG. 1 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory (flash memory) according to the present invention. This NAND flash memory is composed of a memory cell array 7 that holds data in response to an external request and its peripheral circuits. The main peripheral circuits will be described sequentially.
The logic control circuit 1 takes in external control signals such as a chip enable signal CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE, a read enable signal RE, and a write protect signal WP inputted from the outside. An internal control signal corresponding to the operation mode is generated. Here, the internal control signal is used for controlling data latch and transfer of the input / output circuit 4 to be described later.
The control circuit 2 performs sequence control of data writing, reading and erasing based on signals and data of the logic control circuit 1 and the command register 3. It also controls a high voltage generation circuit (not shown) that generates a high voltage used for writing, reading and erasing data.
The input / output circuit 4 is connected to I / O0 to I / O7, and various data are inputted and outputted through this circuit. When a command for controlling the operation is input, the input command is decoded and held in the command register 3, and the control circuit 2 performs sequence control of data writing, reading and erasing based on this command as described above. Do. When an address is input, it is held in the address register 5. When data is input, data is transmitted / received to / from a data buffer 8 described later.
The row decoder 6 and the column decoder 9 select memory cells in the memory cell array based on the data in the address register 5 and the command register 3. Here, the row decoder 6 is involved in the selection of the word line WL of the memory cell array, and the level (voltage level) given to each word line WL depends on the write and read operation modes and the selection and non-selection selection states. Supplied as appropriate.
The data buffer 8 holds data to be written to the memory cell array 7 or data to be read from the memory cell array 7. Here, the data buffer 8 holds data for one page, which is a processing unit for writing and reading.
The data detection circuit 10 and the erroneous erasure detection circuit 11 are circuits added to realize the function according to the present invention. Here, the data detection circuit 10 is a circuit that reads data written in a memory cell that is a write destination of data to be written in the memory cell array 7. The erroneous erasure detection circuit 11 is a circuit that detects the presence or absence of a memory cell that is not in an erased state based on the data read by the data detection circuit 10. Details of the data detection circuit 10 and the erroneous erasure detection circuit 11 will be described later.
[Description of memory cell]
Next, a specific structure of the memory cell 16 constituting the memory cell array 7 shown in FIG. 1 will be described with reference to FIGS.
FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell 16 constituting the memory cell array 7. As shown in the figure, the memory cell 16 includes an N-type source diffusion region 18 and a drain diffusion region 19 formed in the P-type semiconductor substrate 17, and a P between the source diffusion region 18 and the drain diffusion region 19. Tunnel oxide film 20 formed to cover type semiconductor substrate 17, floating gate electrode 21 formed on tunnel oxide film 20, insulating film 22 formed on floating gate electrode 21, and insulating film 22 The control gate electrode 23 is formed on the top. A plurality of memory cells 16 having such a configuration are connected in series within the memory cell array 7.
The memory cell 16 has either an “erased state (a state where no electrons are accumulated)” or a “written state (a state where electrons are accumulated)” depending on whether electrons are injected into the floating gate electrode 21 or not. Is shown. Here, one memory cell 16 corresponds to 1-bit data, the “erased state” of the memory cell 16 corresponds to data of “1” of the logical value, and the “written state” of the memory cell 16 corresponds to the logical value. Corresponds to “0” data.
In the “erased state”, since electrons are not accumulated in the floating gate electrode 21, the P-type semiconductor between the source diffusion region 18 and the drain diffusion region 19 when the read voltage is not applied to the control gate electrode 23. A channel is not formed on the surface of the substrate 17, and the source diffusion region 18 and the drain diffusion region 19 are electrically insulated. On the other hand, when a read voltage is applied to the control gate electrode 23, a channel (not shown) is formed on the surface of the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19. And the drain diffusion region 19 are electrically connected by this channel.
That is, in the “erased state”, when no read voltage is applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 are electrically insulated, and the read voltage is applied to the control gate electrode 23. In this state, the source diffusion region 18 and the drain diffusion region 19 are electrically connected.
FIG. 3 is a cross-sectional view schematically showing the memory cell 16 in the “written state”. As shown in the figure, the “written state” refers to a state in which electrons are accumulated in the floating gate electrode 21. Since the floating gate electrode 21 is sandwiched between the tunnel oxide film 20 and the insulating film 22, the electrons once injected into the floating gate electrode 21 stay in the floating gate electrode 21 for a very long time. In this “write state”, since electrons are accumulated in the floating gate electrode 21, the source diffusion region 18, the drain diffusion region 19, and the like regardless of whether or not the read voltage is applied to the control gate electrode 23. A channel 24 is formed on the surface of the P-type semiconductor substrate 17 therebetween. Therefore, in the “write state”, the source diffusion region 18 and the drain diffusion region 19 are always electrically connected by the channel 24 regardless of whether or not the read voltage is applied to the control gate electrode 23. Become.
Whether the memory cell 16 is in an erased state or a written state can be read as follows. A plurality of memory cells 16 are connected in series in the memory cell array 7. A low level voltage is applied to the memory cell 16 selected in the series body, and a high level voltage is applied to the control gate electrode 23 of the other memory cells 16. In this state, it is detected whether or not the serial body of the memory cells 16 is in a conductive state. As a result, if this serial body is in a conductive state, it is determined that the selected memory cell 16 is in a written state, and if it is in an isolated state, it is determined that the selected flash memory cell 16 is in an erased state. The In this way, it is possible to read out whether the data held in any memory cell 16 included in the serial body is “0” or “1”.
When the memory cell 16 in the erased state is changed to the written state, a high voltage is applied so that the control gate electrode 23 is on the high potential side, and electrons are injected into the floating gate electrode 21 through the tunnel oxide film 20. To do. At this time, an FN (Fowler-Nordheim) tunnel current flows and electrons are injected into the floating gate electrode 21. On the other hand, when the flash memory cell 16 in the written state is changed to the erased state, a high voltage that causes the control gate electrode 23 to be on the low potential side is applied and accumulated in the floating gate electrode 21 via the tunnel oxide film 20. Discharge electrons.
[Description of function to check erased blocks]
FIG. 4 is a block diagram showing the connection part of the memory cell array 7 and its peripheral circuits according to the present invention. In FIG. 1, a data input / output unit 12 is a main part of the data buffer 8 and the column decoder 9 shown in FIG. 1, and a data detection unit 13 is a main part of the data detection circuit shown in FIG.
The data input / output unit 12 includes 512 latch circuits (latch 0 to latch 511) and transistors T 0 to T 511 connected between each latch circuit and the input / output circuit 4. Here, 512 latch circuits correspond to one line of I / O0 to I / O7 shown in FIG. Accordingly, 512 latch circuits each holding 512 bits of data are provided for each line, and 512 bytes of data are held as a whole. This 512-byte data corresponds to data for one page, which is a processing unit for writing and reading.
The data input / output unit 12 is a block related to reading from the memory cell array 7 or writing to the memory cell array 7. When data is read from the memory cell array 7, the data read from the memory cell array 7 is latched (latch 0). When the data is written in the memory cell array 7, the transfer data from the input / output circuit 4 is held in the latch circuit (latch 0 to latch 511).
When data held in the latch circuit (latch 0 to latch 511) is transmitted to the input / output circuit 4 (hereinafter referred to as a read sequence), the latch circuit (latch 0 to latch 511) and the input / output circuit 4 Transistors T0 to T511 connected therebetween are sequentially turned on (conductive state), and 512-bit data is transmitted to the input / output circuit 4 as a serial signal. When the serial signal from the input / output circuit 4 side is held in the latch circuit (latch 0 to latch 511) (hereinafter referred to as a write sequence), the transistor T0 is interlocked with the serial signal from the input / output circuit 4 side. ˜T511 are sequentially turned on (conductive state), and data is sequentially taken into the latch circuits (latch 0 to latch 511).
Transistors T 0 ′ to T 511 ′ constituting the data detection unit 13 are connected between a line connecting the latch circuit (latch 0 to latch 511) and the memory cell array 7 and the erroneous erasure detection circuit 11. Here, the transistors T0 ′ to T511 ′ are set to be turned on (conductive state) at the same time. A mirror circuit including transistors Tr1 and Tr2 and a constant current source 30 is connected to a line connecting the transistors T0 ′ to T511 ′ and the erasure detection circuit 11.
Next, referring to FIG. 5, a process for inspecting the erased state of a memory cell that is a data write destination will be described. Here, the memory cell to which data is written cannot be normally written unless it is in the erased state. Therefore, in the nonvolatile semiconductor memory according to the present invention, before data is written to the memory cell array 7, the memory cell of the memory cell array 7 to which the data is written (512-byte memory cell corresponding to the page to be written) is stored. It is checked whether all the states (written state or erased state) are erased.
FIG. 5 is a configuration diagram showing a connection example from the memory cells constituting the memory cell array 7 to the erroneous erasure detection circuit 11. In the figure, memory cells are connected in series between high potential side transistors Ta0 to Ta511 and low potential side transistors Tb0 to Tb511. The high potential side transistors Ta0 to Ta511 are connected to the erroneous erasure detection circuit 11 via the transistors T0 ′ to T511 ′. A mirror circuit including transistors Tr1 and Tr2 and a constant current source 30 is connected to a line connecting the transistors T0 ′ to T511 ′ and the erasure detection circuit 11.
The control gates of the memory cells connected in series are connected to the word lines WL0 to WLn.
Here, the normal read operation and write operation will be described before describing the processing for inspecting the erased state of the memory cell. For example, when data is read from the memory cells M0 to M511 whose control gates are connected to the word line WL3, a low level read voltage (hereinafter referred to as L voltage) is applied to the word line WL3, and the other words A high level read voltage (hereinafter referred to as H voltage) is applied to the line. Further, an H voltage is applied to the gates of the high potential side transistors Ta0 to Ta511 and the low potential side transistors Tb0 to Tb511.
At this time, since the H voltage is applied to the control gate of the memory cell connected to the word line other than the word line WL3, the drain and source of the memory cell regardless of the state of the memory cell (write state or erase state). There is conduction between them. On the other hand, since the L voltage is applied to the control gates of the memory cells M0 to M511 connected to the word line WL3, if the memory cells M0 to M511 are in the write state, the drain and the source are in a conductive state. If the cells M0 to M511 are in the erased state, the drain and the source are in a non-conductive state. Accordingly, when the memory cells M0 to M511 are in the write state, current flows from the high potential side transistors Ta0 to Ta511 to the low potential side transistors Tb0 to Tb511, but when the memory cells M0 to M511 are in the erased state, Current does not flow. Whether the data written in the memory cells M0 to M511 is the logical value “1” or “0” can be detected based on whether or not this current flows.
When data is written to the memory cells M0 to M511 whose control gates are connected to the word line WL3, a high potential write voltage (hereinafter referred to as a high potential voltage) is applied to the word line WL3, and the other word lines. A medium potential read voltage (hereinafter referred to as a medium potential voltage) is applied to. Further, a higher voltage is applied to the gates of the high-potential side transistors Ta0 to Ta511, and an L voltage is applied to the gates of the low-potential side transistors Tb0 to Tb511.
In this state, when the potential supplied from the side of the data buffer 8 (not shown in FIG. 5) shown in FIG. 1 is 0 V corresponding to the logical value “0”, the memory cells M0 to M511 have no control. A high voltage with a high potential on the gate side is applied, and the memory cells M0 to M511 are in a writing state corresponding to the logical value “0”.
Next, the case where the process of checking the erased state of the memory cell is performed during the write sequence (during the process of taking data to be written into the memory cell array 7 into the latch circuit (latch 0 to latch 511)) will be described.
In this case, the word lines WL0 to WLn, the high-potential side transistors Ta0 to Ta511, and the low-potential side transistors Tb0 to Tb511 are in the process of fetching data to be written into the memory cell array 7 into the latch circuit (latch 0 to latch 511). The same voltage as that in the read operation is applied to the gate. In other words, when the control gate of the memory cell to which the data taken in the latch circuit (latch 0 to latch 511) is written is connected to the word line WL3, the L voltage is applied to the word line WL3. The H voltage is applied to the other word lines. Further, an H voltage is applied to the gates of the high potential side transistors Ta0 to Ta511 and the low potential side transistors Tb0 to Tb511.
In this state, processing for fetching data to be written into the memory cell array 7 into the latch circuit (latch 0 to latch 511) is performed. On the other hand, an H voltage is applied to the gates of the transistors T0 ′ to T511 ′, and the transistors T0 to T511 are all turned on (conductive state). As a result, if at least one memory cell in the memory cells M0 to M511 is in a written state, a current flows through the transistor Tr1 constituting the mirror circuit, and if all of the memory cells M0 to M511 are in an erased state, the current is Not flowing.
Here, when no current flows in the drain terminal of the transistor Tr1 (connection portion between the transistors T0 ′ to T511 ′ and the erroneous erasure detection circuit 11) (when the memory cells M0 to M511 are all in the erased state). Becomes a high level (hereinafter, a state in which the potential is high is referred to as a high level), and a current flows through one or more memory cells (when one or more memory cells M0 to M511 are in a writing state). The current value of the constant current source 30 is set so that becomes a low level (hereinafter, a state where the potential is low is referred to as a low level). Therefore,
If any one of the memory cells M0 to M511 is in a written state, a low level is input to the erroneous erasure detection circuit 11.
FIG. 6 is a block diagram illustrating an example of the erroneous erasure detection circuit 11. In the erroneous erasure detection circuit 11, the output of the AND circuit 14 is connected to the input of the latch circuit 15. Further, the level (high level or low level) of the drain terminal of the transistor Tr1 is input to the AND circuit 14. 5 is provided for each line of I / O0 to I / O7 shown in FIG. 1, the level of the drain terminal of the transistor Tr1 in the eight blocks (high level). (Or low level) is input to the AND circuit 14.
Therefore, if any one of the memory cells M0 to M511 in each block is in a write state, the drain terminal of the transistor Tr1 is at a low level, and even in one block of each block, the transistor Tr1 has a low level. When the drain terminal becomes low level, the output of the AND circuit 14 becomes low level.
That is, if there is at least one memory cell in the write state among the write destination memory cells, the AND circuit 14 outputs a low level.
The latch circuit is a circuit provided to hold the output of the AND circuit 14. The latch circuit receives a latch signal when the output of the AND circuit 14 is stabilized after the H voltage is applied to the gates of the transistors T0 ′ to T511 ′, and the output level (high level) of the AND circuit 14 at that time is high. Level or low level) is maintained. In the above description, the process of checking the erased state of the memory cell is performed during the write sequence (during the process of fetching data to be written into the memory cell array 7 into the latch circuit (latch 0 to latch 511)). At other times, this erased state inspection process may be performed. Further, the number of memory cells selected by the word line and the number of I / O lines are not particularly limited, and the number of memory cells and the number of lines may be set as appropriate. Further, the method for detecting whether or not a current flows through the memory cells M0 to M511 when the transistors T0 ′ to T511 ′ are turned on (conductive state) may be other than the above mirror circuit.
【The invention's effect】
As described above, in the nonvolatile semiconductor memory according to the present invention, the erased state of the nonvolatile semiconductor memory can be inspected by a simple method. In addition, during the process of fetching data to be written into the nonvolatile semiconductor memory, if the erasure state of the data writing destination is inspected, the reliability of the data stored in the nonvolatile semiconductor memory is improved while suppressing a decrease in writing efficiency. Can be made.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a nonvolatile memory according to the present invention.
FIG. 2 is a cross-sectional view schematically showing a structure of a memory cell constituting a memory cell array.
FIG. 3 is a cross-sectional view schematically showing a memory cell in a write state.
FIG. 4 is a configuration diagram showing a connection part of the memory cell array 7 and its peripheral circuits according to the present invention.
FIG. 5 is a configuration diagram showing a connection example from a memory cell constituting the memory cell array 7 to an erroneous erasure detection circuit 11;
FIG. 6 is a block diagram illustrating an example of an erroneous erasure detection circuit 11;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Logic control circuit 2 Control circuit 3 Command register 5 Address register 6 Row decoder 7 Memory cell array 8 Data buffer 9 Column decoder 10 Data detection circuit 11 Error erasure detection circuit 12 Data input / output part 13 Data detection part 14 AND circuit 15 Latch circuit 16 Memory cell 17 P-type semiconductor substrate 18 Source diffusion region 19 Drain diffusion region 20 Tunnel oxide film 21 Floating gate electrode 22 Insulating film 23 Control gate electrode 24 Channel 30 Constant current source

Claims (1)

A plurality of memory cell groups in which a plurality of memory cells are connected in series;
A plurality of word lines connected to gates of one memory cell constituting the memory cell group;
Data holding means for holding data to be written to the memory cell group in units of pages;
An input / output circuit for serially inputting / outputting data to be written to the memory cell group;
An erroneous erasure detection circuit for detecting that all memory cells in a page to which data to be written to the memory cell group is written are in an erase state;
A plurality of first switch elements having one end connected to each of the memory cell groups and the other end connected to the erroneous erasure detection circuit ;
A plurality of second switch elements having one end connected to the data holding means and the other end connected to the input / output circuit ;
The plurality of the first switch elements are simultaneously turned on during the process of serially storing the data to be written in the memory cell group in units of pages in the data holding unit via the input / output circuit, whereby the plurality of memories Cells are connected in parallel,
When all of the plurality of memory cell groups connected in parallel are in an erased state, a signal indicating an erased state is input to the erroneous erase detection circuit,
When any one or more of the plurality of memory cell groups connected in parallel is in a written state, a signal indicating that it is in a written state is input to the erroneous erasure detection circuit. A non-volatile semiconductor memory.

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