KR100600951B1 - Flash memory device and post-program method thereof - Google Patents

Abstract

The present invention provides a flash memory device capable of shortening the post program time of a flash memory device and minimizing the size of a charge pump, and a post program method thereof. To this end, the present invention provides a plurality of word lines and a plurality of bits. At least one word line of the plurality of word lines according to a memory cell array including a plurality of memory cells formed at a portion orthogonal to a line, and an X-address input and enabled by a post program enable signal during a post program operation At least one of the plurality of bit lines according to a word line decoder for providing first data to the selected word line and Y-address input and enabled by the post program enable signal during the post program operation; Select one bit line A bit line decoder configured to provide second data to the selected bit line, and read third data of the corresponding memory cell through the selected bit line during a post program verify operation, and to the bit line decoder during the post program operation. The first amplifier and the second control signal are output by comparing the sense amplifier providing the second data with the third data and the reference data to determine whether an under erase cell exists in the selected bit line where the third data is detected. And a Y-address for storing the Y-address having an under erased cell in the selection bit line according to the first control signal, and then transmitting the Y-address to the bit line decoder according to a post program enable signal. After converting the address register and the fourth data input according to the second control signal into the second data, A flash memory device includes a post program data register configured to transmit the second data to the sense amplifier according to a pre-program enable signal.

Flash memory devices, NOR, erase, post program

Description

Flash memory device and its post program method {FLASH MEMORY DEVICE AND POST-PROGRAM METHOD THEREOF}

1 is an equivalent circuit diagram showing a memory cell array of a typical NOR flash memory device.

FIG. 2 is a cross-sectional view of a unit memory cell shown in FIG. 1; FIG.

3 is a distribution diagram of threshold voltages after program and erase operations of the memory cell illustrated in FIG. 2;

4 is a flowchart illustrating a method of erasing a flash memory device according to the prior art.

5 is a block diagram for performing a post program operation of a flash memory device according to the prior art.

6 is a block diagram illustrating a flash memory device according to a preferred embodiment of the present invention.

7 is a flowchart illustrating a post program operation using the flash memory device illustrated in FIG. 6.

<Explanation of symbols for the main parts of the drawings>

MC: Memory Cell W / L: Word Line

B / L: Bitline CSL: Common Source Line

X-add: X-address Y-add: Y-address

PostEN: Post Program Enable Signal

Pdata: Post Program Data

SAdata: Sense amplifier data WEN: Write enable signal

10 substrate 11 tunnel oxide film

12: floating gate 13: dielectric film

14: control gate 15: source region

16: drain region 51, 61: word line decoder (X-decoder)

52, 62: memory cell array 53, 63: bit line decoder (Y-decoder)

54, 64: Sense amplifier 65: Y-address register

66: post program data register

The present invention relates to a flash memory device and a post program method thereof, and more particularly, to a NOR type flash memory device and a post program method thereof.

Semiconductor memory devices, such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) devices, are volatile and fast data input / output that loses data over time. Input is largely classified into non-volatile (Read Only Memory) products that maintain their state and are slow in input / output of data. ROM products can be classified into ROM, PROM (Programmable ROM), EPROM (Erasable PROM) and EEPROM (Electrically EPROM). Among these ROM products, data can be programmed and erased by electric method. The demand for EEPROM is on the rise.

In general, an EEPROM or a flash EEPROM having a batch erase function has a stack type gate structure in which a floating gate and a control gate are stacked. Flash memory cells are widely used in portable electronics such as notebooks, PDAs, cellular phones, computer BIOS, and printers. From a circuit point of view, a flash memory cell is a unit string in which n cell transistors are connected in series to form a unit string, and these unit strings are paralleled between a bit line and a ground line. The NAND type and the cell transistors are connected in parallel between the bit line and the ground line, which are advantageous for high integration.

Hereinafter, a basic Noah-type flash memory device and its operation characteristics will be described with reference to FIGS. 1 and 2. FIG. 1 is an equivalent circuit diagram illustrating a cell array structure of a NOR flash memory device, and FIG. 2 is a vertical cross-sectional view of the unit cell illustrated in FIG. 1.

As shown in FIG. 1, a plurality of memory cells MC are connected between a plurality of word lines W / L and a plurality of bit lines B / L configured to be orthogonal to each other, and each memory cell MC is connected to each other. The source region of is connected to a common source line (CSL).

As shown in FIG. 2, the memory cell MC includes a floating gate 12 in which data is stored, a tunnel oxide 11 formed between the floating gate 12 and the substrate 10, and a word line. A control gate 14 serving as (W / L) and a dielectric film 13 formed between them 14 and 12 to separate the control gate 14 and the floating gate 12. In addition, the semiconductor device may include source and drain regions 15 and 16 formed in the substrate 10 exposed to both sides of the stacked gate of the floating gate 12 and the control gate 14. Here, the drain region 16 is connected to the bit line B / L, and the source region 15 is connected to the common source line CLS.

The operation of the quinoa flash memory cell is performed by using a channel hot electron (CHE) injection method and a source region or a bulk (substrate) using a Fowler-Nordheim tunneling method. To perform the erase operation.

First, as shown in FIG. 3, a program operation for programming a cell is an operation of increasing the threshold voltage (Vth) of the cell MC by about 2 to 7V by injecting electrons into the floating gate 12. to be. That is, 5 to 7 V is applied to the selection bit line B / L, and 9 to 12 V are applied to the selection word line W / L used as the control gate 14, and the common source line CSL and the substrate 10 are applied. When 0 V is applied to a portion, some of the channel hot electrons are injected into the floating gate 12 through the tunnel oxide film 11 by the gate electric field.

In addition, the erasing operation for erasing the programmed cell is to lower the threshold voltage of the cell MC to about 2V as an initial value by emitting electrons injected into the floating gate 12. That is, the select bit line W / L is floated, 12 to 15 V is applied to the common source line CSL, -8 V is applied to the word line W / L used as the control gate 14, When 8V is applied to the substrate 10, FN tunneling through the tunnel oxide film 11 occurs due to the voltage difference between the floating gate 12 and the source region 15, so that electrons injected into the floating gate 12 are source region. It is made by discharge to (15). Such an erase operation adopts a batch block erase method in which hundreds to thousands of bits including a plurality of word lines (W / L) and bit lines (B / L) are advanced in one block.

On the other hand, a read operation for detecting whether a cell is in a program or erase state is applied by applying a voltage of about 1V to the selection bit line B / L, and applying 4 to 5V to the word line W / L. This is accomplished by sensing the current flowing between the source and drain regions 15 and 16 of the erased cell (hereinafter referred to as the erase cell) or the programmed cell (hereinafter referred to as the program cell).

One of the problems occurring in the quinoa flash memory cell is disturbance caused by over erase. Under-erasing means that the threshold voltage of a normal erase cell is 2V, whereas the tunneling electric field is changed due to a process defect of a unit cell, degradation of a tunnel oxide film, and the erase threshold voltage of a specific cell is lowered to 0V or less. Say.

In general, during the program operation, the selection cell should be programmed by generating current through only the selection cell connected to the selection bit line to which the program voltage of 6V is applied and the selection word line to which 12V is applied. However, when there is an over erased cell (hereinafter referred to as an under erase cell) in an unselected word line to which 0 V is applied, the bit line voltage is discharged through the unselected cell due to a threshold voltage of 0 V or less. This reduces the amount of current through the selection cell. As a result, generation of hot electrons required for the program is suppressed, thereby causing a problem in that the selection cell cannot be programmed. In addition, even during a read operation, a problem arises in that the current flow through the under erase cell misreads the select cell to the erased state even when the select cell is in the program state due to an abnormal current path through the unselected under erase cell.

In order to prevent the cell from being over-erased as described above, in the flash device according to the related art, a pre-program is performed to match the threshold voltage of the initial cell to some extent, and the under-erased cell is removed even after erasing is completed. In order to eliminate the underestimation cell, a soft program process, post-program, is performed. That is, as shown in FIG. 4, the pre-program and pre-program verify steps S41 to S43 continue until the program state is verified, and the post program and post program verify step performed until all the erase cells are removed ( S47 to S49) is additionally performed.

The dual post program operation is to increase the threshold voltage of the over erased cell to 0V or more, and 5V is applied to the drain region, and 0V is applied to the word line (W / L) and the source region. In this way, electrons introduced from the source region by the horizontal electric field generate drain avalanch hot carriers in the drain region, and some electrons are injected into the floating gate of the cell to recover the under erased cell.

5 is a block diagram for performing a post program operation of a flash memory device according to the prior art.

As shown in FIG. 5, a circuit for performing a post program operation includes a plurality of word lines W / L <1> to W / L <n> and a plurality of bit lines B / L <1> to B Memory cell array 52 formed of a plurality of memory cells formed at points perpendicular to each other / L <m>, a word line decoder (X-decoder) 51 and a bit for selecting any one of the memory cells. A bit decoder (Y-decoder) 53 and a sense amplifier 54 for sensing data from selected cells of the memory cell array 52 are provided.

Referring to FIG. 4, the operation characteristics are described. After the erase and erase verification steps S44 to S46 are collectively performed on all the cells of the memory cell array 52, the post program operation S47 is performed. The post program operation S47 is started by the post program operation enable signal PostEN. When the enable signal PostEN is enabled, the word line decoder 51 performs 0 V on all word lines of the cell array 52. Apply. In this case, the bit line decoder 53 selects a corresponding bit line among the plurality of bit lines B / L <1> to B / L <m> according to the input Y-address Y-add, and selects the selected bit. Send post program data (Pdata) on a line. Here, the post program data Pdata is a logic value having a low level '0' or a high level '1'. For example, the post program data Pdata has a low level logic value when applying 5 V to the selected bit line, and has a high level logic value when applying 0V. This operation is performed from the beginning to the end of the Y-add so that the post program operation can be performed on all bit lines of the cell array 52. Thereafter, the post program verification steps S48 and S49 are performed, and if the verify operation is a fail, the post program verification step S47 is repeatedly performed.

However, in the post program operation of the flash memory device according to the related art, at least 8 or 16 bit lines are selected for each Y-add, instead of performing the post program operation only for the corresponding bit line. Will be performed simultaneously. Therefore, when the post program is to be performed for the entire memory cell array, the post program operation time becomes long. In addition, if the number of bit lines selected by the Y-add is large, a voltage (that is, 5V) is supplied to the drain regions of a large number of memory cells during the post program operation. Overload is applied, limiting efficiency due to drive current limitations. On the other hand, when the size of the charge pump is increased in order to increase the driving current of the charge pump, it causes a chip area to increase.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and provides a flash memory device and a post program method thereof capable of shortening the post program time of the flash memory device and minimizing the size of the charge pump. The purpose is.

According to an aspect of the present invention, there is provided a memory cell array including a plurality of memory cells formed at orthogonal portions of a plurality of word lines and a plurality of bit lines, and a post program enable signal during a post program operation. A word line decoder for selecting at least one word line among the plurality of word lines and providing first data to the selected word line according to an X-address enabled and input by the X-address; A bit line decoder for selecting at least one bit line among the plurality of bit lines and providing second data to the selected bit line according to a Y-address enabled and input by a program enable signal; The memory cell through the selected bit line during the verify operation. A sense amplifier configured to read third data and provide the second data to the bit line decoder during the post program operation; and compare the third data with reference data to the selected bit line where the third data is detected. Determining whether there is an under erase cell and outputting first and second control signals, and storing a Y-address in which the under erase cell exists in the selection bit line according to the first control signal, and then enabling the post program. A Y-address register for transmitting the Y-address to the bit line decoder according to a signal, and fourth data input according to the second control signal after being converted into the second data and stored therein, and then the post program enable signal. And a post program data register for transmitting the second data to the sense amplifier. Provide letters.

In addition, according to another aspect of the present invention, there is provided a post program method of the flash memory device, comprising: connecting the selected bit line selected through the bit line decoder corresponding to the Y-address; Reading the third data from the memory cell through the sense amplifier; comparing the third data read by the sense amplifier with the reference data through the comparator; Verifying whether the selection bit line includes an over erase cell in the selection bit line, and storing the Y address through the Y-address register according to the first control signal, and storing the second control signal. Storing the second voltage having a level corresponding to the post program data register. If there is no under-cell in the selection bit line, the Y-address is increased by one through the Y-address register to store the next Y-address, and the level corresponding to the input fourth data is stored. Storing the second data having the second data in the post program data register, and transmitting the Y-address stored in the Y-address register to the bit line decoder according to the post program enable signal. And performing a post program operation by transmitting the second data stored in the post program data register through the sense amplifier to a bit line selected by the Y-address.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Example

6 is a block diagram illustrating a flash memory device according to a preferred embodiment of the present invention. For convenience of description, a block diagram of a quinoa flash memory device configured to select 16 bit lines for each Y-address is shown.

As shown in FIG. 6, a flash memory device according to an exemplary embodiment of the present invention may include a memory cell array 62, a word line decoder 61, a bit line decoder 63, a sense amplifier 64, and a Y-address register. 65, a post program data register 66, and a comparison unit 67 are included.

The memory cell array 62 is a portion where the plurality of word lines W / L <1> to W / L <n> and the plurality of bit lines B / L <1> to B / L <m> are orthogonal to each other. It is composed of a plurality of memory cells formed in each. These memory cells are selected by corresponding word lines and bit lines, respectively.

The word line decoder 61 is enabled by the post program enable signal PostEN, so that the word line decoder 61 of the plurality of word lines W / L <1> to W / L <n> may be configured according to the X-address X-add. At least one word line is selected. In this case, the number of word lines to be selected may be appropriately adjusted according to the size of the memory cell array, and 0V is applied to the selected word lines.

The bit line decoder 63 is enabled by the post program enable signal PostEN together with the word line decoder 61 and is provided in accordance with a plurality of Y-addresses (Y-add) provided from the Y-address register 65. At least one of the bit lines B / L <1> to B / L <m> is selected. At this time, the number of bit lines to be selected can be appropriately adjusted according to the size of the memory cell array, for example, eight or sixteen are selected for one Y-address.

The sense amplifier 64 has a number corresponding to the number of bit lines B / L <1> to B / L <m>. In the verify operation, each data SAdata is detected from memory cells connected to corresponding bit lines selected according to one Y-add. In the post program operation, the post program data Pdatao provided from the post program data register 66 is provided to the corresponding memory cell through the corresponding bit line selected by the bit line decoder 63. For example, when 16 bit lines B / L <1> to B / L <16> are selected for one Y-address during the verify operation, the sense amplifier may select each bit line B / L <. 1> to B / L <16>) to detect and output data SAdata. In addition, during the post program operation, each of the sixteen post program data Pdata1 input is provided to the corresponding memory cell through the corresponding bit lines B / L <1> to B / L <16>. In this case, when the post program data Pdatao is low level, a 5 V post program voltage is provided to the corresponding memory cell through the corresponding bit line, and when the post program data Pdatao is low level, a 0 V post program voltage is transmitted to the corresponding memory cell through the corresponding bit line. Is provided. When the post program voltage of OV is applied, no post program is performed for the cell.

The Y-address register 65 stores a plurality of Y-adds (Y-adds) input through an external bus according to a write enable signal (WEN) input from the comparator 67. After that, the stored Y-address Y-add is output to the bit line decoder 63 according to the post program enable signal PostEN. For example, the bit lines B / L <1> to B / L <m> corresponding to the Y-add [0] by the verification operation for the Y-address [Y-add [0]). The Y-address Y-add [0] is stored by the write enable signal WEN input from the comparator 67 when an over erase occurs in the memory cell connected to at least one of the bit lines. Then, the Y-address Y-add [0], which is enabled and stored by the post program enable signal PostEN, is output to the bit line decoder 63.

The post program data register 66 suitably sets the state of the post program data Pdata input via the external bus according to the 16 post program data state conversion control signals Postdata input from the comparator 67 through the internal bus. After conversion and storage, the 16 data Pdatao enabled and stored by the post program enable signal PostEN are output to the sense amplifier 64. In this case, the control signal Postdata functions as a signal for selecting a bit line. For example, only among memory cells connected to the bit lines B / L <1> among the bit lines B / L <1> to B / L <16> selected by the Y-address [Y-add [0]). When over-erasing occurs, the post program data Pdatao2 to Pdatao16 corresponding to the other control signals Postdata2 to Postdata16 except for the first control signal Postdata1 among the 16 control signals Postdata are stored at a high level and the first control signal is stored. The post program data Pdatao1 corresponding to (Postdata1) is stored at a low level. Then, the post program data Pdatao1 to Pdatao16 enabled and stored by the post program enable signal PostEN are output to the sense amplifier 64.

The comparator 67 receives the data SAdata1 to SAdata16 input from the sense amplifier 64, and compares each data with the reference data REdata to determine an underestimated cell. For example, when the data SAdata1 is compared with the reference data REdata and the data is over-erased, the write enable signal WEN is enabled and output to the Y-address register 65, and only the control signal Postdata1 is low level. The data is output to the post program data register 66 with a logical value of. Meanwhile, the comparison unit 67 compares the output data SAdata with the reference data REdata and determines whether the state of the data SAdata is '0' or '1'.

Hereinafter, a post program operation characteristic of a flash memory device according to an exemplary embodiment of the present invention illustrated in FIG. 6 will be described in detail with reference to FIG. 7.

First, as shown in FIG. 7, the preprogramming and verifying steps S71 to S73 and the erase and erase verifying steps S74 to S76 of the flash memory device according to the preferred embodiment of the present invention are performed in a general manner. Accordingly, description thereof will be omitted.

After the erase verification steps S75 and S76 are completed, a verification operation for determining whether there is an under erase cell among the bit lines selected for the first Y-address Y-add [0] from the external bus is performed (S77 to S79). ). Here, the verification for the Y-address Y-add [0] is performed in the following manner. First, when the Y-address Y-add [0] is input to the bit line decoder 63 through the Y-address register 65, the bit line decoder 63 is Y-add [0]. ), 16 bit lines B / L <1> to B / L <16> are selected from among the plurality of bit lines B / L <1> to B / L <m>. The sense amplifier 64 reads and outputs data SAdata1 to SAdata16 of the corresponding memory cell through the bit lines B / L <1> to B / L <16> thus selected. The comparison unit 67 compares the read data SAdata1 to SAdata16 with the reference data REdata to determine whether there are any erase cells in the corresponding bit lines B / L <1> to B / L <16>. It is a process of determining.

In the determination process, the bit lines B / L <1> to B selected in the Y-address [Y-add [0] during the verification steps S77 to S79 for the first Y-address [Y-add [0]). If there is an underserized cell on at least one bit line, the post program for the corresponding bitline in which the underestimated cell exists is performed (S82). Here, the post program operation is performed in the following manner. First, when it is determined through the comparator 67 that there is an under erase cell only in the bit line B / L <1>, the comparator 67 enables the write enable signal WEN to enable the Y-address register. 65, only the first control signal Postdata1 corresponding to the bit line B / L <1> among the control signals Postdata1 to Postdata16 is outputted to the post program data register 66 at a low level. The Y-address register 65 stores the Y-address Y-add [0] by the write enable signal WEN. In addition, the post program data register 66 converts and stores the state of the post program data Pdata according to the control signal Postdata. In this state, when the post program enable signal PostEN is enabled, the Y-address register 65 outputs the stored Y-address Y-add [0] to the bit line decoder 63, and the post program. The data register 66 outputs the stored post program data Pdata1 to Pdata16 to the sense amplifier 64. At this time, the post program data Pdatao1 has a low level logic value, and the remaining data Pdatao2 to Pdatao16 have a high level logic value. Thereafter, the bit line decoder 63 selects the bit lines B / L <1> to B / L <16> by the Y-address [Y-add [0]). The sense amplifier 64 provides the post program data Pdatao1 to Pdatao16 through the bit lines B / L <1> to B / L <16> selected by the bitline decoder 63. As a result, 5V is applied to the bit lines B / L <1> to perform a post program operation. In addition, 0V is applied to the bit lines B / L <2> to B / L <16 and the post is operated. Program operation does not work.

Meanwhile, the bit lines B / L <1> to B / L selected for the Y-address Y-add [0] during the verification steps S77 to S79 for the first Y-address [Y-add [0]). If there is no excessive cell in < 16 >), it is determined whether the Y-address is the final address (S80). As a result of determination, if the input Y-address is not the final address, the Y-address value is increased by one (S81).

Then, verification is performed for the increased Y-address (S78, S79). During the verification steps (S78, S79), if there is an under erase cell in the corresponding Y-address, the post program step (S82) is performed, and if there is no under erase cell, steps S80 and S81 are sequentially performed. This iterative process is repeatedly performed by the Y-address to the final address.

On the other hand, during the verification steps (S78, S79), if the verification for the corresponding Y-address is repeatedly made beyond the set number of times, fail the chip or terminate the post program operation.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a corresponding Y-address in which an under erase cell is present after a post verification operation is first performed during a post program operation to prevent an over erasure occurring during an erase operation of a flash memory device is performed. By storing the bit line and performing the post program operation on only the corresponding bit line in which the under erase cell exists, the post program time of the flash memory device can be shortened and the size of the charge pump can be minimized.

Claims (22)

A memory cell array including a plurality of memory cells formed at a portion where a plurality of word lines and a plurality of bit lines are orthogonal to each other; A word line that selects at least one word line from among the plurality of word lines according to an X-address enabled by a post program enable signal and is input by a post program enable signal during a post program operation, and provides first data to the selected word line. Decoder; Selecting at least one bit line from among the plurality of bit lines according to a Y-address enabled and input by the post program enable signal during the post program operation, and providing second data to the selected bit line Bitline decoder; A sense amplifier configured to read third data of a corresponding memory cell through the selected bit line during a post program verify operation, and provide the second data to the bit line decoder during the post program operation; A comparator for comparing the third data with reference data to determine whether an under erase cell exists in the selected bit line in which the third data is detected, and outputting first and second control signals; A Y-address register for storing a Y-address in which an under erase cell exists in the selection bit line according to the first control signal, and then transmitting the Y-address to the bit line decoder according to a post program enable signal; And A post program data register configured to convert the fourth data input according to the second control signal into the second data and to store the second data and to transmit the second data to the sense amplifier according to the post program enable signal. Flash memory device comprising a. The method of claim 1, When at least two or more bit lines of the bit lines are selected for each of the Y-addresses by the bit line decoder during the post program operation, the second data may include a first bit line having an under erased cell among the selected bit lines. The flash memory device to have a different level if all of the second bit line that does not exist in the erase cell. The method of claim 2, And the bit line decoder outputs the second data having a low level to the first bit line, and outputs the second data having a high level to the second bit line. The method of claim 2 or 3, The comparator compares the third data detected through the first and second bit lines with the reference data, respectively, and determines that there are undershoot cells in the first bit line, and underscores the second bit line. A flash memory device for determining that no gussels exist. The method of claim 4, wherein And the comparator outputs the second control signal corresponding to the first bit line at a low level, and outputs the second control signal corresponding to the second bit line at a high level. The method of claim 1, The sense amplifier detects the third data independently from each of the selection bit lines through the selection bit line in the post program verification operation, and the second having data of the number of the selection bit lines in the post program operation. A flash memory device for receiving data and independently providing the data to the bit line decoder. The method according to claim 1 or 6, The comparison unit receives the third data including the number of data corresponding to the number of the selection bit lines and compares the third data independently with the reference data to determine whether there is an under erase cell for each selection bit line; device. The method according to claim 1 or 2, And the Y-address register does not store the Y-address when there is no over-cell in the selection bit line, and stores the next Y-address that is input next. The method of claim 8, And the next Y-address stored in the Y-address register is output to the bit line decoder when the post program enable signal is enabled. The method of claim 1, And the second data has a logic value corresponding to the level of the fourth data or a logic value corresponding to the level of the second control signal. The method of claim 1, The post program data register stores the fourth data or the second control signal according to the second control signal. The method according to any one of claims 1, 10 and 11, The second control signal is output at a low level when there is an under erase cell in the selection bit line, and is output at a high level when there is no under erase cell. The method of claim 12, And the level of the second control signal is independently determined for each of the selected bit lines. In the post program method of a flash memory device having the configuration of claim 1, Reading the third data through the sense amplifier from the memory cell connected with the selection bit line selected through the bit line decoder corresponding to the Y-address; Comparing the third data read by the sense amplifier with the reference data through the comparator to verify whether an under erase cell exists in the selection bit line; When there is a selection bit line in which an over erase cell exists in the selection bit line, the Y-address is stored through the Y-address register according to the first control signal, and has a level corresponding to the second control signal. Store the second Y-address by storing the second voltage in the post program data register or by incrementing the Y-address through the Y-address register when there is no under-cell in the selection bit line; Storing the second data having a level corresponding to the input fourth data in the post program data register; And The Y-address stored in the Y-address register is transmitted to the bit line decoder according to the post program enable signal, and the bit line decoder transmits the Y-address to the post program data register at the bit line selected by the transmitted Y-address. Transmitting the stored second data through the sense amplifier to perform a post program operation; Post program method of a flash memory device comprising a. The method of claim 14, When at least two or more bit lines of the bit lines are selected for each of the Y-addresses by the bit line decoder during the post program operation, the second data may include a first bit line having an under erased cell among the selected bit lines. A post-programming method of a flash memory device which has different levels when all of the second bit lines in which there are no erase cells exist. The method of claim 15, And the bit line decoder outputs the second data having a low level to the first bit line, and outputs the second data having a high level to the second bit line. The method according to claim 15 or 16, The comparator compares the third data detected through the first and second bit lines with the reference data, respectively, and determines that there are undershoot cells in the first bit line, and underscores the second bit line. A post program method of a flash memory device for determining that no gussels exist. The method of claim 17, And the comparator outputs the second control signal corresponding to the first bit line at a low level, and outputs the second control signal corresponding to the second bit line at a high level. The method of claim 14, The sense amplifier detects the third data independently from each of the selection bit lines through the selection bit line in the post program verification operation, and the second having data of the number of the selection bit lines in the post program operation. A post program method of a flash memory device for receiving data and independently providing the data to the bit line decoder. The method of claim 14 or 19, The comparison unit receives the third data including the number of data corresponding to the number of the selection bit lines and compares the third data independently with the reference data to determine whether there is an under erase cell for each selection bit line; Post program method of the device. The method according to claim 14 or 15, And the second data has a logic value corresponding to the level of the fourth data or a logic value corresponding to the level of the second control signal. The method according to claim 14 or 15, The post program data register stores the fourth data according to the second control signal, or stores the second control signal.

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