JP2000077606A - Power supply noise reduction package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply noise reduction package capable of bypassing effectively a noise voltage by a capacitor without increasing a mask pattern and a diffusion step of a semiconductor chip. SOLUTION: This package is constituted of a capacitor C, a semiconductor chip 1, and a bump 10, and the capacitor C is constituted of a conductor 1, a dielectric 2, and a conductor 3, and the semiconductor chip 1 is provided with a power supply pad 8 connecting electrically with a power supply wiring 7 on a semiconductor chip substrate 6, and a substrate pad 9 connecting electrically with the semiconductor chip substrate 6, and the conductor 1, the power supply pad 8, and conductor 3, and the substrate pad 9 are electrically connected to each other by the bump 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply noise reduction package including a power supply for reducing power supply noise and a bypass capacitor between ground and the power supply.

[0002]

2. Description of the Related Art A semiconductor integrated circuit device is required to have an output buffer circuit having high speed and high current capability. However, the output buffer circuit having the high-speed and high-current capability causes power supply noise and the like.

[0003] By changing the output pin at high speed and high current, the instantaneous current flowing to the output increases. This current flows through the wires of the system or the wires of the package that behave as inductance. The inductance function is described by the following relationships.

V = L × dI / dt With respect to the inductance L, when dI / dt increases,
It acts as a back electromotive force against the potential change of the output pin, and becomes noise. That is, noise is generated by the inductance component and the instantaneous current flowing therethrough.

As a method of reducing the noise, there is a method of connecting a grounded capacitor between an inductance component and an output buffer for generating a current.

In this circuit, power supply noise generated by the inductance component when the output buffer operates is bypassed by the grounded capacitor, and the noise is reduced.

FIG. 5 shows a package structure of a first conventional example (JP-A-5-206372) for reducing power supply noise. FIG. 6 is an equivalent circuit diagram of FIG.

An upper electrode 33 is formed on the back surface of the semiconductor chip I, a dielectric film 34 is formed on the surface of the upper electrode 33, and a lower electrode 35 is formed on the opposite surface of the dielectric film from the upper electrode, thereby forming a thin film capacitor. I do.

Semiconductor chip I on which thin film capacitor is formed
Is mounted on the package. Package element tower mounting part 40
Are connected to an external lead 39 for supplying a power supply potential. After the semiconductor chip I is fixed to the element mounting portion 40 via a metal brazing material, the electrodes on the semiconductor chip I and the package internal wiring 36 are electrically connected by the bonding wires 32, and the substrate potential of the semiconductor chip I becomes The external lead 38 is connected to the internal wiring of the chip substrate potential via the bonding wire 32.

As shown in FIG. 6, among the inductance 41 of the external lead of the package connected to the semiconductor chip I, the inductance 42 of the internal wiring of the package, and the inductance 43 of the bonding wire, the power supply noise generated in the inductance 41 of the external lead is: It is bypassed by a bypass capacitor C composed of a thin film capacitor.

Next, FIG. 7 shows a second conventional example (JP-A-8-162608) for reducing power supply noise. FIG.
FIG. 2 is a configuration diagram of a second conventional example in which a capacitor is formed on a semiconductor chip.

On the surface of the semiconductor chip I, a capacitor composed of a conductor 52 and a dielectric 53 connected to an electrode portion 54 of the capacitor is formed by respective patterns, and is electrically connected to a substrate electrode 56 of the semiconductor chip I. Is done.

Next, a method for manufacturing the capacitor will be described. The semiconductor chip I in which the uppermost layer other than the electrodes is insulated is set on the vacuum deposition layer, and the conductor 5
2 and aluminum to be the electrode portion 54 are formed using a pattern mask provided so as to be connected to the substrate electrode 56 of the signal system of the semiconductor chip I, and a dielectric 53 is formed thereon using the pattern mask.

Next, the other conductor 52 facing the capacitor is formed on the dielectric 53 using a pattern mask provided so as to be connected to the substrate electrode 56 of the semiconductor chip I to obtain the capacitor.

[0015]

In the first prior art in which power supply noise is reduced, a bypass capacitor formed by a thin film capacitor is connected between a semiconductor chip and a package internal wiring and a bonding wire. Because it has inductance and generates power supply noise,
The problem is that the noise cannot be sufficiently solved.

In the second conventional example, a pattern mask and a diffusion step for forming a thin film capacitor using a diffusion technique on an upper part of the semiconductor chip are required for electrically connecting to the electrode 6 of the semiconductor chip. This necessitates an extra step in forming a semiconductor chip, which has been a problem.

An object of the present invention is to provide a power supply noise reduction package capable of efficiently bypassing a noise voltage by a capacitor without increasing a mask pattern and a diffusion step of a semiconductor chip.

[0018]

The present invention comprises a capacitor, a semiconductor chip, and a bump, wherein the capacitor comprises a first conductor, a dielectric, and a second conductor. Comprises a power supply pad electrically connected to a power supply wiring on a semiconductor chip substrate, and a substrate pad electrically connected to the semiconductor chip substrate, wherein the first conductor, the power supply pad, and the second conductor And the substrate pad are electrically connected by the bump.

According to the present invention, a bypass capacitor between a power supply and a ground for reducing power supply noise is formed by using an empty PAD to form a parallel plate capacitor in a package by a bump technique, thereby providing a mask pattern for a semiconductor chip. The capacitor can be formed at a position close to the semiconductor chip without increasing the number of diffusion steps.

Further, the connection between the capacitor and the semiconductor chip is performed without using a bonding wire, and since there is no inductance serving as a noise source between the capacitor and the semiconductor chip, the noise voltage can be efficiently bypassed by the capacitor.

[0021]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing a first embodiment of a power supply noise reduction package according to the present invention. The power supply noise reduction package shown in FIG. 1 includes a capacitor C, a semiconductor chip I, and a bump 10.

The capacitor C includes a conductor 1, a dielectric 2,
It is constituted by a conductor 3, an electrode portion 22 drawn from the conductor 3, and an electrode portion 23 drawn from the conductor 1,
The capacitance is formed by alternately laminating the conductors 1 and 3 and the dielectric 2.

The semiconductor chip I includes an insulating layer 4, a field oxide film 5, a semiconductor chip substrate 6, a power supply wiring 7,
It is composed of a power supply pad 8 electrically connected to the power supply wiring 7 and a substrate pad 9 electrically connected to the semiconductor chip substrate 6.

The bump 10 electrically connects the electrode 22 of the capacitor C and the power supply pad 8 of the semiconductor chip I, and the electrode 23 of the capacitor C and the substrate pad 9 of the semiconductor chip I
And are electrically connected.

FIG. 2 is a configuration diagram in which a capacitor is formed on a semiconductor chip.

Reference numeral 21 denotes a power supply pad for supplying power to the semiconductor chip. In the semiconductor chip I, the power supply pad 8 and the power supply pad 21 are electrically connected. A bonding wire 24 electrically connects the semiconductor chip I and the package.

Next, a method of manufacturing the package configured as described above will be described.

At the design stage of the semiconductor chip I, the capacitor C is manufactured in accordance with the chip size and the position of the power supply pad. After the semiconductor chip I is manufactured, the semiconductor chip I and the capacitor C are electrically connected using the bumps 10. And assemble it into a package with the semiconductor chip I and the capacitor C integrated.

The power supply pad 8 uses an empty pad and uses a normal wiring layer to form the power supply wiring 7 of the semiconductor chip I.
Connect with

According to the above manufacturing method, a capacitor can be formed without changing the manufacturing process of a semiconductor chip.

Further, if a plurality of package lineups are prepared for one chip size, such as an ASIC, so that an empty pad can always be formed at a predetermined position, the same chip can be used for different semiconductor chips in different manufacturing processes. It is possible to form a package with these capacitors.

FIG. 3 is an equivalent circuit diagram of the first embodiment shown in FIGS.

As shown in FIG. 2, the capacitor C connected to the semiconductor chip I is made closer to the semiconductor chip I than the bonding wire 24. As shown in FIG.
It becomes the bypass capacitor C between the substrate of the semiconductor chip I and the power supply wiring, and the inductance 4 of the bonding wire.
3, the noise voltage generated by the package internal wiring inductance 42 and the external wiring inductance 43 can be bypassed, and the influence on the semiconductor chip can be eliminated.

Next, a second embodiment of the present invention will be described with reference to FIG.
Shown in A different configuration from the first embodiment is that the conductor 3 of the capacitor C is divided. With this configuration, even when the power supply of the semiconductor chip I is two power supplies, the capacitors C1 and C2 can be electrically connected to each power supply.

The manufacturing method is the same as that of the first embodiment.

[0037]

As is apparent from the above description, the power supply noise reduction package of the present invention separately manufactures a capacitor and a semiconductor chip, so that an extra pattern mask and an additional diffusion step are not required in forming a semiconductor chip. It is. In addition, the connection between the capacitor and the semiconductor chip is performed without using a bonding wire, and since there is no inductance serving as a noise source between the capacitor and the semiconductor chip, all noise voltages can be efficiently bypassed by the capacitor. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a configuration diagram in which a capacitor is formed on a semiconductor chip.

FIG. 3 is an equivalent circuit diagram of the first embodiment.

FIG. 4 is a sectional view showing a second embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 5 is a diagram showing a package structure of a first conventional example for reducing power supply noise.

FIG. 6 is an equivalent circuit diagram of the first conventional example.

FIG. 7 is a configuration diagram of a second conventional example in which a capacitor is formed on a semiconductor chip.

DESCRIPTION OF SYMBOLS 1, 3 conductor 2 dielectric 4 insulating layer 5 field oxide film 6 semiconductor chip substrate 7 power supply wiring 8 power supply pad 9 substrate pad 10 bump 21 power supply pad 22, 23 electrode part 24, 32 bonding wire 33 upper part Electrode 34 Dielectric film 35 Lower electrode 36 Package internal wiring 38, 39 External lead 40 Element mounting part 41 External lead inductance 42 Internal wiring inductance 43 External wiring inductance 52 Conductor 53 Dielectric 54 Electrode part 56 Substrate electrode

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[Procedure amendment]

[Submission date] June 24, 1999 (1999.6.2
4)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claim 4

[Correction method] Change

[Correction contents]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction contents]

[0018]

The present invention comprises a capacitor, a semiconductor chip, and a bump, wherein the capacitor comprises a first conductor, a dielectric, and a second conductor. includes a power supply pads which are power line electrically connected to the semiconductor chip on the substrate, a semiconductor chip substrate and electrically connected to the substrate pads, the
A capacitor is connected to a first conductor extending from the first conductor.
An electrode, and a second electrode drawn from the second conductor.
Wherein the first and electrode said power supply pad and the second electrode and the substrate pads, characterized in that it is electrically connected by the bumps.

Claims (6)

[Claims] 1. A capacitor comprising a capacitor, a semiconductor chip, and a bump, wherein the capacitor comprises a first conductor, a dielectric, and a second conductor, and the semiconductor chip comprises a power supply on a semiconductor chip substrate. A power supply pad electrically connected to wiring; and a substrate pad electrically connected to a semiconductor chip substrate, wherein the first conductor and the power supply pad, and the second conductor and the substrate pad are connected to the bump by the bump. A power supply noise reduction package, wherein the power supply noise reduction package is electrically connected. 2. The power supply noise reduction package according to claim 1, wherein said power supply pad uses an empty pad of said semiconductor chip. 3. The power supply noise reduction package according to claim 1, wherein one of the first conductor and the second conductor of the capacitor is divided into two. 4. A method for manufacturing a semiconductor device, comprising: manufacturing a capacitor in accordance with a chip size and a position of a power supply pad in a design stage of a semiconductor chip; electrically connecting the semiconductor chip and the capacitor using bumps after manufacturing the semiconductor chip; A method for manufacturing a power supply noise reduction package, comprising: assembling a package in a state where a chip and a capacitor are integrated. 5. The method according to claim 4, wherein the power supply pad uses an empty pad of the semiconductor chip. 6. The method according to claim 4, wherein one of the conductors of the capacitor is divided into two parts.