JP2000049761A - Sampling clock frequency information transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sampling clock frequency information transmission system, capable of efficiently transmitting the frequency information of a sampling clock provided with a frequency different from a transmission clock by a small bit number. SOLUTION: In this sampling clock frequency information transmission system, the frequency information is compression-encoded and transmitted in the form of a compressed code on a transmission side and the compressed code is decoded on a reception side at the time of transmitting the sampling clock frequency information from the transmission side to the reception side. As the compressed code, a differentially encoded code is used and is transmitted as the code of 2 bits, for instance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a sampling clock frequency used for sampling a television signal or the like,
More particularly, the present invention relates to a sampling clock frequency information transmission method for transmitting frequency information of a sampling frequency from a transmission side to a reception side.

[0002]

2. Description of the Related Art In general, as a transmission method for encoding and transmitting an image signal such as a television signal, a transmitting side samples an image signal by a sampling clock, and a sampled sample is called a sampling clock. There is a method of encoding with transmission clocks having different frequencies and transmitting the encoded data to a receiving side. In such a transmission system, when a sampling clock is generated in synchronization with a television signal, the sampling clock and the transmission line clock become asynchronous.

In this case, the receiving side needs to reproduce the sampling clock used on the transmitting side. In order to regenerate the sampling clock on the receiving side, the transmitting side sends the number of clocks in a fixed cycle T to the receiving side as frequency information, and based on this frequency information, generates a sampling clock having the same frequency as the transmitting side. A method of reproducing on the receiving side is adopted.

As such a sampling clock frequency information transmission method, there is, for example, a method described in Japanese Patent Application No. 52-117613 (hereinafter referred to as Reference 1).

[0005] Here, with reference to FIG. 4, a transmission method described in Patent Document 1 will be described. As shown,
On the transmitting side, a sampling clock generation circuit 1, a counter 2,
And a transmission clock generation circuit 3. The sampling clock generation circuit 1 and the transmission clock generation circuit 3
A sampling clock and a transmission clock are generated, respectively.
The counter 2 counts the number of sampling clocks for each period T obtained by dividing the transmission clock by m.

In this case, since the fluctuation range of the sampling clock and the transmission line clock is predetermined, it is not necessary to transmit the counted clock number from the transmitting side for all bits. For this reason, from the transmitting side, the lower bits, for example, the lower 8 bits, of the bits indicating the number of clocks in the changing range, are transmitted to the receiving side as frequency information I of the number of clocks in the T period.

On the receiving side, a period T obtained by dividing the transmission clock reproduced by the transmission clock reproducing circuit 7 by m is obtained.
Each time, the number of sampling clocks reproduced by the VCO circuit 12 is counted by the counter 9, and the lower 8 bits are taken out to obtain frequency information on the receiving side.

The subtractor 8 provided on the receiving side calculates the difference between the frequency information sent from the transmitting side and the frequency information on the receiving side. This difference is integrated by an integrating circuit 10 and then converted into an analog control signal by a D / A converter 11, and is converted as a voltage control signal into a voltage controlled oscillator (VCO) 1.
2 is supplied. In this case, the VCO 12 reproduces a sampling clock having a frequency corresponding to the control signal.

[0009] The frequency information of the reproduced sampling clock is stabilized by feedback control at a place where the frequency information matches the frequency information on the transmission side.

On the other hand, Japanese Patent Application Laid-Open No. 4-342386 (hereinafter referred to as cited reference 2) discloses that when transmitting a sampled signal from a transmitting side, among the sampled signals over n frames,
A transmission system is disclosed in which only the timing information of the first frame is detected by a transmission timing generation circuit, and this timing information is added to a selector to select a sampling signal and a video signal.

[0011]

In the method described in the above cited reference 1, for example, all 8-bit frequency information is transmitted from the transmitting side to the receiving side for each period T, and the receiving side performs pull-in. If the period T for transmitting the clock information is shortened in order to speed up the tracking, a large number of bits are required for transmitting the clock information, and the number of bits that can transmit the image signal and the like is reduced accordingly.

On the other hand, in the method described in Patent Document 2,
Although the transmission amount of the frequency information regarding the sampling clock can be reduced, there is a disadvantage that when the sampling signal changes during n frames, the change cannot be followed.

An object of the present invention is to provide a sampling clock frequency information transmission system capable of transmitting clock information from a transmitting side to a receiving side with a small number of bits.

It is another object of the present invention to provide a sampling clock frequency information transmission system capable of efficiently transmitting frequency information with a small number of bits and thereby allocating more bits to an image signal.

Still another object of the present invention is to provide a sampling clock frequency information transmission system capable of quickly responding to a change in a sampling signal.

[0016]

To achieve the above object, according to the solution to ## in the present invention, transmit frequency information I _i in the form of data compression code, thereby, the transmission side in fewer bits frequency information I _i To the receiver.

Here, the frequency of the subcarrier synchronization signal of the television signal is usually stable, and the frequency of the sampling clock synchronized therewith is also stable. Since the frequency of the subcarrier is shifted within an allowable range depending on the signal source, the sampling frequency greatly changes only when the signal source is switched by switching channels or the like. On the other hand, the transmission clock is always stable, and only changes slowly due to a temperature change or the like.

In consideration of the above, the frequency information I _i
Is differentially encoded and transmitted. The difference signal is quantized and encoded into three levels (2 bits) of 0 and ± 1.

[0019] or when the video signal source is Tsu switch, periodically to correspond to the transmission error, or performs initialization for correcting when necessary, to send it a number of bits the value of the frequency information I _i To

Thus, in a stable state, either 0 or ± 1 may be transmitted, and frequency information can be transmitted in 2 bits. If 0 and ± 1 are variable-length coded, further bit compression can be performed. Usually, since there are many occurrences of 0, in the present invention,
On average, frequency information can be transmitted with a value close to 1 bit.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG.
The sampling clock frequency information transmission method according to the embodiment includes a transmission side 31 and a reception side 32. Compared with the conventional example shown in FIG. 4, the sampling clock frequency information transmission system shown in FIG. 1 is different from the conventional example in that the transmitting side 31 and the receiving side 32 are connected by the encoding / decoding unit 4. Is different. Among the encoding and decoding unit 4, the encoding circuit 5 provided on the transmission side 31, and data compression encoding of frequency information I _i, and outputs the encoded data D _i. On the other hand, the decoding circuit 6 provided on the receiving side 32 outputs the encoded data _Di.
Is decoded and reproduced, and, for example, 8-bit reproduction frequency information I _i ′ is output. The reproduction frequency information I _i ′ is
And is processed in the same manner as in the case of FIG.
Is controlled. As a result, the VCO 12 sends a reproduction sampling clock having a frequency corresponding to the control signal to the counter 9. The counter 9 counts the number of reproduced sampling clocks within a period obtained by dividing the transmission clock reproduced by the transmission clock reproducing circuit 7, and sends the count value to the subtracter 8. In the subtractor 8, the lower 8
A difference between the bit and the reproduction frequency information I _i ′ is obtained, and a difference signal is output to the integration circuit 10.

Referring to FIG. 2, there is shown a specific configuration of the encoding circuit 5 and the decoding circuit 6 shown in FIG.

In the encoding circuit 5, a subtractor 21 has a frequency information _Ii and a predictor 2 composed of a register.
3 is provided. Subtractor 2
In step 1, the difference between the frequency information I _i and the predicted value is obtained, and the difference signal is sent to the quantizer 22. The quantizer 22 quantizes the difference signal according to its quantization characteristics and outputs a quantized signal.

The quantizer 22 has quantization characteristics of three levels (2 bits) of 0, +1 and -1. The quantizer 22 supplies the quantized difference signal to the code converter 24, while the adder 26
Also supply. The code converter 24 converts the quantized output into a 2-bit code and sends it out to the transmission path.

The adder 26 in the encoding circuit 5 includes a predictor 2
3 and a quantized difference signal, a local decoded signal is obtained and supplied to the predictor 23. The predictor 23 is configured by a register that operates with a clock having a period T, obtains a predicted value of frequency information in the next period T from the local decoded signal, and outputs the predicted value to the subtractor 21 and the adder 26.

On the other hand, a decoding circuit 6 provided on the receiving side
Has a sign inverse converter 27, and the sign inverse converter 27
Upon receiving the bit code, the quantized output signal is reproduced, and the reproduced difference signal is output to the adder 28. The adder 28 to which the predicted value is given from the predictor 29 outputs a decoded signal of frequency information from the reproduced difference signal and the predicted value. The decoded signal is a predictor 2 composed of a register.
9, the predictor 29 obtains a predicted signal of the next cycle from the decoded signal and outputs the predicted signal to the adder 28.

In this case, in consideration of a large change in frequency information due to a transmission line error, channel switching, or the like, the value of the frequency information input to the encoding circuit 5 for each period U obtained by dividing the period T by n. Is encoded by the code converter 24 and transmitted as it is to the decoding circuit 6 on the receiving side via the transmission path, whereby the encoding operation can be initialized.

In this configuration, in the normal state, a 2-bit code is transmitted, and an 8-bit signal for initialization is transmitted every period U.

If the frequency information greatly changes when the channel is switched, if the signal is transmitted by differential encoding with quantization characteristics of 0 and ± 1, it cannot follow the change of the signal of the input frequency information sufficiently and cannot be encoded. It is possible that a case will occur. In this case, the frequency information is forcibly transmitted in 8 bits, and when the receiving side receives the greatly changed frequency information, the VCO 1 immediately follows the value.
2 can reproduce a sampling clock having the same frequency as the transmitting side.

In this case, the encoding circuit 5 may be configured to monitor the magnitude of the difference signal and perform forced transmission when a large difference continues.

As a method of forcibly transmitting frequency information of 8 bits, a signal for distinguishing that an 8-bit signal is compulsory information and 8-bit frequency information may be transmitted together. In this case, the amount of bits to be transmitted differs depending on the case of forced operation, the period U, and the period T.

Next, as another configuration example, an example in which the number of coded bits for transmitting frequency information is constant (2 bits) will be described as a second embodiment of the present invention.

The quantization characteristic has three levels of 0 and ± 1,
If a 2-bit code is assigned to each level, for example, if 0 is [00], 1 is [01], and -1 is [11], code [10] remains. This is 8-bit frequency information. This is a header signal for distinguishing between them. Therefore, when transmitting a 2-bit header signal and 8-bit frequency information, the encoding / decoding process is stopped only for 5 time slots in the period T, and the header and frequency information of the 5 time slots (10 bits) are stopped. A total of 10 bits are transmitted by being divided into 2 bits.

The code inverse converter 27 monitors signals transmitted in 2-bit divisions every T period.
When the code of [0] is sent, the subsequent 8 bits are output to the adder 28 as the uncoded frequency information itself. When the codes [00], [01], and [11] are sent, they are inversely transformed as codes indicating the quantized output levels, and the quantized output levels of 0, 1, and −1 are respectively obtained. The data is reproduced and supplied to the adder 28.

When the frequency information is supplied to the adder 28,
The predictor 29 outputs a predicted value of 0, and the adder 2
The output of 8 reproduces the frequency information transmitted in 8 bits as it is.

On the other hand, when the reproduced quantized output level is supplied to the adder 28, the decoded value of the previous cycle is supplied from the predictor 29 as a prediction signal. Is obtained.

Next, with reference to FIG. 3, the data flow between the encoding circuit 5 and the decoding circuit 6 in the present invention will be compared with the data flow of the conventional example.

FIG. 3A shows a data flow in a conventional example. As shown in FIG. 3 (a), the conventional example, the frequency information I _i output from the counter 2 is transmitted as 8-bit information for each period T.

On the other hand, the first embodiment of the present invention shown in FIG.
For embodiments, the encoded data D _i output from the encoding circuit 5 is obtained by encoding the quantized output, the 2 bits long. Further, frequency information _Ii having a length of 8 bits is transmitted for initialization in each cycle U. FIG. 3 (b)
In this example, the frequency information of the 8-bit I ₁ and I _n is not coded, the other D ₂ to _{D n-1, D n +} 2 ~
In each time slot up to D _2n−1 , 2-bit encoded data is arranged and transmitted at a period T.

FIG. 3 (c) shows a data flow in the second embodiment of the present invention in which frequency information encoded into a 2-bit data string is transmitted for each period T.
Forcible initialization (processing of transmitting 8-bit frequency information as it is) is performed, for example, at the timing of the header (10). From this time slot to five time slots, no differential data is transmitted by differential encoding. Specifically, first, a code [10] indicating a header is sent to the first time slot (2 bits), and 8-bit frequency information I ₁ is sent to the second to fifth time slots. Signals I _{11 to} I divided every two bits
₁₄ are sequentially sent every period T. When the initialization is completed, differential encoding is performed from the next time slot, and 2
Bit encoded data _Di is transmitted.

[0041] In yet another embodiment, the reset interval, i.e., if the value changes during the time slot I ₁ of I ₅ time slots, the recipient is not a I ₁ I
It is desirable to send a value as close as possible to ₅ in order to shorten the frequency response time.

[0042] The value to send during initialization and I _2, further when sending the value of I ₂ in the time slot of the I ₃ ~I ₅ respectively, to perform the correction to approach the value of I ₃ ~I ₅ . When the correction is made in each time slot, the transmitted frequency information is not I ₂₁ , I ₂₂ , I ₂₃ and I ₂₄ ,
The _{I 21, I 32, I 43} , I 54. In this way, I
_A value as close to ₅ as possible can be sent without delay.

[0043]

As is apparent from the above description, according to the present invention, when the sampling frequency and the transmission line clock are not synchronized, the sampling frequency information can be transmitted efficiently with a small number of bits. There is. Further, in the present invention, the frequency response time can be shortened by arranging the frequency information at predetermined intervals.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a sampling clock frequency information transmission method according to a first embodiment of the present invention.

FIG. 2 is a block diagram for more specifically describing the encoding / decoding circuit of the present invention shown in FIG.

FIG. 3 is a time chart for explaining a flow of data of frequency information according to the present invention and the prior art.

FIG. 4 is a block diagram showing a conventional sampling clock frequency information transmission method.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 sampling clock generation circuit 2, 9 counter 3 transmission clock generation circuit 4 encoding / decoding circuit 5 encoding circuit 6 decoding circuit 7 transmission clock regeneration circuit 8 subtractor 10 integration circuit 11 D / A 12 VCO 21 subtractor 22 Quantizer 23,29 Predictor 24 Code converter 26,28 Adder 27 Code inverse converter

Claims (9)

[Claims] 1. A sampling clock frequency information transmission system for transmitting sampling clock frequency information from a transmitting side to a receiving side, wherein the transmitting side performs predetermined compression encoding on the sampling clock frequency information, A sampling clock frequency information transmission method, comprising: encoding means for generating a compression code; and the receiving side includes decoding means for decoding the compression code. 2. The sampling clock frequency information transmission method according to claim 1, wherein said predetermined compression encoding is differential encoding. 3. The method according to claim 2, wherein:
A sampling clock frequency information transmission method, wherein differential encoding is performed using a quantizer having three levels of quantization characteristics. 4. The method according to claim 3, wherein the encoding unit comprises:
The sampling clock frequency information and a subtractor that calculates a difference signal between the prediction value and the output signal to the quantizer, and a code that converts a quantized code from the quantizer into the compressed code. A transformer, and an adder that generates a local decoded signal from the quantized code and the predicted value, wherein the local decoded signal is provided to a predictor that outputs the predicted value. Sampling clock frequency information transmission method. 5. The code decoding device according to claim 3, wherein the decoding means inversely transforms the compression code and outputs a reproduced quantized signal. A sampling clock frequency information transmission method, comprising: an adder that receives a predicted value and outputs a decoded signal, wherein the decoded signal is provided to a predictor that generates the predicted value. 6. A transmitter for transmitting sampling clock frequency information, comprising a coding means for performing a predetermined compression coding on the sampling clock frequency information to generate a compression code. A transmitter for transmitting sampling clock frequency information. 7. A method for transmitting sampling clock frequency information having a predetermined number of bits, wherein the number of bits obtained by compressing and coding the sampling clock frequency information is smaller than the predetermined number of bits. A sampling clock frequency information transmission method, wherein a number of compression codes are obtained and the compression codes are arranged at predetermined intervals. 8. The sampling clock frequency information transmission method according to claim 7, wherein the non-coded sampling clock frequency information is arranged before the compression code. 9. The sampling clock frequency according to claim 7, wherein a header signal indicating the beginning of the sampling clock frequency information is transmitted prior to the compression code, and after the header signal, the sampling clock frequency that is not encoded is transmitted. A sampling clock frequency information transmission method, wherein information is transmitted at predetermined intervals in a form in which information is divided into predetermined bits, and then the compression code is transmitted.