JPH11234634A - Data transmitter and data multiplexer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the data multiplexer generating a moving picture coding experts group MPEG 2 transport stream to grasp properly a state of an output buffer and to control properly a buffer in response to a change in a read clock, and to output the transport stream properly. SOLUTION: A video encoder 20 and an audio encoder 24 encode video/audio data by the MPEG 2 system. A transport packet is generated via switch circuits 34, 36 and outputted sequentially via an FIFO memory 38. In this case, an FIFO residual amount detection section 432 detects an amount of the transport packet left in the FIFO memory 38 and write of the transport packet to the FIFO memory 38 is controlled based on the remaining amount and an external read clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmitting apparatus for transmitting a data packet in which desired data such as video data and audio data are multiplexed, and to multiplex desired data such as video data and audio data. MPEG method (Moving Picture coding Experts Grou
The present invention relates to a data multiplexing apparatus that generates a transport stream (TS) of a high-quality moving image coding system using p.

[0002]

2. Description of the Related Art Video data and audio data are MPEG
Digital television broadcasts, which are compression-encoded by a system or the like, multiplexed into predetermined transmission packets, and distributed to viewers, are being put to practical use. In the MPEG system, when multiplexing audio / video data, it is necessary to consider the remaining buffer capacity of the decompression decoding device on the receiving side on the transmitting side. In other words, the transmitting side manages the data amount and multiplexes and transmits audio / video data so that neither overflow nor underflow occurs in the reception buffer of the decompression decoding device defined in the MPEG standard. Has become.

As an example of a data multiplexing apparatus conforming to such regulations, there is, for example, a data multiplexing apparatus described in Japanese Patent Application No. 9-71834 to the present applicant. In this data multiplexing apparatus, multiplexing of each data is managed in units of one video frame period, so that audio / video data or the like can be appropriately managed without strictly managing the receiving buffer without breaking down the receiving buffer. Can be sent.

[0004] As an interface of a transport stream output from such an MPEG encoder, generally, standards called DVB-parallel and DVB-serial are used. DVB-parallel is 25
A pin D-Sub connector is used, and a DVB-serial uses a BNC connector. Furthermore, DVB-serial
The synchronous I / F (synchronous I / F) and the asynchronous I / F
F (asynchronous I / F), the latter DVB Async
A hronous Serial I / F (DVB-ASI) is more commonly used. In addition, DVB-parallel
/ F (synchronous I / F), DVB Synchronous P
Only arallel I / F (DVB-SPI) exists. Note that the byte clock in the DVB-ASI described above is 27 MHz, and is converted into 8B / 10B and 270 MHz.
transmitted at a rate of z. The maximum transmission path is 27 ×
8 = 216 Mbps, of which the period during which there is no transport stream packet (TS Packet) is
Invalid data is output.

In a data multiplexing apparatus in which data is read at a specific rate, when a buffer for actually outputting a transport stream is controlled, underflow or overflow does not usually occur in the buffer due to hardware. Thus, the amount of data written to the buffer is controlled. Specifically, a setting is made so that data slightly larger than the amount of data to be written to the buffer is read from the buffer, and data different from the elementary stream is appropriately written to the buffer, so that the buffer does not underflow. Data amount is controlled. Therefore, if the rate of the transport stream to be output is fixed, the sum of the bit rates of the elementary streams such as the video stream and the audio stream is set to a value lower than the output rate. Note that invalid data used for adjusting the data amount of this buffer is NU recognized by the MPEG system.
LL packet data.

[0006]

As described above, since the processing for controlling the buffer for outputting the transport stream is performed by hardware in the data multiplexing device 2, for example, N
There is a problem that it is not possible to know the control state of the buffer such as whether or not a UL packet is inserted. Therefore, for example, element stream and NUL
It is not possible to perform processing such as monitoring the state of the transport stream and checking whether the form of the packet is the intended form, such as monitoring the multiplexing state of L data and confirming that there is no abnormality. The problem arises.

Further, for example, when the clock for reading the transport packet from the buffer is not specified, that is, when there is a possibility that the transport packet is read with a different clock depending on the applied standard / format, the state of the buffer is determined. There is also a problem that it is difficult to grasp and properly buffer. In particular, when the read clock is supplied from the outside, it is desired that the state of the buffer be grasped more accurately and appropriate control be performed, but such a demand cannot be met. Also occurs.

Accordingly, an object of the present invention is to provide, for example, M
In a data transmission device for transmitting a data packet such as a PEG2 transport packet, the state of a buffer in an output stage can be properly grasped, so that even if a read clock changes, the amount of data in the buffer can be appropriately adjusted accordingly. The present invention is to provide a data transmission device capable of controlling the data transmission and appropriately outputting a data packet. Another object of the present invention is to provide a data multiplexing apparatus that encodes and multiplexes data such as video data and audio data in accordance with the MPEG2 system to generate a transport stream. It is therefore an object of the present invention to provide a data multiplexing apparatus that can appropriately grasp buffer information, can appropriately control a buffer in response to a change in a read clock, and can output an appropriate transport stream.

[0009]

Therefore, a data transmitting apparatus according to the present invention comprises: packet generating means for sequentially generating a predetermined data packet for transmission from arbitrary data to be transmitted; Are sequentially recorded and sequentially output based on an arbitrary output signal input from the outside, and remaining data amount detecting means for detecting the amount of remaining data packets recorded in the buffer means and not yet output Based on the detected remaining data packet amount and the output signal, so that the data packets sequentially recorded from the buffer means are sequentially output based on the output signal. Buffer recording control means for controlling recording of data packets.

In the data transmitting apparatus having such a configuration, arbitrary data to be transmitted is sequentially converted into packets for transmission in the packet generation means, and the packets are sequentially recorded in the buffer means, and a clock input from the outside is used. The signals are sequentially output based on an output control signal such as a signal.
At this time, the remaining data amount detecting means detects the amount of remaining data packets recorded in the buffer means and not yet output, so that the buffer recording control means controls the detected remaining data packet amount and output control. Based on the signal, the recording of the packet data in the buffer unit is controlled so that the data packet is appropriately output from the buffer unit, that is, the buffer unit does not overflow or become empty.

Further, the data multiplexing device of the present invention converts any data to be transmitted including video data and audio data into the MPEG2 format (Moving Picture Code).
encoding means for encoding according to a high-quality moving picture encoding method by the NG Experts Group), and multiplexing for multiplexing the encoded data in a predetermined format to generate an MPEG2 transport stream composed of MPEG2 transport packets. And buffer means for sequentially recording the generated transport packets and sequentially outputting the transport packets based on an arbitrary output signal input from the outside,
Remaining data amount detection means for detecting the amount of remaining transport packets recorded in the buffer means and not yet output, and the transport packets sequentially recorded from the buffer means are sequentially output based on the output signal And buffer recording control means for controlling recording of the transport packet in the buffer means based on the detected amount of remaining transport packets and the output signal.

In the data multiplexing apparatus having such a configuration, the encoding means encodes the video / audio data according to the MPEG2 system, and the multiplexing means generates a transport packet. Then, the packets are sequentially recorded in the buffer means and sequentially output based on an output control signal such as a clock signal input from the outside. At this time, the remaining data amount detection means detects the amount of remaining transport packets recorded in the buffer means and not yet output, so that the buffer recording control means Based on the output control signal, the transport packet is appropriately output from the buffer means, that is, the recording of the transport packet in the buffer means is controlled so that the buffer means does not overflow or become empty. You.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A first embodiment of a data multiplexing apparatus according to the present invention will be described with reference to FIGS. In the first embodiment, a data multiplexing device that outputs transport packets by DVB-ASI will be described.

First, the configuration of the data multiplexing device will be described. FIG. 1 is a block diagram showing the configuration of the data multiplexing device. The data multiplexing device 2 includes a video encoder 20, an audio encoder 24, a subtitle encoder 28, a multiplexing system 12, and a control system 42.

First, the video encoder 20 will be described. FIG. 2 is a block diagram showing a configuration of the video encoder 20. The video encoder 20 includes an addition circuit 20
2, DCT circuit 204, quantization circuit 206, inverse quantization circuit 208, inverse DCT circuit 210, addition circuit 212, frame memory circuit 216, variable length coding circuit (VLC) 2
18, a bit rate control circuit 220, and a variable length code buffer (VLC buffer) 222.

In such a configuration, the video encoder 20 converts video data input from the outside into MPEG2 data.
Compression encoding to generate a video stream having a data amount substantially equal to the target data amount, and a data size IF 30a and a FIFO memory 32 of the data multiplexer 2.
Output to a. Therefore, video encoder 2
For the bit rate control circuit 220 of 0, the target data amount is set in advance by the CPU 424 of the data multiplexer 2. The bit rate control circuit 220 performs quantization based on the data amount of the video stream actually generated by the variable-length encoding circuit 218 so that the set target data amount and the data amount after compression encoding become equal. 206
Control.

Next, the audio encoder 24 will be described. FIG. 3 is a block diagram showing a configuration of the audio encoder 24. The audio encoder 24 includes a sub-band analysis filter bank 240, a linear quantization circuit 2
42, bit compression circuit 244, FFT (fast fourier tr
ansform) circuit 246, a psychological auditory model 248, a dynamic bit allocation circuit 250, a scale factor selection information storage circuit 252, a scale factor extraction circuit 254, a side information encoding circuit 256, and a bit stream generation circuit 258. In such a configuration, the audio encoder 24 compresses and encodes audio data input from an external device in accordance with the MPEG2 system, generates an audio stream, and sends the audio stream to the data size IF 30b and the FIFO memory 32b of the data multiplexer 2. Output.

The subtitle encoder 28 encodes private data (user data) such as subtitle data input from an external device. Note that the subtitle encoder 28 may directly receive the encoded subtitle data from outside. In that case,
For example, the ENIF circuit 420 receives the encoded subtitle data via a LAN such as an Ethernet network or the SIF 422 via a serial line, and stores the encoded subtitle data in the RAM 430 via the CPU bus. d.

The multiplexing system 12 includes an input FIFO memory 32a, 32b, 32c, a first switch circuit 34, a second switch circuit 36, an output FIFO memory 38, and a SCSI (small computer system interface). An interface circuit (SCSIIF circuit) 40 is provided.

The FIFO memories 32a, 32b, and 32c buffer the video stream, the audio stream, and the subtitle stream input from the video encoder 20, the audio encoder 24, and the subtitle encoder 28, respectively. Output for b and c.

The first switch circuit 34 controls the input terminals a, b, and
One of c and d is selected, one of the elementary streams input to each of these input terminals is selected and multiplexed, and output to the input terminal b of the switch circuit 36. Note that, when there is no elementary stream input to any of the input terminals, the switch circuit 34
Alternatively, when stuffing processing is performed, predetermined blank data (consecutive logical values 1 or 0) is output without selecting any of the input terminals a, b, c, and d.

The second switch circuit 36 selects one of the input terminals a and b according to the control of the multiplexing system 12 through the control signal, and inputs an elementary stream input from the switch circuit 34 to the input terminal b. Either or
A private data stream input from the processing RAM 426 to the input terminal a is selected and multiplexed, and
Output to the memory 38 and the SCSIIF circuit 40.

The FIFO memory 38 includes a switch circuit 36
Buffer the multiplexed data stream and output it as a transport stream to an external device such as a communication line (not shown).

The SCSIIF circuit 40 includes a switch circuit 3
The multiplexed data stream is output to a recording device (not shown) such as a hard disk device (HDD) or a magneto-optical disk device (MOD) and recorded.

The control system 42 includes a data size counting interface circuit 30a, 30b, 30c, and a RAM 43.
0, Ethernet interface circuit (ENIF) 4
20, serial interface circuit (SIF) 42
2, a CPU 424, a processing RAM 426, and a control data RAM 428.

Data size IF 30a, 30b, 30c
Respectively, counts the data size of each frame of the video stream, audio stream, and subtitle stream input from the video encoder 20, the audio encoder 24, and the subtitle encoder 28, and outputs the data size to the CPU 424 via the CPU bus.

The ENIF circuit 420 receives private data input via a LAN such as an Ethernet (not shown), and receives the private data via a CPU bus.
And also receives the encoded subtitle data and outputs them to the RAM 430 via the CPU bus.

The SIF circuit 422 receives, for example, serial-format private data input from a computer, receives the encoded subtitle data to the CPU 424 via the CPU bus, and
Each is output to the RAM 430 via the PU bus.

The CPU 424 is composed of, for example, a microprocessor, a ROM for storing programs, and peripheral circuits thereof, and controls each section of the data multiplexer 2 so that the data multiplexer 2 performs a desired operation. I do. Specifically, the CPU 424 sets a target data amount to, for example, the bit rate control circuit 220 of the video encoder 20.

The CPU 424 controls the control data RA
Using the control data stored in M428, the contents of the adaptation field including the information of the PCR and the PES header are generated. The generated header is the RA for processing.
After being stored in M426, the second switch circuit 36
, Whereby transport packetization of the multiplexed data stream is performed. The header data is stored in the ENIF circuit 240 or the SIF circuit 42.
2 and may be created based on private data stored in the RAM 426.

The CPU 424 has a data size IF
30a, 30b, 30c, ENIF circuit 420 and S
The data size input from the IF circuit 422, and
The order of the elementary streams to be multiplexed, the multiplexed data amount of each elementary stream, and the like are determined based on the remaining storage capacity (remaining buffer capacity) of the FIFO memories 32a, 32b, and 32c, and the switch circuit 34 is determined according to the determination. , 36 are controlled.

At this time, the FIFO memory 3 operates so that the FIFO memory 38 functions properly without overflow or underflow, and a desired transport stream is appropriately output from the data multiplexer 2.
8 controls writing of a transport packet. The control of the FIFO memory 38 according to the present invention will be described later in detail.

The processing RAM 426 is a memory for storing data to be handled when the CPU 424 performs the above-described processing. Specifically, for example, the CPU 4
The header generated at 24 is stored in the processing RAM 426, and is output from the processing RAM 426 directly via the second switch circuit 36. Also, the CPU 42
4 is the data of the encoded data amount read from the data size IFs 30a, 30b, 30c, etc., and the ENIF circuit 2
Private data or the like input via the SIF circuit 40 or the SIF circuit 422 is temporarily stored in the processing RAM 426, and is used for processing in the CPU 424.

The control data RAM 428 is
Reference numeral 4 denotes a memory for storing, for example, control data related to the processing as described above. RAM 42 for control data
8 stores, for example, control data related to the creation of the header data described above.

Next, the operation of the data multiplexing device 2 will be described. In the data multiplexing device 2, the video encoder 20 compresses and encodes video data to generate a video stream of a desired data amount, and the audio encoder 24 compresses and encodes audio data to generate an audio stream of a desired data amount. Then, the subtitle encoder 28 compresses and encodes user data such as subtitle data to generate a subtitle stream.

At this time, the data size IFs 30a, 30
b and 30c respectively count the data size of each elementary stream input from the video encoder 20, the audio encoder 24, and the subtitle encoder 28 for each frame, and output the data size to the CPU 424. Each generated elementary stream is applied to the switch circuit 34 via the FIFO memories 32a to 32c,
One of the elementary streams is sequentially selected and multiplexed, and output to the switch circuit 36.

The control data stored in the control data RAM 428 or the control data input via the ENIF circuit 240 or the SIF circuit 422
CPU 424 using the user data stored in
Generates an adaptation field containing PCR information and the contents of a PES header,
After being stored in 426, it is output to the switch circuit 36. Then, the CPU 424 controls the data size IF 30
a, the order of the elementary streams to be multiplexed, the amount of multiplexed data of each elementary stream, etc., based on the data size input from a, 30b, and 30c and the remaining storage capacity of the FIFO memories 32a, 32b, and 32c. The CPU 424 determines the switch circuit 3
4,36 multiplexing operations are controlled.

Further, the operation of writing the multiplexed data to the FIFO memory 38 is controlled by a method described later, whereby the multiplexed data stream is converted into a transport packet, and the FIFO memory 38 is sequentially and appropriately adjusted.
Will be recorded. The multiplexed data stream buffered in the FIFO memory 38 is sequentially output based on a predetermined output clock, and output as a transport stream to an external device such as a communication line (not shown). The data stream multiplexed by the switch circuit 36 is output to a recording device (not shown) such as a hard disk device via the SCSIIF circuit 40.

In this manner, in the data multiplexing device 2, multiplexing of each data is managed in units of one video frame period, and audio / video data and the like are appropriately transmitted without breaking the receiving buffer. .

Next, a method for controlling writing of transport packets to the FIFO memory 38 in the data multiplexing apparatus 2 according to the present invention will be described. As described above, in the data multiplexing device 2,
A transport stream is output in DVB-ASI. In DVB-ASI, the output clock, that is, FI
As the read clock of the FO memory 38, the same internal clock as the system clock is used. Since the clock is 27 MHz, the number of clocks in one frame is 90 in the case of a 525/60 system as shown in Expression 1.
Equation 2 for a 0900 clock, 625/60 system
As shown in FIG.

[0041]

FRAME_CLKS = 1716 × 525 = 900900 (1) FRAME_CLKS = 1728 × 625 = 10800000 (2)

The data multiplexing apparatus 2 outputs a DVB-ASI transport packet with a constant interval between transport packets (188 bytes). Therefore, the bit rate R at this time is expressed by the following equation (3), where N is the interval between the first data of the transport packet.
become that way.

[0043]

R = 27 × 8 × 188 / N [Mbps] (3)

When the bit rate R determined by the equation (3) is applied, that is, when the data interval N at the head of the transport packet is used, the read clock becomes 27 MHz.
In DVB-ASI, the number P shown in Equation 4 in one frame
Is read from the FIFO memory 38.

[0045]

P = FRAME_CLKS / N (4)

Therefore, by writing the same amount of transport packets into the FIFO memory 38,
The FIFO memory 38 can be controlled without failure.
However, in Equation 4, since the number of packets P is not always divisible, that is, not always an integer value, Equation 5
As shown in Expression 7, the correction is performed for each frame.

[0047]

## EQU4 ## FLAME_CLKS2 = FRAME_CLKS + Q _-1 (5) P = FRAME_CLKS2 / N (6) Q = FRAME_CLKS2% N (7)

In Equations 5 to 7, A% B represents the remainder of A / B. P is the number of write transport packets, Q is the number of clocks less than N to carry over to the next frame, and Q ₋₁ is Q carried out one frame before. Note that the initial value of the remaining clock number Q is 0.

In the data multiplexing device 2, the FIFO
The number of transport packets written to the memory 38 is controlled in this way. Note that, at this time, by starting to write the transport packet to the FIFO memory 38 and then starting reading it one frame later,
Almost one frame of data is stored in the FIFO memory 38, and the FIFO memory 38 is appropriately controlled without overflow or failure.

A procedure for actually controlling the writing of the transport packet to the FIFO memory 38 in such a manner will be described with reference to FIG. FIG.
5 is a flowchart illustrating a transport packet writing control algorithm for the FO memory 38.

First, before starting encoding, initialization is performed. That is, the transport packet interval N is calculated based on the required transport packet rate, the variable Q indicating the number of clocks carried forward and the variable count_frame for counting the number of frames are cleared to 0, and the clock number of one frame is indicated. Variable FRAM
E_CLKS is a value corresponding to the system to be processed, that is, 900 900 (525/60 system) or 1080
000 (625/50 system) is set (step S10). When encoding is started (step S
11) Wait for the video frame signal to be encoded and output (step S12). When the video frame signal is input, the value count_ of the frame number counter is counted.
The frame is counted up by one (step S1)
3).

When this counter value count_frame is 1, since the encoding has just started, the FIF
The reading of the O memory 38 has not started yet, and step S1
The process proceeds to the process of No. 6 (step S14). When the processing of the second frame is started after the processing of steps S16 to S18 described later, the frame counter value co
When unt_frame is 2, the process proceeds from step S14 to step S15, and instructs to start reading data from the FIFO memory 38 (step S1).
5). Then, according to Equation 5, the number of frame clocks FRA
The corrected frame clock number FRAME_CLKS2 is calculated by adding the carry-over clock number Q to ME_CLKS (step S16), and the corrected frame clock number FRAM is calculated.
Based on E_CLKS2 and the packet interval N, Equation 6
Then, the number of write packets P and the number of carry-over clocks Q are obtained from Expression 7 (step S17).

Then, the number of packets P obtained in step S17 is written in the FIFO memory 38 (step S18), and the process proceeds to step S12 and subsequent steps for the next frame period. Incidentally, in step S18, if the packet count P _es elementary stream is less than the write count P is a P-P _es number of NULL packets F
The data is written to the FIFO memory 38 so that P transport packets are written to the FIFO memory 38 as a whole. The NULL packet used at this time is:
It is assumed that the information is recorded in the processing RAM 426 in advance.

As described above, in the data multiplexing apparatus 2 of the present embodiment, the FIFO memory 38 can be controlled so as not to fail, and the transport packet can be appropriately output by DVB-ASI. In addition, the control can be easily performed without increasing the size of the apparatus, since it is only necessary to add software having a simple algorithm as shown in FIG.

Second Embodiment A data multiplexing apparatus according to a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, a description will be given of a data multiplexing apparatus capable of outputting a transport packet by either DVB-ASI or DVP-SPI according to a request. In the following description, the same components having the same functions as those of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 5 is a block diagram showing a configuration of a data multiplexing device 2b according to the second embodiment. As shown in the figure, the data multiplexing device 2b has substantially the same configuration as the data multiplexing device 2 of the first embodiment, except that the data multiplexing device 2b has a FIFO remaining amount detection unit 432.
The data multiplexing apparatus 2 differs from the data multiplexing apparatus 2 in the method of applying a clock when reading a transport packet from the FIFO memory 38 and the method of controlling the writing of the transport packet to the FIFO memory 38 in the CPU 424. Other, video encoder 20, audio encoder 24, subtitle encoder 28, multiplexing system 1
The configuration and function of each unit of the control system 2 and the control system 42 are the same as those of the data multiplexer 2.

The FIFO remaining amount detecting section 432 outputs the FIFO
The amount of data buffered in the O memory 38 is detected and notified to the CPU 424. FIFO remaining amount detection unit 4
Specifically, for example, the counter 32 that differentiates the write enable signal and the read enable signal of the FIFO memory 38 and counts up or down a counter indicating the remaining data amount can be configured. The data amount notified to the CPU 424 is F
It is used for controlling writing of a transport packet to the IFO memory 38.

In the data multiplexing apparatus 2b, there are two types of clock application methods for reading a transport packet from the FIFO memory 38. First
Is similar to the method of reading the transport packet from the FIFO memory 38 in the data multiplexing device 2 of the first embodiment, but based on the 27 MHz clock inside the data multiplexing device 2b by DVB-ASI. This is a method of outputting a packet.

The second method is to output a transport packet by DVB-SPI based on an externally applied clock. The DVB-SPI is an I / F for receiving a clock from a modulator connected to the data multiplexing device 2 and outputting a transport packet, and a read clock of the FIFO memory 38 is a clock synchronized with an external clock. Therefore, there is no guarantee that this clock will be 27 MHz, which is the same as the internal clock of the data multiplexing device 2, nor that the relationship between the internal clock and each frame will be constant. In the embodiment, the transport packet interval N) is constant and 1
Only 88 or 204 are allowed.

To cope with these two types of transport packet reading methods, the data multiplexing device 2b
In, the writing of the transport packet to the FIFO memory 38 is controlled by the method as shown in FIG. First, before encoding is started, initialization is performed (step S20). As an initial setting, first, a transport packet interval N is determined based on a required transport packet rate. This interval N is calculated based on the requested transport packet rate when the interface is DVB-ASI, and is 188 or 204 when the interface is DVB-SPI.
Is a predetermined value. Also, a variable Q indicating the number of carry-over clocks and a variable co
Unt_frame is cleared to 0, and a variable FRAME_CLKS indicating the number of clocks of one frame is set to a value corresponding to the processing target system, that is, 900900 (525 /
60 system) or 1080000 (625/50 system).

When encoding is started (step S2)
1) Wait for the video frame signal to be encoded and output (step S22). When the video frame signal is input, the value count_f of the frame number counter is counted.
The count is incremented by one (step S23).
When the counter value count_frame is 1,
Since the encoding has just started, the FIFO memory 38
Does not start yet, and proceeds to the processing of step S26 (step S24). In addition, step S26 described later
When the process of the second frame is started after the process of step S33, the frame counter value count_frame
When e is 2, the process proceeds from step S24 to step S25, and instructs to start reading data from the FIFO memory 38 (step S25).

Next, if the interface is DVB-ASI
Or DVB-SPI (step S26),
In the case of DVB-ASI, the process of step S31 is immediately performed, and in the case of DVB-SPI, steps S30 to S31 are performed.
In step S33, the number of clocks for one frame is determined.

In the case of DVB-SPI, the remaining data amount fifo_depth of the FIFO memory 38 is determined by the FIFO
The data is read from the remaining amount detection unit 432 (step S27), and the data remaining amount fifo_depth and the reference value fifo_
Compare with depth_ref (step S28).
In step S28, the remaining data amount fifo_dep
When th is larger than the reference value fifo_depth_ref, the difference value fifo of the remaining data amount is calculated based on Expression 8.
_Diff, and the difference value fifo_dif
Based on f, the number of clocks FRAME_CLKS for one frame period is determined by equation 9 (step S29).

[0064]

## EQU00005 ## fifo_diff = fifo_depth_ref-fifo_depth (8) FRAME_CLKS = FRAME_CLKS + N.times.depth_diff (9)

In step S28, the remaining data amount fifo_depth is set to the reference value fifo_depth.
If the difference is not more than _ref, a difference value fifo_diff of the remaining data amount is obtained based on Expression 10, and further, based on the difference value fifo_diff, the number of clocks FRAME_CLKS in one frame period is determined by Expression 11 (Step S30).

[0066]

[Mathematical formula-see original document] fifo_diff = fifo_depth-fifo_depth_ref ... (10) FRAME_CLKS = FRAME_CLKS-N * depth_diff ... (11)

Then, in the case of DVB-ASI, and
In the case of DVB-SPI, if the new number of clocks per frame is determined in steps S27 to S30, the process proceeds to step S31.
According to Equation 5, the frame clock number FRAME_CLKS
Is added to the carry-over clock number Q to calculate a corrected frame clock number FRAME_CLKS2 (step S3).
1), the number of corrected frame clocks FRAME_CLK
6 and 7 based on S2 and the packet interval N
Thus, the number of write packets P and the number of carry-over clocks Q are obtained (step S32). And step S
The number of packets P obtained at 32 is stored in the FIFO memory 38.
(Step S33), and the process proceeds to step S22 and subsequent steps for the next frame period.

The predetermined reference value fifo_depth_ref used when DVB = SPI is determined based on the number of data in one frame, the intermediate value of the capacity of the FIFO memory 38, and the like. Also, in step S33,
If the packet count P _es elementary stream is less than the write count P writes the P-P _es number of NULL packets in the FIFO memory 38, so that the P number of transport packets as a whole is written into the FIFO memory 38 To It is assumed that the NULL packet used at this time is recorded in the processing RAM 426 in advance.

As described above, in the data multiplexing device 2b, the number of clocks of one frame with respect to the external clock is determined by the remaining data amount fifo_of the FIFO memory 38.
The depth is determined in consideration of the depth. That is, F
When the remaining data amount fifo_depth of the IFO memory 38 is smaller than a predetermined value fifo_depth_ref, the number of clocks per frame is increased by increasing FRAME_CLKS, and when the remaining data amount fifo_depth is increased, FRAME_CLKS is decreased. Therefore, the transport packet can be recorded in the FIFO memory 38 so that the remaining amount of data in the FIFO memory 38 is always appropriate and an appropriate transport packet can be output. As a result, it is possible to transmit an appropriate transport stream to the receiving side without causing a failure in the receiving buffer.

Also, for DVB-ASI, DVB-ASI
Since it can also handle SPI, it is possible to provide a data multiplexing apparatus applicable to a wider range of applications.

Note that the present invention is not limited to the present embodiment, and various suitable modifications are possible. For example, the CPU 424 controls writing to the FIFO memory 38 according to the first and second embodiments. However,
Processing related to the control of the data multiplexing device 2 is as follows.
It is not limited to such a form. For example, the control may be performed by a control circuit of a dedicated FIFO memory 38 that performs the same processing, or the same control may be performed by a controller or the like higher than the data multiplexer 2.

In particular, as shown in the second embodiment,
In the data multiplexing apparatus 2 having the configuration of the FIFO remaining amount detecting section 432, various controls and the state of transmission of the transport stream can be detected based on the detection result of the FIFO remaining amount detecting section 432. Therefore, a controller or DV higher than the data multiplexing device 2
It is conceivable that an arbitrary configuration unit or the like linked to the control unit of the B system can use the detection result of the FIFO remaining amount detection unit 432. Therefore, such FI
The control for the FO memory 38 may also be performed by such a controller. Even in such a mode, the F level is determined based on the detection result of the FIFO remaining amount detection unit 432.
It is clear that the write control to the IFO memory 38 is within the scope of the present invention.

In the data write control method for the FIFO memory 38 of the data multiplexing apparatus 2b of the second embodiment, in the case of DVP-SPI, the initial value of the number of clocks FRAME_CLKS for one frame is 9090.
0 or 1080,000. This value is a suitable value when the transport packet read clock from the FIFO memory 38 input from the outside is 27 MHz, and the initial value is not limited to this value. It is preferable that the initial value is close to the value of the external clock, and the value and the determination method may be determined by any method.

For example, it is possible to calculate a transport stream rate in consideration of overhead for making a transport stream from a bit rate of an elementary stream such as video / audio data, and determine the initial value based on the calculated transport stream rate. Good. When a higher-level controller that controls an MPEG encoder (data multiplexing device) sets a video / audio bit rate for the MPEG encoder, the value may substantially depend on an external clock. Because of the high bit rate, a method of determining the initial value based on these bit rates is effective. In that case, F
Even when the data in the FIFO memory 38 is read, the write control to the FIFO memory 38 can be performed more stably. In this case, a specific method of calculating the initial value may be an arbitrary method.

[0075]

As described above, according to the data transmission apparatus of the present invention, the state of the buffer in the output stage can be properly grasped, and even if the read clock changes, the buffer of the buffer can be appropriately controlled. The data amount can be controlled, and the data packet can be output appropriately. According to the data multiplexing apparatus of the present invention, a transport stream is output in a data multiplexing apparatus that encodes and multiplexes data including video data and audio data according to the MPEG2 system to generate a transport stream. The state of the FIFO can be properly grasped, so that even if the read clock changes, the FIFO can be appropriately controlled according to the change, and an appropriate transport stream can be output.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data multiplexing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a video encoder of the data multiplexing apparatus shown in FIG.

FIG. 3 is a block diagram showing a configuration of an audio encoder of the data multiplexing device shown in FIG.

FIG. 4 is a diagram illustrating a FI in the data multiplexer shown in FIG. 1;
4 is a flowchart illustrating a method of controlling writing of a transport packet to an FO memory.

FIG. 5 is a block diagram illustrating a configuration of a data multiplexing device according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating the FI in the data multiplexer shown in FIG. 5;
4 is a flowchart illustrating a method of controlling writing of a transport packet to an FO memory.

[Explanation of symbols]

2, 2b ... data multiplexing device, 12 ... multiplexing system, 20 ...
Video encoder, 24 ... Audio encoder, 28
... subtitle encoders, 32a, 32b, 32c ...
FIFO memory, 34, 36 switch circuit, 38 F
IFO memory, 40 SCSI IF circuit, 42 control system, 30a, 30b, 30c data amount IF, 420
ENIF circuit, 422 ... SIF circuit, 424 ... CPU,
426: RAM for processing, 428: RAM for control data,
430 ... RAM, 432 ... FIFO remaining amount detector

Claims (15)

[Claims] 1. A packet generating means for sequentially generating a predetermined data packet for transmission from data to be transmitted, and an output signal in which the sequentially generated data packets are sequentially recorded and externally input. Buffer means that is sequentially output based on the following: remaining data amount detection means that detects the amount of remaining data packets recorded in the buffer means that have not yet been output; and the data packets that are sequentially recorded by the buffer means. And buffer recording control means for controlling recording of the data packet in the buffer means based on the amount of the detected remaining data packet and the output signal so that the data packet is sequentially output based on the output signal. Data sending device. 2. The data to be transmitted is arbitrary data including video data and audio data, and the packet generation means determines that each of the data is a high-quality moving image code by MPEG2 (Moving Picture coding Experts Group). 2. The data transmitting apparatus according to claim 1, wherein a transport packet of each data encoded by the encoding method is generated, and an MPEG2 transport stream in which each data is multiplexed is generated. 3. The buffer means sequentially outputs the data packets at a desired data rate on the basis of a clock signal of a predetermined frequency input from the outside. 3. The data transmitting apparatus according to claim 2, wherein recording of said data packet in said buffer means is controlled based on a frequency of a signal. 4. The buffer recording control means compares the detected remaining data packet amount with a predetermined reference data packet amount to determine a difference between the detected data packet amount and the remaining data packet amount. The number of data packets obtained by subtracting the difference from the number of the data packets transmitted from the buffer means within one frame period of the video data is recorded in the buffer means, and when the amount of remaining data packets is small, Controlling the recording of the data packets in the buffer means so as to record the number of data packets obtained by adding the difference to the number of the data packets transmitted from the buffer means in the one frame period in the buffer means; The data transmission device according to claim 3. 5. The data transmitting apparatus according to claim 4, wherein the reference data packet amount is determined in advance based on the data packet amount recordable in the buffer means. 6. The amount of the reference data packet is 1
5. The data transmitting apparatus according to claim 4, wherein the data transmitting apparatus determines in advance based on the number of the data packets transmitted from the buffer means during a frame period. 7. An encoding means for encoding any data to be transmitted including the video data and the audio data according to the MPEG2 system, and any one of the arbitrary data to be transmitted, Based on the encoding rate at the time of the encoding for any multiple types of data or all types of data,
A frequency estimating unit for estimating a frequency of the clock signal input from the outside, wherein the packet generating unit generates the MPEG2 transport packet in which the encoded data is multiplexed, The buffer recording control means performs the control by referring to the estimated frequency of the clock signal as an initial value of the frequency of the clock signal used to control the recording of the data packet in the buffer means. Item 3. The data transmission device according to Item 3. 8. The data transmitting apparatus according to claim 3, wherein said buffer means has a FIFO memory. 9. An arbitrary data to be transmitted including video data and audio data is converted to an MPEG2 format (Mov
encoding means for encoding according to a high-quality moving picture encoding method by the ING Picture Coding Experts Group), and multiplexing the encoded data in a predetermined format to MP
MPE composed of EG2 transport packets
Multiplexing means for generating a G2 transport stream; buffer means for sequentially recording the generated transport packets and sequentially outputting them based on an arbitrary output signal input from the outside; Remaining data amount detection means for detecting the amount of remaining transport packets not yet output, and the transport packets sequentially recorded from the buffer means are sequentially output based on the output signal, A data multiplexing apparatus comprising: a buffer recording control unit that controls recording of the transport packet in the buffer unit based on the detected amount of the remaining transport packet and the output signal. 10. The buffer unit sequentially outputs the transport packets so as to have a desired data rate based on a clock signal of a predetermined frequency input from the outside. 10. The data multiplexing device according to claim 9, wherein recording of said transport packet in said buffer means is controlled based on a frequency of a clock signal. 11. The buffer recording control means compares the detected amount of remaining transport packets with a predetermined reference amount of transport packets and obtains a difference therebetween.
When the amount of the remaining transport packets is large, the number of transport packets obtained by subtracting the difference from the number of the transport packets transmitted from the buffer unit within one frame period of the video data is transmitted to the buffer unit. Recording, and when the amount of the remaining transport packets is small, the number of transport packets, which is obtained by adding the difference to the number of the transport packets transmitted from the buffer means within the one frame period, to the buffer means. 11. The data multiplexing apparatus according to claim 10, wherein recording of said transport packet in said buffer means is controlled to record. 12. The data multiplexing apparatus according to claim 11, wherein said reference transport packet amount is determined in advance based on the transport packet amount recordable in said buffer means. 13. The data multiplexing apparatus according to claim 11, wherein the amount of the reference transport packets is determined in advance based on the number of the transport packets transmitted from the buffer means within one frame period. 14. The method according to claim 1, wherein the external data is selected based on a coding rate at the time of the coding for any one kind of data, arbitrary plural kinds of data or all kinds of data among the arbitrary data to be transmitted. Frequency estimating means for estimating the frequency of the input clock signal, wherein the buffer recording control means controls the recording of the transport packet in the buffer means by controlling the estimated frequency of the clock signal. 12. The data multiplexing device according to claim 11, wherein the control is performed by referring to an initial value of a frequency of the clock signal used for performing the control. 15. The data multiplexing apparatus according to claim 11, wherein said multiplexing means multiplexes, for each frame period of said video data, video data of said period and audio data corresponding to said period.