JPH11225136A - Clock recovery system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock recovery system that relieves the load on CPU and prevents mis arithmetic operations due to updating of a program time reference value PCR and a system time clock STC on the way. SOLUTION: The system consists of a clock generating means 3 that generates a recovered reference clock with a period in response to a control signal, a synchronization information acquisition means 124 that obtains recovery reference synchronization information from the recovered reference clock, an arithmetic means 10 consisting of the hardware that sequentially calculates error information denoting an error of the recovered reference clock with respect to a reference clock based on the reference synchronization information and the recovered reference synchronization information set sequentially with data to be recovered in a packet, and a CPU 16 that sequentially acquires error information via a bus with a bit width smaller than a bit width of the reference synchronization information and a bit width of the recovered reference synchronization information and provides an output of a control signal used to change a period of the recovered reference clock so as to decrease an error indicared by the acquired error information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock reproducing apparatus, and more particularly to a clock reproducing apparatus used for reproducing a reference clock intended on a transmitting side in a decoding / reproducing apparatus used on the receiving side of digital communication.

[0002]

2. Description of the Related Art As one of the methods for compressing moving image data to efficiently transmit video data (image data and audio data) in television broadcasting using digital technology, high-quality digital video / MPEG (Motion), an encoding method for compressing audio signals with high efficiency
MPE proposed by ving Picuture Expert Group)
G2 (international standard ISO / IEC13818-1).

This MPEG2 encoding method (hereinafter referred to as MPE)
In digital communication using G2), the transmitting side separately encodes / compresses video data of a plurality of programs to be transmitted and encodes / compresses image data and audio data in the video data for each program. And the encoded individual streams are further time-division multiplexed into packets composed of a multiplexed stream called a transport stream, and the packets are transmitted via a transmission medium such as a communication satellite. Then, the transmitted packet is received, and the transport stream decoding / reproducing device extracts and decodes image data and audio data for each program from the received packet.

[0004] Then, on the receiving side including the transport stream decoding / reproducing apparatus, image data,
When extracting and decoding audio data, it is necessary to decode them based on the time reference at the time of encoding on the transmission side. For this reason, it is necessary to synchronize the reference clock of the decoding system on the receiving side with the reference clock of the encoding system on the transmitting side.
STC serving as a time reference in the decoding system on the receiving side
A PCR (program time reference value) is included in a packet as information (synchronization information) for setting or calibrating a value of a system time clock (hereinafter referred to as a reproduction reference clock) to a value intended on the transmission side. . This P
CR is represented by a count value of a reference clock on the transmission side.
Therefore, in order to reproduce the reproduction reference clock on the receiving side using the PCR, a frequency (period) corresponding to the control signal is used.
PLL (Phase Locked L) that generates the playback reference clock
oop) and the reproduction reference clock generated in the PLL, and the counted value when the PCR arrives (hereinafter, referred to as
STC value) and S for PCR
Control means for obtaining an error of the TC value and outputting a control signal for reducing the obtained error to control the PLL is provided on the receiving side. In MPEG2, the PL
L and the counter are required to be installed in the transport stream decoding / reproducing apparatus.

FIG. 3 is a block diagram showing a configuration of a calculation means for controlling the frequency of a reproduction reference clock in a conventional transport stream decoding / reproduction apparatus having such a reproduction reference clock reproduction function. (SGS-THOMS
ON Microelectronics limited. ST20-TP2) In the figure, reference numeral 20 denotes a calculating means for controlling the frequency of the reproduction reference clock, and the calculating means 20 is provided by a PCR detecting means (not shown) of the transport stream decoding / reproducing apparatus. The PCR register 11 for storing the transmitted PCR, and the P register transmitted from a counter (not shown).
It has an STC register 12 for storing an STC value at the time when the PCR detected by the CR detection means arrives, and a CPU 16 connected to the PCR register 11 and the STC register 12 via a bus 15. The CPU 16 is connected via a bus 15 to a PLL (not shown) for generating a reproduction reference clock.
It is also connected to other circuits (not shown) of the transport stream decoding / playback apparatus.

In the arithmetic means 20 constructed as described above, the CPU 16 reads the PCR and ST from the PCR register 11 and the STC register 12 according to software.
The C value is read, the difference between the read PCR and the STC value is calculated with respect to the PCR, and a control signal for controlling the frequency of the reproduction reference clock is output to the PLL based on the calculation result. Also, the CPU 16
Performs various operations / controls in the transport stream decoding / reproducing apparatus through the bus 15 in addition to the arithmetic processing required for the frequency control of the reproduction reference clock.

[0007]

However, in the arithmetic means 20 in the above-mentioned conventional transport stream decoding / playback apparatus, the PCR and STC values are MPEG2
Since the bit width of the bus 15 is usually 8 bits or 16 bits, while the CPU 16 performs the arithmetic processing necessary for controlling the frequency of the reproduction reference clock, while the bit width of the bus 15 is normally 8 bits or 16 bits. , These PCR and STC values are stored in the PCR register 11 and the STC register 1
Even reading from 2 requires a plurality of (12 or 6) read cycles, and also requires operations such as subtraction. For this reason, there is a problem that the load on the CPU 16 is large.

Further, as a result of requiring a plurality of read cycles to read the PCR and STC values from the PCR register 11 and the STC register 12, while the CPU 16 is reading the PCR and STC values, P
When the CR arrives at the counter, the PCR register 11
And the STC value of the STC register 12 is updated, and a PCR and an STC value different from the PCR and the STC value to be actually operated are read, and a correct operation result may not be obtained. There was a problem.

The present invention has been made in view of such a problem, and can reduce a load on a CPU.
It is another object of the present invention to provide a clock reproducing apparatus capable of preventing a mistake in a calculation required for frequency control of a reproduction reference clock due to updating of a PCR and an STC value during the operation.

[0010]

A clock reproducing apparatus according to the present invention (claim 1) is a decoding / reproducing apparatus used on the receiving side of digital communication, in which data to be reproduced is sequentially transmitted in packets from the transmitting side. Clock generating means for generating a reference clock having a cycle corresponding to a control signal, which is used for reproducing a reference clock serving as a time reference for reproducing the data, and information corresponding to the cycle of the generated reproduction reference clock. A synchronization information obtaining means for obtaining reproduction reference synchronization information having a certain bit width, and a certain bit width comprising information corresponding to the period of the reference clock transmitted together with the data to be reproduced in the packet and sequentially detected by the decoding and reproduction apparatus. Reference synchronization information, and error information indicating an error of the reproduction reference clock with respect to the reference clock from the obtained reproduction reference synchronization information. A calculating means comprising hardware for sequentially calculating, and the calculated error information is sequentially transferred from the calculating means via a bus having a bit width smaller than the bit width of the reference synchronization information and the bit width of the reproduction reference synchronization information. And a CPU for outputting to the clock generation means a control signal for changing the cycle of the reproduction reference clock so as to reduce the error indicated by the obtained error information.

In the clock recovery apparatus according to the present invention (claim 2), in the clock recovery apparatus (claim 1), the arithmetic means includes: as the error information, a bit width of the reference synchronization information; The CPU has a storage means for calculating a bit having a bit width smaller than the bit width of the synchronization information, and has a storage means for sequentially storing the error information calculated sequentially, and the CPU is sequentially stored in the storage means. By sequentially reading the error information, the error information is obtained from the arithmetic means.

[0012] In the clock recovery device according to the present invention (claim 3), in the clock recovery device (claim 2), the arithmetic means has a bit width not exceeding the bit width of the bus as the error information. It is assumed that a thing is calculated.

In the clock recovery device according to the present invention (claim 4), in the clock recovery device (claim 3), the arithmetic means includes: as the error information, a part indicating the error is represented by a predetermined bit width. It is assumed that an operation having an overflow flag indicating that there is no operation is performed.

According to a fifth aspect of the present invention, there is provided a clock reproducing apparatus according to any one of the first to fourth aspects, wherein the clock reproducing apparatus is a transport stream decoding and reproducing apparatus as the decoding and reproducing apparatus. The synchronization information obtaining means obtains, as the reproduction reference synchronization information, an STC value including a count value of the reproduction reference clock from the reproduction reference clock as an STC; The calculating means is
The error information is calculated from the PCR as the reference synchronization information including the count value of the reference clock detected by the transport stream decoding / reproducing apparatus from the packet and the STC value. It is.

In the clock recovery apparatus according to the present invention (claim 6), in the clock recovery apparatus (claim 5), the calculating means stores the PCR which arrives sequentially so as to be sequentially updated. Means, and STC value storage means for storing the STC value at the time when the PCR arrives so as to be sequentially updated, wherein the PCR stored in the PCR storage means and the STC value stored in the STC value storage means are provided. Information including a difference from the value is calculated as the error information.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram showing an outline of a configuration of a clock recovery device according to Embodiment 1 of the present invention and a configuration of a transport stream decoding / reproduction device using the clock recovery device.

In FIG. 1, reference numeral 1 denotes a transport stream decoding / playback apparatus. The transport stream decoding / reproducing apparatus 1 detects an input terminal 110 for receiving a packet arriving as a continuous bit sequence, and a synchronization bit as identification information of the packet from the bit sequence received at the input terminal 110, and thereby converts the bit sequence for each packet. And a synchronization detection circuit 111 for transmitting the bit string to the clock recovery device together with the detected synchronization bits.
A buffer 113 for temporarily storing packets delimited by the synchronization detection circuit 111, a packet read from the buffer 113, and image data and audio data for each program extracted from the read packet for each program; And a clock reproducing device 2 that reproduces a reproduction reference clock used in a decoding system on the receiving side by using a bit string and a synchronization bit transmitted from the synchronization detection circuit 111. A buffer 115 for temporarily storing the image data extracted by the CPU 16, and decoding the image data stored in the buffer 115 in accordance with the MPEG2 method using the reproduction reference clock reproduced by the clock reproduction device 2, and A video signal decoder 117 as a signal;
The video signal decoded by the video signal decoder 117
NTSC encoder 11 for converting to C television signal
8 and NTSC converted by the NTSC encoder 118
Video signal output terminal 1 for outputting a television signal to the outside
19, a buffer 116 for temporarily storing audio data extracted by the CPU 16, a PLL 129 for converting a reproduction reference clock reproduced by the clock reproduction device 2 to a reproduction reference clock of a predetermined frequency, and a buffer 116 for storing. The audio data is decoded using the reproduction reference clock of a predetermined frequency converted by the PLL 129, and the audio data is converted into an audio signal by the audio signal decoder 120, and the audio signal decoded by the audio signal decoder 120 is converted into an analog audio signal. Audio signal DAC (digital / analog conversion circuit) 1
21 and an audio signal output terminal 122 for outputting an analog audio signal converted by the audio signal DAC 121 to the outside.

Further, the clock reproducing apparatus 2 is transmitted together with a synchronization bit from a clock generation circuit 3 for generating a reproduction reference clock having a frequency corresponding to the reproduction reference clock control signal, and a synchronization detection circuit 111 of the transport stream decoding apparatus. PCR using the synchronization bit from the bit sequence
And a reproduction reference clock generated by the clock generation circuit 3 and outputs an STC value which is a count value of the reproduction reference clock at the time when the PCR detected by the PCR detection circuit 112 is received. The counter 124 and the P detected by the PCR detection circuit 112
Using the CR and the STC value output from the counter 124, a difference between the STC value for the PCR is calculated, and the difference is temporarily stored as error information, and the error information stored in the calculation circuit 10 is calculated. And outputs to the clock generation circuit 3 a reproduction reference clock control signal that reduces the difference between the STC value and the PCR in the error information.
And the CPU 16 which is also a calculation / control device of the transport stream decoding device, which instructs the PCR detection circuit 112 to detect the error. The reproduction reference clock generated by the clock generation circuit 3 is input to the CPU 16 for use in calculation / control by the CPU 16.

The clock generating circuit 3 comprises a PLL. The PLL includes a PWM wave generating circuit 126 for outputting a PWM wave corresponding to a reproduction reference clock control signal output from the CPU 16, and an output from the PWM wave generating circuit 126. LPF (low-pass filter) 127 for smoothing the PWM wave and outputting a DC voltage, and a VCO (voltage controlled oscillator) 128 for generating a reproduction reference clock having a frequency corresponding to the DC voltage output from LPF 127. ing.

FIG. 2 is a block diagram showing a configuration of the arithmetic circuit 10 of the clock recovery device 2 of FIG. In the figure,
The arithmetic circuit 10 includes a PCR register 11 that stores a PCR output from the PCR detection circuit of the clock recovery device;
An STC register 12 for storing an STC value output from a counter of the clock recovery device;
And PC input from STC register 12, respectively.
For the R and STC values, a subtractor 13 configured by hardware for calculating a difference between the STC value and the PCR by subtracting the PCR from the STC value, and the difference calculated by the subtractor 13 is temporarily used as error information 17. And a subtraction result register 14 for storing the result. And this arithmetic circuit 1
0 subtraction result register 14 is connected to CPU 15 via bus 15
16 is connected. Also, the PCR detection circuit 112, the buffer 113, the buffer 115, and the buffer 116 in FIG.
U16 is connected via the bus 15.

The PCR register 11 and the STC
PCR and STC respectively stored in the register 12
While the value has a bit width of 42 bits, the error information 17 stored in the subtraction result register 14
, The 6-bit difference data representing the lower 6 digits of the absolute value of the STC value difference, the 1-bit code flag representing the sign of the STC value difference for the PCR, and the absolute value of the STC value difference for the PCR. It consists of a 1-bit overflow flag indicating whether or not it has exceeded 6 digits (overflow), and has a total bit width of 8 bits. The bit width of the bus 15 is 8 bits in the first embodiment. Therefore, the CPU 16 subtracts the error information 17 from the subtraction result register 14 via the bus 15.
It is possible to read out at once.

Here, in MPEG2, PCR (STC
The bit width of the same value is defined as 6 bytes (48 bits) including the invalid bit, and the actual data which is the count value of the clock is represented by 42 bits. The reason why 42 bits (base 33 + extension 9) is used is that the reference clock used on the transmission side and the reception side is 2 bits.
7 MHz, which is to allow the PCR which is the count value of the reference clock of 27 MHz to represent a range of 24 hours. In contrast, PCR is performed for each program, for example,
It is inserted into the packet at 0.1 second intervals. Therefore, the difference in the count value between the PCRs that arrive before and after the transport stream decoding / reproducing apparatus 1 is P, which corresponds to 24 hours.
It is very small compared to CR,
And ST of the clock recovery device 2 operating in a steady state.
The difference from the C value is also very small as compared with the PCR corresponding to the above 24 hours. Therefore, normally, it is sufficiently possible to represent the difference of the STC value with respect to the PCR with 6 bits without causing an overflow.

Next, the operation of the transport stream decoding device 1 and the clock reproducing device 2 configured as described above will be described with reference to FIGS. In these figures, it is assumed that packets are sequentially arrived at the transport stream decoding / reproducing apparatus 1 in a bit string state, and the clock reproducing apparatus 2 reproduces a reproduction reference clock by the clock generation circuit 3.

In this state, when the input terminal 110 receives the incoming bit string, the synchronization detecting circuit 111 detects a synchronization bit from the received bit string, and separates the bit string into packets to send to the buffer 113. At the same time, the bit sequence is transmitted to the clock reproducing device together with the synchronization bit. The buffer 113 temporarily stores the transmitted packet. Then, the CPU 16
Reads the packets stored in the buffer 113, extracts image data and audio data for each program from the read packets, sends them to the buffers 115 and 116, respectively, and the packets include PCR. If so, it instructs the PCR detection circuit 112 of the clock reproduction device 2 to detect the PCR. The buffer 115 and the buffer 116 temporarily store the transmitted image data and audio data, respectively. Then, the video signal decoder 117 decodes the image data stored in the buffer 115 using the reproduction reference clock reproduced by the clock reproduction device 2 to generate a video signal, and sends the video signal to the NTSC encoder 118. The transmitted video signal is converted by the NTSC encoder 118 into an NTSC television signal, which is output from the video signal output terminal 119 to the outside.

On the other hand, the audio signal decoder 120 decodes the audio data stored in the buffer 116 using a reproduction reference clock of a predetermined frequency converted by the PLL 129 to generate an audio signal, and sends the audio signal to the audio signal DAC 121. . The transmitted audio signal is converted to an audio signal DAC12.
1 converts the analog audio signal into an analog audio signal and outputs the analog audio signal from the audio signal output terminal 122 to the outside.

Next, in the clock reproducing apparatus 2, the PCR detection circuit 112 receives the packet sent from the synchronization detection circuit 111 and only receives a command from the CPU 16 to detect the PCR from the received packet. The PCR is detected, and the detected PCR is sent to the counter 124 of the clock reproducing device and the PCR register 11 of the arithmetic circuit 10, respectively. This transmitted PCR is received, and the PCR register 11
1 is the received PCR.
Is updated to the contents of On the other hand, upon receiving the transmitted PCR, the counter 124 counts the VC of the clock generation circuit 3.
The arithmetic circuit 1 uses the count value at the time when the PCR of the reproduction reference clock input from O128 is received as the STC value.
0 to the STC register 12. This sent S
The TC value is received, and the STC register 12
The contents of the STC value stored in the register 12 are updated to the contents of the received STC value.

The P of the updated PCR register 11
The STC value of the CR and STC register 12 is output to a subtractor 13, which outputs the output PCR and ST.
For the C value, a difference between the STC value and the PCR is calculated, and the difference is used as error information 17 in a subtraction result register 14.
Output to Upon receiving the output error information 17,
In the subtraction result register 14, the content of the error information 17 stored in the subtraction result register 14 is updated to the content of the received error information 17. In addition, CPU
16 is interrupted.

Then, the updated error information 17 is
The CPU 16 reads from the subtraction result register 14 in one read cycle, and outputs a reproduction reference clock control signal to the clock generation circuit 3 based on the read error information 17. At this time, when the control signal that reduces the difference between the STC value and the PCR indicated by the error information 17, that is, when the sign flag of the error information 17 is positive, the pulse width of the PWM wave becomes small, In the case of P
A reproduction reference clock control signal is output such that the pulse width of the WM wave increases and the amount of change in the pulse width of the PWM wave corresponds to the value of the difference data of the error information 17. Even if the CPU 16 reads the error information 17 from the subtraction result register 14 and updates the error information 17 at the same time, the error information 17 is updated.
Can be taken out.

The CPU 16 reads the error information 1
7 indicates that the difference data of the error information 17 has overflowed, the counter 124 is used, for example, when the power is turned on or when the program is switched.
Is initialized by the PCR received at that time, or ignored if the overflow flag does not occur more than once continuously.

Upon receiving the output reproduction reference clock control signal, the clock generation circuit 3 generates a PWM wave
26 changes the pulse width of the PWM wave according to the reproduction reference clock control signal, and the DC voltage output from the LPF 127 changes accordingly. Thereby, VCO12
The cycle of the reproduction reference clock generated in step 8 is changed so that the difference of the STC value with respect to the PCR becomes small, and the cycle of the reproduction reference clock is calibrated so as to match the cycle intended on the transmission side (the cycle of the reference clock). You.

In the above description, the bit width of the error information 17 is set to 8 bits. However, the bit width of the error information 17 can be equal to the bit width of the bus 15 at the maximum. If the bit width of the bus 15 is 16 bits, the bit width of the error information 17 can be up to 16 bits.

In the above description, the difference between the PCR and the STC value at the time when the PCR arrives at the counter 124 is obtained as the error information 17.
CR and any PCR arriving after the arrival of the PCR
May be calculated from the STC value corresponding to.

As described above, in the first embodiment, the difference between the PCR and the STC value is calculated using the subtraction result register 1
4, the error information 17 of 8 bits equal to the bit width of the bus 15 is stored, so that the stored error information 17 can be read by the CPU 16 in one read cycle. Therefore, since the subtraction process is performed only by software, a 42-bit PC
Compared with the conventional example that requires 12 read cycles to read the R and STC values, the load on the CPU is reduced to at least 1/12. Note that this CPU load reduction effect is obtained when the bit width of the bus 15 is 8 bits. In the conventional example, the number of read times is such that the bit width of the bus 15 is relatively smaller than the bit width of the PCR and STC values. Therefore, the effect of the reduction becomes large.

In the first embodiment, the CPU
16 is one read cycle, and the clock generation circuit 3
The error information 17 necessary for controlling the error information 17 can be taken out, so that the data before and after the update is not mixed in the error information 17, and as a result, the PC
By updating the R and STC values, it is possible to prevent erroneous calculations required for controlling the frequency of the reproduction reference clock.

In the first embodiment, since the error information 17 has an overflow flag,
The CPU 16 can detect the error information 17 in which the overflow has occurred and can appropriately process the error information 17, so that the bit width of the error information 17 can be reduced without causing a malfunction. Further, since the overflow flag can be read at the same timing as when the difference data in the error information 17 is read, responsive control becomes possible.

In the first embodiment, the error information 1
Although the difference of the STC value with respect to the PCR is used as 7, the error information 17 may be any information that indicates an error between the reproduction reference clock on the reception side and the reference clock on the transmission side. In this case, if the bit width of the error information 17 is smaller than the bit widths of the reference synchronization information and the reproduction reference synchronization information,
As a result, the processing load on the CPU 16 can be further reduced, and the CPU 16 can read the error information 17 in one read cycle as long as the error width does not exceed the bit width of the bus 15. For example, PCR
Can be used as error information.

In the first embodiment, the synchronization information for synchronizing the transmitting side and the receiving side is defined as MPEG2
, The count values of the reference clock and the reproduction reference clock are used. However, when the present invention is applied to a system other than MPEG2, the synchronization information is proportional to the periods of the reference clock and the reproduction reference clock. Any numerical information may be used as long as the period of the reference clock and the reproduction reference clock is specified as defined in MPEG1.

In the first embodiment, MPEG2
Although the case where the present invention is applied to the clock reproducing device in the encoding method has been described, the present invention is not limited to this, and can be applied to a clock reproducing device in another encoding method. For example, as described above, the present invention is applied to a clock reproducing apparatus using the MPEG1 encoding method by using the reference clock and the period of the reproduction reference clock as the synchronization information as in the first embodiment. can do.

[0039]

As described above, according to the first aspect of the present invention, the CPU that controls the period of the reproduction reference clock calculates the error information of the reproduction reference clock with respect to the reference clock used for the control, and calculates the error information. In a clock recovery device configured to acquire via a bus having a bit width smaller than the bit width of the reference synchronization information used to perform the synchronization and the reproduction reference synchronization information, means for calculating error information is configured by hardware. Therefore, when compared with the case where the CPU reads the reference synchronization information and the reproduction reference synchronization information and calculates the error information by software as in the conventional example, the CPU can read only the calculated error information. As a result, not only the calculation load is reduced, but also the load for reading out information for controlling the reproduction reference clock is reduced by at least half. At this time, as the bit width of the reference synchronization information and the reproduction reference synchronization information is larger than the bit width of the bus, the number of times of reading in the conventional example is increased, so that the absolute amount of the load reduced by half becomes large. Therefore, when the bit widths of the reference synchronization information and the reproduction reference synchronization information are larger than the bit width of the bus, it is possible to provide a clock reproducing apparatus that can obtain a large CPU load reduction effect.

According to the invention of claim 2, according to claim 1,
In the invention, the error information is calculated with a bit width smaller than the bit widths of the reference synchronization information and the reproduction reference synchronization information. Therefore, the number of times required to read the error information is reduced, and accordingly, The burden on the CPU can be further reduced.

According to the invention of claim 3, according to claim 2,
According to the invention, the error information having a bit width not exceeding the bus bit width is calculated, so that the error information can be read out at one time, and the load on the CPU can be further reduced. . Further, as a result of reading the error information at one time, data before and after the update is not mixed in the error information. As a result,
By updating the reference synchronization information and the reproduction reference synchronization information during the reading, it is possible to prevent the calculation necessary for controlling the frequency of the reproduction reference clock from being erroneously performed.

According to the invention of claim 4, according to claim 3,
In the invention of the present invention, the information having an overflow flag is calculated as the error information, so that the CPU can detect the error information that caused the overflow and appropriately process the error information. The bit width can be reduced. Further, since the overflow flag can be read at the same timing as when the difference data in the error information is read, responsive control becomes possible.

According to the invention of claim 5, according to claim 1,
In any one of the inventions according to any one of (4) to (4), when used in a transport stream decoding / reproducing apparatus, an STC value is obtained from a reproduction reference clock as STC as reproduction reference synchronization information, and a PCR is used as reference synchronization information.
Error information is calculated from the STC value and the
Normally, the bit width of the bus is up to about 16 bits, whereas the bit width of the PCR and STC values is 42 bits. Therefore, it is possible to support MPEG2 which can reduce the load on the CPU according to the bit width of the bus. It is possible to provide a simple clock reproducing device.

According to the invention of claim 6, according to claim 5,
In the invention of the above, a PCR storage means for storing the sequentially arriving PCRs so as to be sequentially updated and an STC value storage means for storing the STC values at the time when the PCR arrives so as to be sequentially updated are provided. PCR stored in storage means and STC stored in STC value storage means
Since the information including the difference from the value is calculated as error information, the PCR and STC values are only changed in the lower bits when the error of the reproduction reference clock with respect to the reference clock is small in the bit width of 42 bits. Because of this, it is possible to reduce the bit width of the error information, and as a result, it is possible to provide a clock reproducing apparatus that is compatible with MPEG2 and that can further reduce the load on the CPU.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a clock reproduction device according to a first embodiment of the present invention and a transport stream decoding / reproduction device using the clock reproduction device.

FIG. 2 is a block diagram illustrating a configuration of an arithmetic circuit of the clock recovery device of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a calculating means for controlling a frequency of a reproduction reference clock in a conventional transport stream decoding and reproducing apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transport stream decoding / reproduction apparatus 2 Clock reproduction apparatus 3 Clock generation circuit 10 Operation circuit 11 PCR register 12 STC register 13 Subtractor 14 Subtraction result register 15 Bus 16 CPU 17 Error information 20 Operation means 110 Input terminal 111 Synchronization detection circuit 112 PCR Detection circuit 113, 115, 116 Buffer 117 Video signal decoder 118 NTSC encoder 119 Video signal output terminal 120 Audio signal decoder 121 Audio signal DAC 122 Audio signal output terminal 124 Counter 126 PWM wave generation circuit 127 LPF 128 VCO 129 PLL

Claims (6)

[Claims] 1. A decoding / reproducing apparatus used on the receiving side of digital communication, which is used for reproducing a reference clock serving as a time reference for reproducing data to be reproduced sequentially transmitted in packets from the transmitting side. A clock generating means for generating a reproduction reference clock having a cycle corresponding to the control signal; a synchronization information obtaining means for obtaining reproduction reference synchronization information having a bit width composed of information corresponding to the cycle of the generated reproduction reference clock; Reference synchronization information of a certain bit width including information corresponding to the cycle of the reference clock, which is transmitted together with data to be reproduced in a packet and sequentially detected by the decoding / reproducing device,
And calculating means comprising hardware for sequentially calculating error information indicating an error of the reproduction reference clock with respect to the reference clock from the obtained reproduction reference synchronization information, and calculating the calculated error information by using the bit width of the reference synchronization information,
And sequentially obtained from the arithmetic means via a bus having a bit width smaller than the bit width of the reproduction reference synchronization information,
A clock reproducing apparatus comprising: a CPU that outputs a control signal for changing a cycle of the reproduction reference clock to the clock generation means so that an error indicated by the obtained error information is reduced. 2. The clock recovery apparatus according to claim 1, wherein said arithmetic means has a bit width of said reference synchronization information and a bit width smaller than a bit width of said reproduction reference synchronization information as said error information. , And
And a storage unit for sequentially storing the sequentially calculated error information. The CPU acquires the error information from the calculation unit by sequentially reading the error information sequentially stored in the storage unit. A clock recovery device, characterized in that: 3. The clock recovery apparatus according to claim 2, wherein said calculating means calculates, as said error information, a signal having a bit width not exceeding a bit width of said bus. Clock regeneration device. 4. The clock recovery device according to claim 3, wherein said arithmetic means calculates the error information having an overflow flag indicating that a portion indicating the error cannot be represented by a predetermined bit width. A clock recovery device characterized in that: 5. The clock reproducing device according to claim 1, wherein the clock reproducing device is used in a transport stream decoding / reproducing device as the decoding / reproducing device, and the synchronization information acquiring device includes: Means for obtaining, from the reproduction reference clock as STC, an STC value including a count value of the reproduction reference clock as the reproduction reference synchronization information; and the arithmetic means for decoding the transport stream from the packet. A PC as the reference synchronization information including a count value of the reference clock detected by the playback device;
A clock reproducing apparatus for calculating the error information from R and the STC value. 6. The clock recovery apparatus according to claim 5, wherein the arithmetic means stores the sequentially arriving PCRs so as to be sequentially updated, and the PCR storage means.
STC value storage means for storing the STC value at the time of arrival in such a way that the STC value is sequentially updated, and stores a difference between the PCR stored in the PCR storage means and the STC value stored in the STC value storage means. A clock regenerating device for calculating included information as the error information.