JP2000041265A - Reciprocation deflection video signal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for a high voltage flyback pulse by using a reciprocal deflection type horizontal deflection output circuit, to reduce a power loss of a switching element, to adopt a low breakdown voltage switching element or the like, and to obtain a reciprocation deflection video signal display device that eliminates uneven density of a scanning line caused at both ends of a screen without adding newly a large scale circuit such as an auxiliary deflection waveform generating means and an auxiliary deflection yoke. SOLUTION: The display device is provided with a scanning conversion means 113 that converts video image scanning of a received video signal from rester scanning into reciprocating scanning, a reciprocating horizontal deflection output means 122 that generates a reciprocating horizontal deflection waveform, a vertical deflection output means 123 that generates a vertical deflection waveform, a horizontal deflection means 143 that is driven by a reciprocating horizontal deflection waveform, a vertical deflection means 142 that is driven by a vertical deflection waveform, to realize a reciprocating scanning of video scanning in the reciprocating deflection video signal display device. It is also provided with a video scanning position fine-adjustment means 130 that corrects color slurring on a screen emitted by red, green, blue electron beams and the scanning position of the scanning line on the screen and that corrects minutely a scanning position of the scanning line on the screen and that fine-adjusts the video image scanning position.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reciprocating deflection type video signal display device and, more particularly, to a video signal display device suitable for displaying high-definition video information and performing video scanning by reciprocating horizontal deflection.

[0002]

2. Description of the Related Art In recent years, image quality has been improved with the enlargement of television screens. As means for improving the image quality of a television, means for converting a conventional interlaced scanning image into a progressive scanning image and displaying the image is often used. When the number of scanning lines is doubled by the above processing, the horizontal scanning frequency is changed from 15.73 kHz of the conventional video to 31.5 kHz. Further, high-definition horizontal scanning is required for high-definition televisions and displays that display images of personal computers that are currently under consideration. In general, as the horizontal scanning frequency increases, the current consumption of the electromagnetic deflection type horizontal deflection output circuit increases.
Further, there are problems such as the necessity of a switching element capable of withstanding the high voltage of the flyback pulse generated during the horizontal retrace period, and the inability to reduce power loss when the switching element is cut off.

As a method for solving the above-mentioned problem associated with the increase in the horizontal scanning frequency, a reciprocating deflection type video signal display device in which horizontal video scanning is performed in a reciprocating manner is disclosed in Japanese Patent Laid-Open No. 8-17.
No. 2543. As described in this publication, the use of the high-voltage flyback pulse can be eliminated by using a reciprocating deflection type horizontal deflection output circuit. Further, the switching element having a low withstand voltage can be used, and the power loss in the switching element can be further reduced.

[0004] However, the reciprocating deflection type video signal display device having such an advantage, if the horizontal deflection is simply changed to the reciprocating deflection type, as described in FIG. At both ends of the screen, the scanning lines become uneven every two lines. In the above publication, the density of scanning lines generated at both ends of the screen is eliminated by performing vertical deflection control using a stepwise vertical deflection waveform. That is, in addition to the existing vertical deflection waveform generating means, a separate auxiliary deflection waveform generating means is prepared to obtain the stepwise vertical deflection waveform,
Further, vertical deflection control of the electron beam is performed by an existing vertical deflection yoke and an auxiliary deflection yoke prepared separately, thereby eliminating the density of scanning lines generated at both ends of the screen. That is, in this prior art, it was necessary to separately prepare an auxiliary deflection waveform generating means and an auxiliary deflection yoke.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the need for a high-voltage flyback pulse, to reduce the power loss of a switching element, and to realize a low breakdown voltage switching element by using a reciprocating deflection type horizontal deflection output circuit. In addition to realizing the adoption and the like, it is possible to generate at both ends of the screen in the reciprocating deflection type video signal display device without separately preparing a large-scale new additional circuit such as the auxiliary deflection waveform generating means and the auxiliary deflection yoke described in the prior art. An object of the present invention is to provide a device for eliminating the density of scanning lines.

[0006]

SUMMARY OF THE INVENTION The present invention provides a scan conversion means for converting a video scan of an input video signal from a raster scan to a reciprocal scan, a reciprocal horizontal deflection output means for generating a reciprocal horizontal deflection waveform, A vertical deflection output means for generating a vertical deflection waveform, a horizontal deflection means driven by the reciprocating horizontal deflection waveform, and a vertical deflection means driven by the vertical deflection waveform; In the reciprocating deflection type video signal display device to be realized, the color misregistration of each of the red, green and blue electron beams on the screen is corrected, and the scanning position of the scanning line on the screen is minutely corrected, and the video scanning position is adjusted. This is a reciprocating deflection type video signal display device including a video scanning position fine adjustment means for performing fine adjustment.

Further, in the present invention, the image scanning position fine adjustment means includes a convergence correction waveform generating means for generating a convergence correction waveform for correcting a color shift of each of the red, green and blue electron beams on the screen; Auxiliary deflection waveform generating means for generating an auxiliary deflection waveform for fine correction of a scanning position on a screen; adding means for adding the convergence correction waveform and the auxiliary deflection waveform to generate a superimposed waveform; And a convergence means driven by a reciprocating deflection type video signal display device.

The present invention is the reciprocating deflection type video signal display device wherein the video scanning position fine adjustment means is program-controlled.

Further, the present invention is a reciprocating deflection type video signal display device which is a CRT projection type projection television.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described. Embodiments of the present invention will be described with reference to the drawings. The reciprocating deflection type video signal display device described in this embodiment is a projection television. In addition to horizontal deflection and reciprocal processing of video scanning, the NTSC interlacing scanning type used in the current TV system is used for the horizontal scanning line number. The following description will be made on the assumption that double-speed scanning line conversion processing for converting from 262.5 lines to 525 lines in the sequential scanning method is also performed at the same time.

FIG. 1 is a block diagram illustrating an embodiment of a reciprocating deflection type video signal display device. The reciprocating deflection type video signal display device of the present embodiment includes an input terminal 101 for inputting a video signal of the current NTSC system, a tuner 102 for demodulating a video signal input from the input terminal 101, selecting a channel, and the like. Y / C separation circuit 11 for separating the output composite video signal into a luminance signal and a chroma signal
1. A color demodulation circuit 112 for demodulating two kinds of color difference signals from a chroma signal, a scan conversion circuit 113 for converting a luminance signal and a color difference signal from a raster scan for scanning in the same direction to a reciprocating scan, and a luminance signal and a color difference signal. Matrix conversion circuit 114, amplifier 115, tuner 102 for converting into primary color signals of red (R), green (G), and blue (B)
The horizontal synchronization signal (H) and the vertical synchronization signal (V) are extracted from the composite video signal output from the
, A horizontal deflection circuit 122 for generating a reciprocating horizontal deflection waveform, a vertical deflection circuit 123 for generating a vertical deflection waveform, and a digital convergence circuit 13
A convergence correction waveform generating circuit 131 for generating a convergence correction waveform for correcting color shift of each primary color signal of 0, RGB on the screen, and an auxiliary deflection waveform for eliminating the density of scanning lines generated at both ends of the screen. Auxiliary deflection circuit 132 for generating, convergence correction waveform generation circuit 131
The first, second, and third adders 133 to 1 add the convergence correction waveforms for the RGB primary color signals generated in step (1) and the auxiliary deflection waveform generated in the auxiliary deflection circuit 132, respectively.
35, projection tubes 141, 151, 1 for RGB primary color signals
61, vertical deflection coil 14 for RGB primary color signal projection tube
2, 152, 162, horizontal deflection coils 143, 153, 163 for RGB primary color signal projection tubes, convergence coils 144, 154, 16 for RGB primary color signal projection tubes
4 is provided. The convergence correction waveform generation circuit 131 is a convergence correction waveform generation unit that generates a convergence correction waveform for correcting a color shift of each of the red, green, and blue electron beams on the screen. Auxiliary deflection circuit 13
Reference numeral 2 denotes an auxiliary deflection waveform generating means for generating an auxiliary deflection waveform for finely correcting the scanning position of the scanning line on the screen. The first, second and third adders 133 to 135 are adding means for adding the convergence correction waveform and the auxiliary deflection waveform to generate a superimposed waveform. The convergence coils 144, 154, and 164 for the RGB primary color signal projection tubes are convergence means driven by a superimposed waveform.

A television broadcast wave input to an input terminal 101 of the reciprocating deflection type video signal display device of the present embodiment via a television broadcast receiving antenna (not shown) is received, demodulated, and selected by a tuner 102. Each processing of the station is performed and output as a composite video signal. The composite video signal output from the tuner 102 is input to a Y / C separation circuit 111 and a synchronization separation circuit 121, and is subjected to Y / C separation processing and synchronization separation processing, respectively. The Y / C separation circuit 111 converts the input composite video signal into a luminance signal Y and a chroma signal C.
And the luminance signal Y is supplied to the scan conversion circuit 113,
The chroma signal C is output to the color demodulation circuit 112, respectively. The color demodulation circuit 112 demodulates two types of color difference signals (RY) and (BY) from the input chroma signal C,
The two types of color difference signals are output to the scan conversion circuit 113.

The scanning conversion circuit 113 converts the number of horizontal scanning lines from 262.5 lines in the NTSC interlaced scanning system to 525 lines in the sequential scanning system, as well as a double-speed scanning line conversion process. A conversion process from a raster scan of a video signal scan to a reciprocal scan necessary for the process is performed.

An example of the operation of the scan conversion circuit 113 will be described with reference to FIGS. FIG. 2 is an example of a detailed block diagram of the scan conversion circuit 113. The scan conversion circuit 113 includes an input terminal 201 for the horizontal synchronization signal H,
Input terminals 202 to 204 for inputting the luminance signal Y and the color difference signals (RY) and (BY) output from the Y / C separation circuit 111 and the color demodulation circuit 112, respectively, and subjected to the scan conversion processing. A luminance signal Y2 and a color difference signal (RY) 2,
(BY) Output terminals 205 to 20 for outputting 2 respectively
7, Y signal scan conversion circuit 210, (RY) signal scan conversion circuit 220, (BY) signal scan conversion circuit 230, A / D converter 2 for converting an analog signal into digital data
11. first and second memories 212 and 213 capable of storing digital video data for at least one horizontal scanning period;
A selector 214, a D / A converter 215 for converting digital data into an analog signal, a counter 241 reset by the horizontal synchronizing signal H input from the input terminal 201, and capable of performing a count-up operation for at least one horizontal scanning period, 241 and the memories 212 and 2
13, a write control circuit 24 for controlling the write operation
2. First and second according to the count value of the counter 241
And a read control circuit 243 for controlling the read operation of the memories 212 and 213.

Note that the Y signal scan conversion circuit 210 and (R-
Since the Y) signal scanning conversion circuit 220 and the (BY) signal scanning conversion circuit 230 perform the same operation with the same configuration,
A description of the (RY) signal scanning conversion circuit 220 and the (BY) signal scanning conversion circuit 230 will be omitted, and only the operation of the Y signal scanning conversion circuit 210 will be described below.

The luminance signal Y output from the Y / C separation circuit 111 shown in FIG.
The data is converted into digital data by the converter 211. In this embodiment, this digital sampling is performed with a 14.3 MHz clock. Input terminal 2
The analog video signal for one horizontal scanning period inputted from 02 is converted into digital video data of 910 samples,
It is supplied to the input ports of the first and second memories 212 and 213.

Although not shown in the figure, the digital signal processing section of the main scan conversion circuit 113 basically has a 28.
It is assumed that it is operating with a 6 MHz basic clock. 14.3, which is the operation clock of the above-mentioned A / D converter.
The MHz clock can be obtained by dividing the basic clock by two.

The counter 241 is reset in synchronization with the falling edge (or rising edge) of the horizontal synchronizing signal H input from the input terminal 201, and thereafter counts up in synchronization with the basic clock and writes and controls the count value. The data is output to the circuit 242 and the read control circuit 243. Write control circuit 242 and read control circuit 24
3 decodes the count value of the counter 241 and writes the write address signal W.3. ADR, write enable signal W
EA, WEB, and the read address signal R.E. ADR,
Generate read permission signals REA and REB.

The first and second memories 212 and 213
The control signal generated by the write control circuit 242 and the read control circuit 243, that is, the write address signal W. AD
R, write enable signals WEA, WEB, and read address signal R.R. ADR, read permission signals REA, REB
And reading and writing of data is performed according to. Further, by the data selection processing of the selector 214, it is possible to obtain the video data subjected to the scan conversion processing.

An example of the data write and read operations of the first and second memories 212 and 213 will be described with reference to FIG. FIG. 3 shows the first and second memories 21 shown in FIG.
FIGS. 2A and 2B are diagrams for explaining write and read operations, wherein a signal 301 is a horizontal synchronizing signal H input from an input terminal 201 in FIG. The signal 311 is shown in FIG.
Is the luminance signal data output from the A / D converter 211 of FIG. The signal 312 is a write address signal W. output from the write control circuit 242 of FIG. ADR. Signal 3
13, 314 are first and second memories 212, respectively;
213 are write enable signals WEA and WEB, and it is assumed that writing to the memory is enabled when each is at the H level. The signal 321 is output from the selector 214 in FIG. 2 and is luminance signal data that has been subjected to double-speed scanning line conversion processing and conversion processing to reciprocal scanning in the main scanning conversion circuit. The signal 322 is the read address signal R.R. output from the read control circuit 243 of FIG. ADR
It is. The signals 323 and 324 are read permission signals REA and RE of the first and second memories 212 and 213, respectively.
B, and it is assumed that reading from the memory is permitted when each is at the H level.

In this embodiment, of the 910 samples of digitally sampled video data for one horizontal scanning period, only 768 samples including effective display data are read / written from / to the memory.

First, an example of a video data write operation will be described. The video data 311 (A) of 768 samples for the first one horizontal scanning period includes the write address signal W. In response to the ADR and the write enable signal WEA, the first
From address 000h (0) of memory 212 to 2FFh (7
67) sequentially written to addresses; For the next one horizontal scan period,
The video data 311 (B) of 768 samples is composed of the write address signal W. In response to the ADR and the write enable signal WEB, the data is sequentially written from the address 000h (0) to the address 2FFh (767) of the second memory 213. Thereafter, the video data of 768 samples is alternately written to the first memory 212 and the second memory 213 every one horizontal scanning period. Note that data is written using a 14.3 MHz clock obtained by dividing the basic clock 28.6 MHz by 2, or writing the same data twice to the same address using the basic clock. Just do it.

On the other hand, in the operation of reading video data, basically, data is read from one of the first and second memories 212 and 213 to which data is not written. It operates to read the contents stored in the memory twice each during one horizontal scanning period. That is, the video data 31 is stored in the second memory 213.
1 (B) is written, the read address signal R. According to the ADR and the read permission signal REA,
The video data stored in the first memory 212 is read twice. At this time, the read address signal R. As shown by the signal 322 in FIG. 3, the ADR operates in the order of addresses 000h (0) to 2FFh (767) in the first read operation, and 2FFh in the second read operation.
The operation is performed in the order from address (767) to address 000h (0). As a result, the video data 321 (A) and 321 (A)
(A)-can be obtained. The video data 321
Although (A) and 321 (A)-have the same contents,
(A) is a scanning line for scanning from left to right on the screen, and 321 (A)
− Is a scanning line that scans from the right to the left of the screen.

The selector 214 shown in FIG.
A data selection operation is performed by a signal obtained by dividing the horizontal synchronization signal H input from 1 into two.

With the above processing, the Y signal scan conversion circuit 2
In step 10, double speed scanning line conversion processing for converting the number of horizontal scanning lines from 262.5 lines in the NTSC interlaced scanning method to 525 lines in the sequential scanning method, and video signal scanning required for the reciprocating horizontal deflection processing of the present embodiment. The conversion process from raster scan to reciprocal scan can be realized at the same time.

In FIG. 3, the period 350 can be arbitrarily set depending on the system design. This period 350
By shortening the PRT display,
The time for which the electron beam excites the phosphor per unit time can be lengthened, and the luminance can be improved as compared with a unidirectional scanning system that performs video scanning by raster scanning.

In the apparatus of this embodiment, as described above,
In the scan conversion circuit 113, the number of horizontal scanning lines is reduced from 262.5 to 52 in addition to the conversion processing from raster scan to reciprocal scan of video signal scanning required for reciprocal horizontal deflection processing.
Double-speed scanning line conversion processing for conversion into five lines is performed. This double-speed scanning line conversion processing is not always necessary for the reciprocating deflection type video signal display device of the present embodiment, but by performing the above processing, in addition to the effects obtained in the present embodiment, When used as a multimedia television that can also display a VGA screen, a new effect can be obtained. That is, by the above processing, the horizontal and vertical scanning frequencies are equal between the case of displaying the NTSC video and the case of displaying the VGA screen of the personal computer, and an inexpensive single scan deflection circuit can be used.

In the scan conversion circuit 113 of this embodiment shown in FIG. 2, the (RY) signal scan conversion circuits 220 and (B) also correspond to the color difference signals (RY) and (BY), respectively. BY) A signal scan conversion circuit 230 is prepared, and scan conversion is realized by performing the same processing as described above. However, since the color difference signal generally has a narrower frequency band than the luminance signal, the scan conversion is performed. As an example of the circuit 113, which is different from the example illustrated in FIG. 2, a circuit illustrated in FIG. 10 may be used.

The scan conversion circuit 113 shown in FIG. 10 converts the color difference signals (RY) and (BY) input from the color difference signal scan conversion circuit 250 and the input terminals 203 and 204 from analog signals to digital data. A / D converter 221,
231, memories 252 and 253 having the same capacity as the memories 212 and 213 in FIG.
54, multiplexing circuit 255, separating circuit 256, D / A converters 225 and 23 for converting digital data into analog signals
5 mag. In addition, components having the same numbers as those in FIG. 2 perform the same operations as those in FIG.

The color difference signals (RY) and (BY) input from the input terminals 203 and 204 in FIG.
28.6 MHz basic clock with D converters 221 and 231
Is digitally sampled at 7.2 MHz, and time-division multiplexed by the multiplexing circuit 255. Less than,
By performing the same memory processing as described above, FIG.
The double-speed scanning line conversion processing for converting the number of horizontal scanning lines from 262.5 lines in the NTSC interlacing scanning method to 525 lines in the sequential scanning method as in the case of the scanning conversion circuit 113 having the configuration shown in FIG. The conversion process from the raster scan of the video signal scan required for the horizontal deflection process to the reciprocal scan can be realized.

The configuration of the scan conversion circuit 113 shown in FIG. 10 requires the addition of a multiplexing circuit 255 and a separation circuit 256, but has the advantage that the number of memories can be reduced as compared with the configuration shown in FIG. . Further, there is an advantage that the A / D converters 221 and 231 and the D / A converters 225 and 235 for color difference signals can be operated at a low speed.

The luminance signal Y2 and the chrominance signal (R) output after being subjected to scan conversion processing by the scan conversion circuit 113 of FIG.
-Y) 2 and (BY) 2 are the matrix conversion circuits 1
At 14, the signals are converted into RGB primary color signals, and supplied to the projection tubes 141, 151, 161 via the amplifier 115.

The composite video signal output from the tuner 102 is input to the Y / C separation circuit 111 and to the synchronization separation circuit 121 at the same time. Sync separation circuit 121
In addition to the detection of the horizontal synchronizing signal H and the vertical synchronizing signal V, the basic clock 28.6 MHz for generating the double-speed horizontal synchronizing signal H2, the determination signal (O / E), and the operation of the digital signal processing unit
Is generated.

FIG. 4 shows an example of a detailed block diagram of the sync separation circuit 121. The sync separation circuit 121 is connected to the input terminal 40 of the composite video signal output from the tuner 102 in FIG.
1, horizontal synchronization signal H output terminal 402, horizontal synchronization signal H
The output terminal 403 of the double-speed horizontal synchronizing signal H2, the output terminal 404 of the vertical synchronizing signal V, the output terminal 405 of the discrimination signal (O / E), and the basic clock of the operation of the digital signal processing unit (this embodiment) The output terminal 406 outputs 28.6 MHz in the example). However, in FIG. 1 and FIG. 2, the description of the signal line through which the basic clock propagates and the input terminal is omitted. Also, the sync detection circuit 41
1. Double speed conversion circuit 412 for horizontal synchronization signal H, frequency divider 41
3, a PLL 414, and an oscillator 415.

The composite video signal input from the input terminal 401 shown in the figure is first input to the sync detection circuit 411, where the horizontal synchronizing signal H and the vertical synchronizing signal V are detected. This is because a synchronization signal including an equalization pulse can be extracted by comparing the input composite video signal with a signal of a predetermined voltage, so that the detection of the horizontal synchronization signal H and the vertical synchronization signal V can be detected from the extracted synchronization signal. For example, a method of performing such operations may be used. The horizontal synchronization signal H and the vertical synchronization signal V detected by the sync detection circuit 411 are output from output terminals 402 and 404, respectively, as shown in FIG.
Are output to the scan conversion circuit 113 and the vertical deflection circuit 123.

Further, the horizontal synchronizing signal H is supplied to the double speed conversion circuit 4.
1 and a double-speed horizontal synchronizing signal H2 corresponding to a video signal which has been double-speed scanned by the scan conversion circuit 113 in FIG.
Is generated. The generated double-speed horizontal synchronizing signal H2 is output from the output terminal 403, is input to the horizontal deflection circuit 122, is also input to the frequency divider 413, and is provided with the discrimination signal (O
/ E) is generated. The determination signal (O / E) may be generated by dividing the frequency of the double-speed horizontal synchronization signal H2 using a D flip-flop or the like.

The discrimination signal (O / E) is supplied to the scan conversion circuit 11
3 is a signal for discriminating between odd-numbered scanning lines and even-numbered scanning lines of the video signal subjected to the double-speed scanning line conversion processing,
Further, the signal is a signal for discriminating a scanning line scanned from the left to the right of the screen and a scanning line scanned from the right to the left of the image of the video signal which has been subjected to the conversion processing from the raster scan to the reciprocal scan of the video signal scanning. .

The horizontal synchronizing signal H, the double-speed horizontal synchronizing signal H
FIG. 5 shows an example of the output timing of the decision signal 2 and the determination signal (O / E). In the figure, a signal 501 is a horizontal synchronizing signal H, a signal 502 is a double speed horizontal synchronizing signal H2, and a signal 503 is a discrimination signal (O / E). And operate synchronously. Further, the signal 511 corresponds to the scan conversion circuit 11 of FIG.
The signal 521 is a luminance signal Y2 that has been subjected to scan conversion processing and is output from the scan conversion circuit 113.

In this embodiment, the discrimination signal (O / E) becomes L level during the period of the luminance signal output Y2 521 (A) and 521 (B), and the luminance signal output Y2 521 (A) −,
It is set to the H level during the period of 521 (B)-.

The horizontal synchronization signal H output from the sync detection circuit 411 is further input to one input terminal of the PLL 414. An oscillator 4 is connected to the other input terminal of the PLL 414.
The clock of 28.6 MHz output from 15 is input. The 28.6 MHz clock output from the oscillator 415 is frequency-divided by 1820, and the phase of the clock is compared with the horizontal synchronization signal H output from the sync detection circuit 411.
28.6 MHz, which is a basic clock for the operation of the digital signal processing unit of the apparatus, is generated. The generated basic clock is output from an output terminal 406 and is supplied to a digital signal processing unit of the scan conversion circuit 113, although not shown.

The horizontal deflection circuit 122 shown in FIG. 1 receives the double-speed horizontal synchronization signal H2 output from the synchronization separation circuit 121 and generates a reciprocating horizontal deflection waveform. FIG. 6 illustrates the double-speed horizontal synchronizing signal H2, the determination signal (O / E), and the generated reciprocating horizontal deflection waveform H2Def. In the figure, a signal 601 is a double-speed horizontal synchronization signal H2 input to the horizontal deflection circuit 122, a signal 602 is a discrimination signal (O / E), and a signal 603 is a reciprocating horizontal deflection waveform used in the apparatus of the present embodiment. H2Def. In addition, a horizontal deflection waveform H2Def ′ in the case of performing the horizontal deflection of the raster scan method is illustrated as a reference to the signal 613. The reciprocating horizontal deflection waveform H2Def of the signal 603 is the same as the horizontal deflection coil 1 shown in FIG.
43, waveforms of currents supplied to 153, 163,
This current causes the horizontal deflection coils 143, 153, 16
3 is driven to control the horizontal deflection of the electron beam of each of the RGB primary color signals.

The circuit for generating the reciprocating horizontal deflection waveform H2Def is disclosed in the above-mentioned Japanese Patent Laid-Open Publication No. Hei 8-172543.
The reciprocal horizontal deflection waveform H2 may be the same as the circuit described in Japanese Patent Application Laid-Open Publication No.
By realizing reciprocating horizontal deflection using Def,
As in the apparatus disclosed in the above publication, it is possible to obtain the effects of eliminating the need for a high-voltage flyback pulse, reducing the power loss of the switching element, and employing a low-voltage switching element.

On the other hand, the vertical deflection circuit 123 receives the vertical synchronization signal V output from the synchronization separation circuit 121 and generates a vertical deflection waveform VDef. This vertical deflection waveform VD
ef is the vertical deflection coils 142, 152, 162 of FIG.
The vertical deflection coils 142, 152, and 162 are driven by the current to control the vertical deflection of the electron beams of the RGB primary color signals. Also,
The circuit for generating the vertical deflection waveform VDef used in this embodiment is as follows.
The same circuit as that generally used at present may be used.

FIG. 7 shows the scanning trajectory of the electron beam on the television screen by the reciprocating horizontal deflection waveform H2Def and the vertical deflection waveform VDef obtained by the apparatus of this embodiment. In the figure, a signal 701 is a vertical deflection waveform VDef output from the vertical deflection circuit 123, a signal 702 is a discrimination signal (O / E), and a signal 703 is a reciprocating horizontal deflection waveform output from the horizontal deflection circuit 122. H2Def, and the signal 704 is a scanning trajectory of the electron beam on the television screen.

As can be seen from the scanning locus 704 in FIG.
If the horizontal deflection is simply performed in a reciprocating manner, the scanning trajectory of the electron beam on the television screen becomes zigzag, and the image quality is deteriorated due to the density of the scanning lines at both ends of the screen. In this embodiment, the density of the scanning lines at both ends of the screen is corrected and eliminated by using the digital convergence circuit 130 shown in FIG.

A process for correcting the density of scanning lines at both ends of the screen using the digital convergence circuit 130 will be described. The projection television described in this embodiment has 3
A color image is obtained by enlarging each primary color image of RGB displayed on the projection tubes 141, 151, and 161 of the book with a lens and combining them on a screen. The images displayed by the three projection tubes are left as they are in FIG.
A color shift occurs as shown in FIG. In order to correct this color shift, each of the projection tubes 141, 151, 161 includes a vertical deflection coil 142, 152, 162, a horizontal deflection coil 1,
43, 153 and 163, the convergence coil 1
44, 154 and 164 are mounted. By applying a correction current to the convergence coils 144, 154, 164, an image in which color misregistration is corrected as shown in FIG. 8B is obtained.

The convergence coil 144 described above,
A convergence correction waveform generation circuit generates a current to be applied to 154 and 164, that is, a convergence correction waveform. Generally, a digital circuit capable of generating an arbitrary waveform is used for the convergence correction waveform generation circuit in terms of correction accuracy and the like. This digital convergence correction waveform generation circuit detects the amount of color misregistration of each of the RGB primary color images on the screen using an optical sensor or the like, calculates the optimum correction amount using a microcomputer or the like, and generates an optimum correction waveform. By driving the convergence coils 144, 154, and 164, the color shift on the screen is corrected.

In the apparatus of this embodiment, the above processing is performed by the convergence correction waveform generation circuit 131 in the digital convergence circuit 130 shown in FIG. In addition,
In the figure, illustrations of an optical sensor for detecting the amount of color misregistration, a microcomputer for calculating a correction amount and the like and performing program control are omitted.

The digital convergence circuit 130 of the apparatus of this embodiment further includes an auxiliary deflection circuit 132 and an adder 1
33, 134, and 135. The discrimination signal (O / E) output from the synchronization separation circuit 121 is input to the auxiliary deflection circuit 132, and the microcomputer generates an auxiliary deflection waveform for correcting the density of the scanning lines at both ends of the screen, and performs convergence. Performs superimposition processing on the correction waveform.

FIG. 7 shows an example of the auxiliary deflection waveform 711 generated by the auxiliary deflection circuit 132. In the apparatus of this embodiment, the vertical deflection coil 1 shown in FIG.
42, 152 and 162 are driven, and the convergence coils 144 and 1 in FIG.
54 and 164 are driven, and the vertical deflection of the electron beam is controlled (however, the color shift correction by the convergence correction waveform is ignored). This means that the superimposed waveform 7
12 is equivalent to controlling the vertical deflection of the electron beam by driving the vertical deflection coils 142, 152, 162, and therefore the trajectory of the electron beam on the television screen is
714. As a result, it is possible to eliminate the density of the scanning lines at both ends of the screen which is generated when the reciprocating horizontal deflection circuit is employed.

The generation of the auxiliary deflection waveform described above is as follows.
By inputting the determination signal (O / E) to the microcomputer of the digital convergence circuit 130 in FIG. 1, it is possible to perform the program control simultaneously with the calculation of the convergence correction amount. Further, by adding the calculated convergence correction amount and the auxiliary deflection correction amount in the microcomputer, it becomes unnecessary to add a new circuit for generating the auxiliary deflection waveform. The existing convergence coil is also used for minute correction of the scanning locus of the electron beam.

By using the video signal display device of the present embodiment described above, the use of a reciprocating deflection type horizontal deflection output circuit eliminates the need for a high-voltage flyback pulse, reduces power loss of a switching element, and reduces power consumption. It is possible to employ a withstand voltage switching element or the like, and it is possible to eliminate the density of scanning lines generated at both ends of the screen of the reciprocating deflection type video signal display device without requiring a large-scale new additional circuit.

The auxiliary deflection waveform shown as the signal 711 in FIG. 7 is an example used in the above description, and is not limited to this waveform. For example, an auxiliary deflection waveform as shown by a signal 1211 in FIG. 12 may be used. In this case, the locus of the electron beam on the television screen is the scanning locus 1214 in FIG.
It becomes like. Even in this case, all the effects described above can be similarly obtained.

The scanning trajectory 714 of the electron beam on the television screen shown in FIG. 7 shows the scanning lines (A) and (A).
-, (B) and (B)-, etc. have a difference in the scanning direction,
The same scanning line is used as a picture. That is, scanning locus 7
In FIG. 14, two scanning lines of the same picture are displayed on the television screen. This scanning trajectory 714 causes deterioration of the vertical resolution when the screen size of the television becomes larger than a certain size.

A reciprocating deflection type video signal display device for preventing the deterioration of the vertical resolution will be described below as a second embodiment. In order to prevent the deterioration of the vertical resolution, the auxiliary deflection waveform generated by the auxiliary deflection circuit 132 in FIG. 1 may be a waveform 911 as shown in FIG. By using the auxiliary deflection waveform 911, the scanning trajectory of the electron beam on the screen becomes 91
As shown in FIG. That is, since the scanning lines of the same pattern scan the same position, deterioration of the vertical resolution of the image can be prevented.

Even when the auxiliary deflection waveform 911 shown in FIG. 9 is employed, the effect of the present embodiment, that is, the need for a high-voltage flyback pulse using a reciprocating deflection type horizontal deflection output circuit is eliminated and switching is performed. Reduction of power loss of elements, adoption of low withstand voltage switching elements, etc., and elimination of coarse and dense scanning lines generated at both ends of the screen of a reciprocating deflection type video signal display device without requiring a large-scale new circuit addition. The effect is obtained equally.

Incidentally, in the first and second embodiments described above,
In the scan conversion circuit 113 of FIG.
As a process for converting from 262.5 lines in the TSC interlaced scanning system to 525 lines in the sequential scanning system, a double-speed scanning line conversion process of displaying the same scanning line twice is performed. A scanning line complementing process for generating a line may be performed. When performing the scan line complementing process, the scan conversion circuit 113 needs at least a memory capable of storing video data for one frame, a motion detection circuit, and the like. Video is obtained. When the scan line complementing process is performed in the scan conversion circuit 113, the waveform 7 shown in FIG.
11 and the waveform 1211 shown in FIG. In this case, the locus of the electron beam on the television screen is like the locus 714 shown in FIG. 7 or the locus 1214 shown in FIG.

In the first and second embodiments described above, the scan conversion circuit 113 shown in FIG. 1 uses a horizontal scanning line in addition to the conversion process from the raster scan to the reciprocal scan of the video signal scan necessary for the reciprocal horizontal deflection process. Although the double-speed scanning line conversion processing for converting the number from 262.5 lines in the NTSC interlaced scanning method to 525 lines in the sequential scanning method is performed, an apparatus having a configuration that does not perform the double-speed scanning line conversion processing according to the present embodiment. It is possible to get an effect.

A video signal display device in which the double-speed scanning line conversion processing is not performed will be described below as a third embodiment.
When the double-speed scanning line conversion processing is not performed, the memory operation in the scanning conversion circuit 113 in FIG. 1 is as shown in FIG.

In FIG. 11, signals 301 and 311-
314 is the same as the signal of the same number shown in FIG. A signal 331 is luminance signal data output from the selector 214 in FIG. 2 and subjected to conversion processing to reciprocal scanning in the main scan conversion circuit. A signal 332 is output from the read control circuit 243 in FIG. Read address signal R. It is ADR, and signals 333 and 334 are read permission signals REA and REB of the first and second memories 212 and 213, respectively, and reading from the memories is permitted when the signals are at H level. The writing operation of the video data is the same as that described with reference to FIG.

On the other hand, in the operation of reading video data, basically, data is read from one of the first and second memories 212 and 213 to which data is not written. Is the same as in FIG. That is, the video data 311 is stored in the second memory 213.
(B) is written, the read address signal R.D. The video data stored in the first memory 212 is read according to the ADR and the read permission signal REA. At this time, in this embodiment, the read address signal R.
The ADR counts up from address 000h (0) to address 2FFh (767) every one horizontal scanning period and 00 from address 2FFh (767) as shown at 332 in FIG.
The countdown to the address 0h (0) is performed alternately.

In this embodiment, the data reading is the same as the basic clock, like the data writing.
A 14.3 MHz clock obtained by dividing 6 MHz by 2 is used, or data of the same address is read out twice by using the above basic clock.

By the above-described processing, in the scan conversion circuit 113, the conversion processing from the raster scan to the reciprocal scan of the video signal scan required for the reciprocal horizontal deflection processing of the present embodiment can be realized.

When the above-mentioned memory operation is employed, the double-speed horizontal synchronizing signal H2 described in the first and second embodiments is used.
Is not necessary, and the horizontal synchronization signal H is supplied as a substitute to the horizontal deflection circuit 122 that requires the double-speed horizontal synchronization signal H2. It is necessary to operate the circuit by preparing a signal having a period twice as long as the waveform shown in FIG. 6 and the like for the determination signal (O / E), the reciprocating horizontal deflection waveform H2Def, and the like.

With the above configuration, the use of a reciprocating deflection type horizontal deflection output circuit eliminates the need for a high-voltage flyback pulse, reduces the power loss of the switching element, employs a low withstand voltage switching element, and realizes a large scale. It is possible to obtain effects such as elimination of unevenness of scanning lines generated at both ends of the screen of the reciprocating deflection type video signal display device without adding a new circuit.

[0066]

According to the present invention, an auxiliary digital deflection circuit is generated by using an existing digital convergence circuit, and a minute correction of vertical deflection control is performed by using an existing convergence coil. It is possible to eliminate the density of the scanning lines at both ends of the screen caused by the reciprocating horizontal deflection circuit without adding a circuit. Further, in the device of the present invention, the need for a high-voltage flyback pulse, which is obtained by a conventional reciprocating deflection type video signal display device,
It is possible to obtain a reciprocating deflection type video signal display device without reducing the power loss of the switching element, realizing the adoption of the low withstand voltage switching element, and the like.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a reciprocating deflection type video signal display device according to a first embodiment.

FIG. 2 is an explanatory block diagram of the scan conversion circuit of FIG. 1;

FIG. 3 is an explanatory diagram of an example of a timing such as data writing to the memory in FIG. 2;

FIG. 4 is an explanatory block diagram of an example of a sync separation circuit of FIG. 1;

5 is an explanatory diagram of an example of a horizontal synchronization signal H and the like output from the synchronization separation circuit in FIG. 4;

FIG. 6 is an explanatory diagram of an example of a double-speed horizontal synchronization signal H2 and the like input to the horizontal deflection circuit of FIG. 1;

FIG. 7 is an explanatory diagram of an example of a horizontal deflection waveform H2Def and the like output from the horizontal deflection circuit of FIG. 1;

FIG. 8 is an explanatory diagram of a color shift or the like that occurs in a projection television.

9 is an explanatory diagram of an example of a horizontal deflection waveform H2Def and the like output from the horizontal deflection circuit of FIG. 1;

10 is an explanatory diagram of an example of the configuration of the scan conversion circuit in FIG. 1 which is different from FIG. 2;

FIG. 11 is an explanatory diagram of data writing and the like in the memory of FIG. 2;

FIG. 12 is an explanatory diagram of an example of a horizontal deflection waveform H2Def and the like output from the horizontal deflection circuit of FIG. 1;

[Description of Code] 111 Y / C separation circuit 112 Color demodulation circuit 113 Scan conversion circuit 114 Matrix conversion circuit 121 Synchronous separation circuit 122 Horizontal deflection circuit 123 Vertical deflection circuit 130 Digital convergence circuit 131 Convergence correction waveform generation circuit 132 Auxiliary deflection circuit 133 , 134, 135 Adders 141, 151, 161 Projection tubes 142, 152, 162 Vertical deflection coil 143, 153, 163 Horizontal deflection coil 144, 154, 164 Convergence coil 701 Vertical deflection waveform 702 Discrimination signal 703 Reciprocating horizontal deflection waveform 711 Auxiliary deflection waveform 714 Operation track of electron beam

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Toshimitsu Watanabe 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Multimedia Systems Development Division of Hitachi, Ltd. (72) Inventor Masahisa Tsukahara Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa 292 Hitachi Image Information System Co., Ltd. (72) Inventor Kunori Matsumi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa F-term (Reference) 5C060 AA06 BB13 BC05 BD02 BD06 BE02 BE07 CE01 CG01 CG08 GB02 HB24 HB26 5C068 AA01 BA02 BA11 BA30 KA11 LA13 LA15 MA03

Claims (4)

[Claims] 1. A scan conversion means for converting a video scan of an input video signal from a raster scan to a reciprocal scan, a reciprocal horizontal deflection output means for generating a reciprocal horizontal deflection waveform, and a vertical deflection for generating a vertical deflection waveform. Output means, horizontal deflection means driven by the reciprocating horizontal deflection waveform, and vertical deflection means driven by the vertical deflection waveform,
In a reciprocating deflection type video signal display device that realizes reciprocal scanning of video scanning, it corrects the color shift of each red, green, blue electron beam on the screen and finely corrects the scanning position of the scanning line on the screen. A reciprocating deflection type video signal display device comprising a video scanning position fine adjustment means for finely adjusting the video scanning position. 2. A reciprocating deflection type video signal display device according to claim 1, wherein said video scanning position fine adjustment means generates a convergence correction waveform for correcting a color shift of each of red, green and blue electron beams on a screen. Convergence correction waveform generation means, auxiliary deflection waveform generation means for generating an auxiliary deflection waveform for finely correcting the scanning position of the scanning line on the screen, and a superposition waveform by adding the convergence correction waveform and the auxiliary deflection waveform , And a convergence means driven by the superimposed waveform. 3. The reciprocating deflection type video signal display device according to claim 1, wherein said video scanning position fine adjustment means is program-controlled. 4. The reciprocating deflection type video signal display device according to claim 1, wherein said reciprocating deflection type video signal display device is a CRT projection type projection television.