JPH0614217A - Moire canceling circuit - Google Patents

Abstract

PURPOSE:To reduce a moire phenomenon due to the interference of the signal pattern of a picture and the shadow mask pitch of a CRT. CONSTITUTION:A display device including a synchronism separator circuit 2, video circuit 3, CRT 4 and deflection circuit 5 is equipped with a moire canceling circuit 8. Position data indicating the horizontal scanning start position of each of plural blocks in a frame are stored in a memory 9. When a vertical synchronizing signal is inputted from the synchronism separator circuit 2 to a memory control part 10, respective position data are read from the memory 9 corresponding to each horizontal synchronizing signal and applied to a D/A converter 11. Then, the D/A converter 11 outputs a voltage signal whose scanning start position is shifted to the deflection circuit 5. The deflection circuit 5 generates a deflection current by the pertinent voltage signal and applies it to a deflection coil 6. Thus, the picture having high quality in which the moire interference is reduced can be outputted from the CRT 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moiré canceling circuit for reducing an image moiré phenomenon in a display device using a cathode ray tube (hereinafter referred to as CRT).

[0002]

2. Description of the Related Art A raster scan type display device used in a television receiver or a computer displays an image by repeatedly scanning the electron beam in the horizontal direction and moving the scan line in the vertical direction. In a display device using a CRT, the pitch of the shadow mask determines the dot pitch of phosphors that emit light in the video signal. Therefore, for example, when an on / off luminance signal is applied to each dot in the horizontal direction (such a pattern is
The pitch of the image display pattern and the pitch of the shadow mask of the CRT cause mutual interference, and a moire phenomenon occurs in the image.

In order to reduce such a moire phenomenon,
In the conventional display device, the following methods have been used in combination. (1) By changing the size of the image display area,
The pattern pitch of the image displayed on the CRT is changed to reduce mutual interference with the shadow mask. (2) By changing the pitch of the shadow mask,
Mutual interference between the shadow mask and the image display pattern is reduced. (3) The focus of the electron beam is deteriorated and the size of one dot of the image display pattern is increased. Then,
The contrast of mutual interference becomes small, and the moire phenomenon becomes inconspicuous.

[0004]

However, the conventional method as described above has the following problems. (1) With the method of changing the size of the display area of the image, it is difficult to determine the size of the display area for each image each time. (2) Changing the pitch of the shadow mask changes the design of the CRT including the shadow mask, which itself requires a considerable development period and development cost. (3) With the method of deteriorating the focus and increasing the spot size, it is difficult to reduce the moire phenomenon and maintain a predetermined resolution.

In recent years, display monitors are required to have various horizontal frequencies and vertical frequencies due to higher resolution and diversification. In such a multi-scan display device, it is impossible to reduce the moire phenomenon for all images and to eliminate the problem in practical use by the method described above. Further, the shadow mask pitch of the CRT is different between the center of the screen and the periphery of the screen, and even if the entire screen is uniformly corrected, it is difficult to reduce the uniform moire phenomenon on the entire screen.

The present invention has been made in view of the above-mentioned problems of the prior art, and is a moiré canceller capable of reducing the moiré phenomenon in all operation modes and minimizing deterioration of image resolution. The purpose is to provide a circuit.

[0007]

SUMMARY OF THE INVENTION The present invention provides a sync separation circuit for separating a vertical and horizontal sync signal from a video signal, a sawtooth wave signal in response to a periodic signal and its start timing signal, and deflection of a cathode ray tube. A moiré canceling circuit that is used in a display device having a deflection circuit that outputs a deflection current to a coil and reduces a moiré phenomenon of an image caused by interference between a pattern of an image signal and a pitch of a shadow mask of a cathode ray tube. A non-volatile memory that stores data indicating the horizontal scanning start position or time for each horizontal scanning period, a memory control unit that reads the data in the memory for each horizontal scanning period, and a horizontal scanning output by the memory control unit A D / A converter that converts data indicating a start position or time into a voltage signal and outputs the voltage signal to the deflection circuit as a timing signal. Is shall.

[0008]

According to the present invention having such a feature, the sync separation circuit separates the vertical and horizontal sync signals from the video signal input to the display device, and supplies these signals to the memory control section. Then, the memory control unit reads the data indicating the horizontal scanning start position or time from the non-volatile memory in synchronization with the synchronization signal for each horizontal scanning period. D / A
The converter converts the data in the memory into a voltage signal and outputs the signal to the deflection circuit. The deflection circuit controls the generation start time by the voltage signal, generates a sawtooth wave current, and gives the deflection current to the deflection coil. By doing so, the moire phenomenon of the image caused by the interference between the pattern of the image signal and the pitch of the shadow mask of the cathode ray tube can be reduced.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A moire cancel circuit for a display device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a display device including a moire cancel circuit. 2 is an explanatory view of a display screen showing the operation of the moire cancel circuit of this embodiment.

In the display device shown in FIG. 1, an input terminal 1 is a terminal to which a video signal including R, G and B luminance signals is input, and is connected to a sync separation circuit 2 and a video circuit 3. The sync separation circuit 2 is a circuit for separating the horizontal and vertical sync signals from the video signal. The video circuit 3 includes an image amplification circuit and outputs the R, G, B luminance signals to the CRT 4. The deflection circuit 5 is a circuit that generates vertical and horizontal deflection currents based on the vertical and horizontal synchronization signals output from the sync separation circuit 2 and outputs the currents to the deflection coil 6. The deflection circuit 5 includes a horizontal deflection circuit (not shown) and a phase shifter 7 for a horizontal synchronizing signal, and generates a sawtooth wave current necessary for deflection. In the deflection circuit 5,
The signal at the scanning start position of the video signal including the dot signal is input by the moire cancel circuit described later.

Now, the display device has a moire canceling circuit 8
Is provided. The moire cancel circuit 8 includes a memory 9, a memory control unit 10, and a D / A converter 11, and outputs a scanning start position signal of each horizontal scanning line in one frame of a video signal to the deflection circuit 5. The memory 9 is composed of, for example, a nonvolatile memory such as an EEPROM, and stores first position data and second position data described later.

As shown in FIG. 2, one frame of the CRT 4 is divided into a plurality of scanning blocks if scanning is performed with non-interlace. For example, 1 frame is 10
It is composed of 24 lines, and it is 1st-8th along the vertical scanning direction.
It is divided into 8 blocks. That is, each block is 1
It consists of 28 horizontal scan lines. Here, the first screen position B1 indicated by a dotted line indicates the position of an odd-numbered horizontal scanning line included in the first block. The first screen position B2 indicates the position of the odd-numbered horizontal scanning line included in the second block. Similarly, the first screen positions B3 to B8
Indicates the positions of odd-numbered horizontal scanning lines in the third to eighth blocks, respectively. The scan start positions of the screen positions B1 to B8 are shifted, and the scan start position data of the screen positions B1 to B8 are set to the first position data D1 to D8, respectively.

The second screen position C shown by the solid line in FIG. 2 is the position of all even-numbered horizontal scanning lines in one frame. That is, the screen position C is the second, fourth ...
It is assumed that 24-line signals are output as video signals from a fixed time different from the initial position of one frame.
This time is stored in the memory 9 as the second position data D0. The scanning start time of each of the screen positions B1 to B8 is set in accordance with the characteristics of the image pattern and the shadow mask output on the CRT 4, and these data are stored in the memory 9.

The memory control unit 10 is a circuit that includes a microcomputer, counts the number of horizontal synchronizing signals in each vertical synchronizing period, and reads out desired position data from the memory 9 in each horizontal scanning period. Next, the D / A converter 11
Is a circuit for converting the data of the memory 9 output from the memory control unit 10 into an analog signal. D / A converter 1
The output of 1 is output to the phase shifter 7 in the deflection circuit 5.

In the moiré cancel circuit 8 having the above-described structure, when the display device starts operating, the input terminal 1
The video signal is input to. The sync separation circuit 2 separates the vertical and horizontal sync signals from this video signal and supplies them to the memory controller 10. The memory control unit 10 resets the address of the memory 9 with the vertical synchronizing signal and reads the first position data D1 in the memory 9. When the signal of the first horizontal scanning line L1 is input to the video circuit 3, the memory control unit 10 gives horizontal position information corresponding to time t ₁ to the D / A converter 11 as shown in FIG. The D / A converter 11 converts this position data into an analog voltage and gives it to the deflection circuit 5. Then, the phase shifter 7 in the deflection circuit 5
However, the phase of the horizontal synchronizing signal is delayed by the input position signal, and the horizontal deflection current is generated from time t ₁ .

Next, when the signal of the second horizontal scanning line L2 is input, the memory control unit 10 causes the second memory of the memory 9 to receive the second signal.
Position data D0 is read and horizontal position information is given to the D / A converter 11. At this time, the D / A converter 11 outputs a voltage signal corresponding to time t ₀ in FIG. 2 to the deflection circuit 5. Then, the deflection circuit 5 generates a horizontal deflection current from time t ₀ .

Similarly, the third horizontal scanning line L3
When the signal of 1 is input, the signal of the first position data D1 is read. Further, when the signal of the fourth horizontal scanning line L4 is input, the second position data D0 is read. In this way, the reading from the first position data D1 and the second position data D0 is alternately performed, and the signal processing is continued until the 128th horizontal scanning line.

Next, with respect to the second block, each position data is similarly read out. That is, from the 129th to the 256th
In the th horizontal scanning line, the first position data D2 and the second position data D0 stored in the memory 9 are alternately read, so that the D / A converter 11 causes the deflection circuit 5 to read.
Output a signal to. Then, the deflection circuit 5 applies a desired sawtooth wave deflection current to the deflection coil 6. Thus, 128
The memory control unit 10 reads out the necessary position data information for each horizontal scanning line, and the video signal output from the video circuit 3 is displayed on the CRT 4.

The number of dots in the horizontal scanning direction is 1280, for example.
When the scanning start positions of the screen positions B1 to B8 are delayed by a predetermined time, the 1280-dot signals are all output with the same delay. Moreover, FIG.
Start time t ₁ ~t ₈ horizontal scan shown in is determined based on the type of video signal applied to CRT4 its characteristics or the display device. If the 1-dot cycle of the video signal is T, the time
It is sufficient that the maximum delay time from T ₀ is T / 2.

By such an operation, the display position of each horizontal scan is shifted to the left and right relative to each horizontal synchronizing signal. Therefore, the phase of the image display pattern and the interference wave of the shadow mask of the CRT 4 are deviated between the odd-numbered scanning lines and the even-numbered scanning lines. That is, the contrast due to the moire phenomenon becomes weak, and a delicate image is faithfully output on the display screen.

In the multi-scan type display device,
With respect to various display modes (when the frame frequency and the number of scanning lines are different from each other), the first position data and the second position data are stored in the memory 9 for each mode so that the moire phenomenon is minimized. Then, the optimum image is always displayed on the CRT 4.

[0022]

As described in detail above, according to the present invention, the data indicating each horizontal scanning start position is stored in the memory, so that the video signal of each horizontal scanning is shifted from the horizontal synchronizing signal by a predetermined pitch. Can be output. Therefore, the dot pitch of the video signal and the pitch of the shadow mask of the cathode ray tube will shift regardless of the type of display image,
It is possible to reduce the image moire phenomenon without lowering the image resolution. Therefore, an effect that a high quality image can be displayed is produced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a display device including a moire cancel circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a display screen showing the operation of the moire cancel circuit in the present embodiment.

[Explanation of symbols]

 1 Input Terminal of Video Signal 2 Sync Separation Circuit 3 Video Circuit 4 CRT 5 Deflection Circuit 6 Deflection Coil 7 Phase Shifter 8 Moire Cancel Circuit 9 Memory 10 Memory Controller 11 D / A Converter B1 to B8 First Screen Position C No. 2 screen position

Claims (2)

[Claims] 1. A sync separation circuit for separating vertical and horizontal sync signals from a video signal, a sawtooth wave signal is generated according to a periodic signal and its start timing signal, and a deflection current is output to a deflection coil of a cathode ray tube. A moiré canceling circuit used in a display device having a deflection circuit for reducing a moiré phenomenon of an image caused by interference between a pattern of an image signal and a pitch of a shadow mask of the cathode ray tube, in each horizontal scanning period. A non-volatile memory that stores data indicating a horizontal scanning start position or time, a memory control unit that reads the data in the memory for each horizontal scanning period, and a horizontal scanning start position that the memory control unit outputs A D / A converter which converts data indicating time into a voltage signal and outputs the voltage signal to the deflection circuit as a timing signal. Moire cancel circuit. 2. The memory stores first position data for storing data indicating an odd-numbered horizontal scanning start position in a frame for each block obtained by equally dividing the frame into a plurality of scanning lines, and data in the frame. 2. The moire cancel circuit according to claim 1, further comprising: second position data that stores data indicating even-numbered horizontal scanning start positions.