JP2637221B2 - Digital convergence correction device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a convergence correction device in a television receiver or a display using a cathode ray tube, and in particular, to a reduction in the memory capacity of a memory for storing convergence correction data. The present invention relates to a digital convergence correction device capable of achieving cost reduction.

[Conventional technology]

As disclosed in Japanese Patent Publication No. 56-40355, a digital convergence correction device capable of performing convergence correction with high accuracy uses a digital convergence correction amount required at each point on a screen as convergence correction data in a memory in a digital format. The convergence correction data is read out in synchronization with the raster scan in the cathode ray tube, and the convergence correction data is converted into an analog signal to obtain a convergence correction signal, whereby the convergence correction of the electron beam is performed. The convergence correction amount required for each point (convergence correction point) on the screen that requires convergence correction can be determined independently, and a convergence correction signal having a desired waveform can be easily obtained. be able to.

Hereinafter, the conventional digital convergence correction device will be described in detail to the necessary extent with reference to FIG.

In FIG. 2, reference numerals 1 and 2 denote input terminals for inputting a horizontal blanking pulse H.BLK and a vertical blanking pulse V.BLK in synchronization with a raster scan in a cathode ray tube (not shown).

3 is PLL (Phase Locked Loop), 4,5
Are an H address counter and a V address counter for designating an H address and a V address as read addresses of the memory 6 described later.

6 is a memory for storing convergence correction data, 7 is a digital / analog converter (DAC), 8 is a low-pass filter (LPF) for interpolating a signal, and 9 is an amplifier (AM) for driving a convergence yoke 10 described later.
P) and 10 are convergence yokes (CY) for generating a convergence magnetic field.

Now, the output of PLL3 is the horizontal deflection frequency from input terminal 1.
synchronized in phase with the horizontal blanking pulse H.BLK with f _H,
And shall clock having a frequency obtained by multiplying the f _H is generated.

The H address counter 4 counts the output of PLL3,
An H address signal designating a read address in the memory 6 is generated. The V address counter 5 counts the clock of the H cycle from the H address counter 4 and designates a V address as a read address in the memory 6 by using a vertical blanking pulse from the input terminal 2 as a reset pulse. V address signal to be generated. As a result, the convergence correction data stored in the memory 6 is stored in a cathode ray tube (not shown).
Is read out in synchronization with the raster scan.

The read convergence correction data is converted from a digital signal to an analog signal by a digital-to-analog converter 7, and then a convergence yoke 10 is driven via a low-pass filter 8 and an amplifier 9 to perform convergence correction.

When the above digital convergence correction device is used in a television receiver or the like that performs interlaced scanning, the display positions of the scanning lines on the cathode ray tube differ between even and odd fields. It is necessary to have separate convergence correction data for each.

However, if separate convergence correction data is provided for each field, the memory capacity for storing the convergence correction data is doubled, and a field discriminating unit is required, resulting in an increase in cost. For this reason, in the conventional digital convergence correction device, the correction is performed using the same convergence correction data for each field, using the approximate name of the convergence correction amount of the even field and the odd field.

[Problems to be solved by the invention]

In the prior art, when the amount of raster correction by the digital convergence correction device is large, the convergence correction amount of the even field and the odd field is the same, so that the convergence correction amount in the vertical direction on the screen becomes discontinuous, There was a problem that raster unevenness occurred. Here, raster unevenness refers to a state in which the intervals between scanning lines are uneven.

Hereinafter, the cause of raster unevenness will be described in detail with reference to the drawings.

FIG. 3 is a characteristic diagram showing the amount of convergence correction for each scanning line on the screen. The horizontal axis represents scanning lines sequentially numbered from the top of the screen, and the vertical axis represents a certain vertical line assumed on the screen. And the convergence correction amount in the vertical direction at the point where the scanning lines shown on the horizontal axis intersect.

In the figure, in the even field, the scanning line number is the convergence correction amount of the even number (indicated by (A) in the figure), and in the odd field, the scanning line number is the odd number of the convergence correction amount (the point (a) in the figure). Output (C) (C) or (D) (D)).

That is, in the even fields (scan lines 0, 2, 4, 6, ...), the corresponding convergence correction amounts are stored, so that they are output as indicated by the circles, but the odd fields (scan lines 1, 3, 5,...) Do not store the corresponding convergence correction amounts, so that, for example,
Then, the convergence correction amount (○) of the scanning line 6 of the even field adjacent to the right is set as □ (印), or the convergence correction amount (○) of the scanning line 4 of the even field adjacent to the left is set as △. This is output as a mark (c).

FIG. 4 is an explanatory diagram in which the state of the raster on the screen after the convergence correction is partially enlarged.

The convergence correction amount corresponding to the scanning line of the odd field is also stored, and when the convergence correction is strictly performed, the convergence correction amount of FIG. 3A for the even field and the convergence correction amount of FIG. Output. In this case, since the convergence correction amount changes smoothly from the top of the screen to the bottom, the scanning line displayed on the screen is the fourth line.
As shown in FIG. 7A, the scanning lines (A) of the even-numbered fields and the scanning lines (A) of the odd-numbered fields are arranged at equal intervals, and no raster unevenness occurs.

However, as described above, in order to reduce the memory capacity, only the convergence correction amount of the even field is stored in the memory, and that of the odd field is not stored. To output the convergence correction amount of the even field on one scanning line (FIG. 3 (c)) or the correction amount of the even field below one scanning line (FIG. 3 (d)) instead of FIG. become.

In this case, since the convergence correction amount is discontinuous from the top to the bottom of the screen, the scanning lines displayed on the screen are as shown in FIG. 4 (b) or (c). ) And scanning lines (c) or (d) in the odd-numbered fields are uneven, and raster unevenness occurs.

When the amount of raster correction by the digital convergence correction device becomes large, this raster unevenness causes a problem in terms of image quality deterioration.

In order to halve the memory capacity during sequential scanning, similar convergence correction data is stored for every other scanning line, and the same raster unevenness occurs when convergence correction is performed using the same convergence correction data for two horizontal periods. There was a problem that occurred.

An object of the present invention is to use a memory storing the convergence correction data of one field at the time of interlaced scanning, or to use a memory storing the convergence correction data at every other scanning line at the time of sequential scanning. It is another object of the present invention to provide a digital convergence correction apparatus that does not cause raster unevenness.

[Means for solving the problem]

In the present application for achieving the above object, the following means are employed as respective inventions.

(1) Scanning lines on a cathode ray tube screen are divided into two types of scanning lines at odd-numbered positions and scanning lines at even-numbered positions in view of a display position, and one of them is a first scanning line group and the other is a second scanning line group. And the convergence correction data relating to the first scanning line group is stored in the digital memory. When the first scanning line group is scanned, the convergence correction data is read from the digital memory as it is. When the second scanning line group is scanned, the scanning line adjacent to the one scanning line belonging to the second scanning line group in the first scanning line group during the one scanning period. And the lower adjacent scanning line, and the convergence correction data of the upper adjacent scanning line and the convergence correction data of the lower adjacent scanning line are alternately read from the digital memory and used during the one scanning period. Caught.

(2) When scanning the second scanning line group, the second scanning line group is used for the second scanning line group in the first scanning line group in the one scanning period every other frame.
The convergence correction data of the upper adjacent scanning line and the convergence correction data of the lower adjacent scanning line among the upper scanning line and the lower scanning line of the one scanning line belonging to the one scanning line group are stored in a digital memory. , And alternately read from them.

(3) When scanning the second scanning line group, in the one scanning period, the scanning line adjacent to and above the one scanning line belonging to the second scanning line group in the first scanning line group. Among the adjacent scanning lines, the convergence correction data of the upper adjacent scanning line and the convergence correction data of the lower adjacent scanning line are read out from the digital memory, the average value thereof is calculated, and the average value is used.

(4) The scanning lines on the cathode ray tube screen are divided into two types of scanning lines at odd-numbered positions and scanning lines at even-numbered positions in view of the display position, one of which is a first scanning line group and the other is a second scanning line group. The convergence correction data of the first scanning line group alone is stored in the digital memory, and the difference between the convergence correction data of the second scanning line group and that of the first scanning line group is rasterized. A raster non-uniformity correction signal generation circuit that outputs as a non-uniformity correction signal is prepared, and when the second scanning line group is scanned, the correction signal output from the raster non-uniformity correction signal generation circuit is added by an adding unit. .

(5) The scanning lines on the cathode ray tube screen are divided into two types of scanning lines at odd-numbered positions and scanning lines at even-numbered positions in view of the display position, and one of them is a first scanning line group and the other is a second scanning line group. When only the convergence correction data of the first scanning line group is stored in the digital memory, and when the convergence correction data is read out from the digital memory and used as the convergence correction output, the amplitude is set to the first convergence correction output. An amplitude control means for controlling and outputting differently when scanning the scanning line group and when scanning the second scanning line group is provided.

[Action]

 The operation will be described according to the numbers of the respective means.

(1) Since the convergence correction data of the upper adjacent scanning line and the convergence correction data of the lower adjacent scanning line are alternately used during the one scanning period, the convergence correction data is visually recognized as if the average correction data is used. And the raster unevenness is visually reduced.

(2) Since the convergence correction data of the upper adjacent scanning line and that of the lower adjacent scanning line are alternately used at one frame interval,
Although flicker may be a problem, it is effective in a display or the like using a long persistence phosphor.

(3) Since the convergence correction data of the upper adjacent scanning line and the average value of the convergence correction data of the lower adjacent scanning line are calculated and used, raster unevenness can be actually reduced, not visually.

(4) Since the correction signal output from the raster unevenness correction signal generation circuit is added, the raster unevenness can be actually reduced, not visually.

(5) When the convergence correction data is read out from the digital memory and output as convergence correction data, the amplitude of the convergence correction data is set higher in the first scanning line group when viewed from the second scanning line group when scanning the second scanning line group. Since the amplitude control means controls the convergence correction signal of the scanning line at the adjacent position and the value of the convergence correction signal of the scanning line at the lower adjacent position to be approximately the intermediate value, the raster unevenness is actually reduced, not visually. be able to.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, the same elements as those in FIG. 2 (that is, 1 to 10) are denoted by the same reference numerals as those in FIG. In addition, reference numeral 11 denotes an H address counter 4 and a V blanking pulse input terminal 2.
This is a field discriminating unit that fetches a signal from the field and performs a field even / odd discrimination, and outputs a logic 0 in an even field and a logic 1 in an odd field. 12 is the least significant bit of the H address counter 4 and the output of the field
An AND circuit 13 for performing an AND operation is a V address adder 13 for digitally adding the output of the AND circuit 12 to the output of the V address counter 5. These element parts S (field discriminating unit 11, AND circuit 12, address adder 13) enclosed by broken lines are parts added according to the present invention.

FIG. 5 is a timing chart showing the operation of the configuration of FIG. 1. Numerals 51, 52, and 53 denote the field discriminator 11, the least significant bit of the H address counter 4, and the output of the AND circuit 12 in FIG. Are respectively shown.

FIGS. 6 and 7 are scanning line state diagrams when convergence correction is performed using the configuration of FIG.
In FIG. 6, reference numerals 61a and 61b denote scanning lines of even fields, 62 denotes scanning lines of odd fields, and similarly, FIGS. 71a and 71b denote scanning lines of even fields, and 72 denotes scanning lines of odd fields.

As can be seen from FIG. 5, the field determination output 51,
AND output 53 of H address counter least significant bit output 52
Is supplied to the V address counter 5 by the V address adder 13.
Is added to Therefore, as for the vertical read address of the memory 6, the output of the V address counter 5 is specified as it is in the even field, and the output of the V address counter 5 and 1 are added to the output of the V address counter 5 in the odd field. The data is output alternately at each convergence correction output point in the horizontal direction.

That is, the convergence correction data of the odd field is obtained by dividing the convergence correction data of the even field on one scanning line (FIG. 3 (c)) and the convergence correction data of the even field on one scanning line (FIG. 3 (d)). It is output alternately for each horizontal convergence correction point.

For this reason, as shown in FIG. 62, the raster of the odd field becomes wavy around the center position of the rasters 61 (a) and 61 (b) of the even field.

According to the present embodiment, since the convergence correction is performed on the scanning lines of the odd-numbered fields in a wavy manner, there is an effect of visually reducing raster unevenness and improving image quality. Further, a trap filter for removing a frequency component of a wave of a scanning line in an odd field is provided, or a first filter is provided so as to suppress the frequency component.
By designing the LPF 8 shown in the figure, the scanning lines of the odd fields are changed to the scanning lines 71 of the even fields as shown in FIG.
Appearing in the middle between (a) and 71 (b), it is possible to eliminate vertical raster unevenness without becoming wavy.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 8 is a block diagram showing a second embodiment of the present invention. In FIG. 8, the components (ie, 1 to 11 and 13) that perform the same operations as those in FIG.
The same numbers as those in the figure are given. In addition,
14 is a frame counter that repeats 0 output and 1 output each time the output of the field discriminator 11 falls, and 15 is an A that performs an AND operation of the output of the frame counter 14 and the field discriminator 11.
ND circuit.

FIG. 9 is a dimming chart showing the circuit operation of FIG. 8, and reference numerals 91, 92, and 93 indicate the outputs of the field discriminating unit 11, the frame counter 14, and the AND circuit 15, respectively, in FIG.

FIG. 10 shows a scanning line state when convergence correction is performed using the configuration shown in FIG. 8, where 101a and 101b show scanning lines for even fields, and 102 and 103 show scanning lines for odd fields.

As can be seen from FIG. 9, the field discrimination output 91,
The AND output 93 of the frame count output 92 is added to the V address counter 5 by the V address adder 13. For this reason, as the read address in the vertical direction of the memory 6, the output of the V address counter 5 is specified as it is in the even field, and the V address counter 5 is read in the odd field.
Is output as it is, and the value obtained by adding 1 to the output of the V address counter 5 is output alternately for each frame.

That is, the convergence correction data of the odd field is obtained by dividing the convergence correction data of the even field on one scanning line (FIG. 3 (c)) and the convergence correction data of the even field on one scanning line (FIG. 3 (d)). It is output alternately for each frame.

For this reason, the scanning lines of the odd fields are shown in FIGS.
As shown in FIG.
It appears alternately up and down for each frame with the center position of (b) as the center.

According to the present embodiment, since the convergence correction of the scanning lines of the odd-numbered fields is performed alternately up and down for each frame, the raster unevenness in the vertical direction is apparently reduced and the image quality is improved.

Next, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 11 is a block diagram showing a third embodiment of the present invention. 11, the components (ie, 1 to 11) that perform the same operations as those in FIG. 1 are denoted by the same reference numerals as those in FIG. In addition, reference numeral 16 denotes a 1H delay circuit which stores the convergence correction data output from the memory for one horizontal period and outputs convergence correction data delayed by one horizontal period, and 17 denotes an output of the memory 6 and an output of the 1H delay circuit 16. An averaging circuit 18 for calculating the average value by digital processing selects an output of the memory 6 when the output of the field discriminator 11 is logic 0, that is, in an even field, and outputs an output of the field discriminator 11 which is logic 1 When there is, that is, in the odd field, the selection circuit selects the output of the averaging circuit 17.

Now, in the case of an even field, it is assumed that the output of the memory 6 is selected by the selection circuit 18 and the convergence correction amount shown in FIG.

Next, in the odd field, the 1H delay circuit 16 outputs the convergence correction data of the even field on one scanning line (third field).
FIG. 3 (C) shows that the convergence correction data (FIG. 3 (D)) of the even field under one scanning line is input from the memory 6 to the averaging circuit 17, and as a result,
From 17 the average value of each correction amount in FIGS. 3 (c) and (d),
That is, (a) is output, and convergence correction is performed via the selection circuit 18. As a result, the scanning line state is as shown in FIG.

According to the present embodiment, as the convergence correction data of the odd field, the average value of the convergence correction data of the even field above and below one scanning line is calculated and the convergence correction is performed, so that the convergence correction amount in the vertical direction becomes continuous. No raster unevenness occurs.

Next, a description will be given of a fourth embodiment in which the 1H delay circuit of the third embodiment shown in FIG. 11 is deleted, and the same operation can be performed.

FIG. 12 is a block diagram showing a fourth embodiment of the present invention. In FIG. 12, the same elements as those in FIG. 11 (ie, 1 to 11, 17, 18) are denoted by the same reference numerals as those in FIG. In addition, reference numeral 19 denotes a V address adder for adding the least significant bit of the H address counter 4 to the output of the V address counter 5, 20 a latch for holding data in the memory 6, and 21 for an output of the selection circuit 18. Latch.

Now, the V address adder 19 has an H address counter 4
, The least significant bit is added.
The convergence correction data at the address obtained by adding 1 to the output of the address counter 5 and the convergence correction data at the address designated by the V address counter 5 are output alternately. First, the convergence correction data at the address obtained by adding 1 to the output of the V address counter 5, that is, the same data as the convergence correction data delayed by 1H, is held in the latch 20.

Next, when the memory 6 outputs the convergence correction data at the address designated by the V address counter 5, the averaging operation is performed by the averaging circuit 17 and the result is held in the latch 21.

According to the present embodiment, the same effect as that of the third embodiment can be realized without the 1H delay circuit.

Next, a fifth embodiment of the present invention in which raster unevenness is corrected by using a raster unevenness correction signal generating means will be described with reference to FIG.

FIG. 13 is a block diagram showing a fifth embodiment of the present invention. In FIG. 13, components (ie, 1 to 11) that perform the same operations as those in FIG. 1 are denoted by the same reference numerals as those in FIG. In addition, reference numeral 22 denotes a raster unevenness correction signal of one field period synchronized with a raster scan necessary for correcting raster unevenness, based on signals input from the H blanking pulse input terminal 1 and the V blanking pulse input terminal 2. And a means for generating the raster unevenness correction signal. The output means of the digital-analog converter 7 of the conventional digital convergence correction device shown in FIG. For example, a circuit similar to the analog convergence circuit to be used can be considered.

An adder 23 outputs the output of the raster unevenness correction waveform generation circuit 22 only when the field discrimination output is logic 1.
An analog switch for transmitting the signal to a convergence correction signal output from the digital-analog converter 7;
The adder adds the output of the analog switch 23.

Now, in the even field, the convergence correction signal shown in FIG.
It is assumed that the signal is output from the analog converter 7. At each screen position, the raster unevenness correction waveform generating circuit 22 converts the convergence correction data (FIG. 3 (c)) output from the digital-analog converter 7 into an odd field and an odd field that does not cause raster unevenness. The difference from the convergence correction data (FIG. 3A) is output as a raster unevenness correction signal. The raster unevenness correction signal is supplied to the analog switch 23 and the adder 24.
As a result, the convergence correction amount shown in FIG. 3A for the even field and the convergence correction amount shown in FIG.
Output from 10. As a result, the screen state is as shown in FIG.
Thus, it is possible to eliminate raster unevenness.

According to the present embodiment, it is possible to eliminate raster unevenness in the vertical direction, and to reduce raster unevenness that occurs when interlaced scanning is not correctly performed in the deflection circuit.
Raster unevenness generated during digital convergence correction can be eliminated at the same time.

Further, in the present embodiment, the raster unevenness correction signal generation circuit 22 uses an H address counter instead of using the signals input from the H blanking pulse input terminal 1 and the V blanking pulse input terminal 2 to generate a signal. 4, the signal may be generated using the output of the V address counter 5.

Further, in the present embodiment, when the raster unevenness correction signal generation circuit 22 generates a raster unevenness correction signal of one frame cycle synchronized with the raster scan, the output of the raster unevenness correction waveform generation circuit 22 is directly sent to the adder 24. In addition, correction of raster unevenness can be performed. In this case, the field determination unit 11 and the analog switch 23 can be deleted.

Next, a sixth embodiment of the present invention for correcting the raster unevenness by controlling the amplitude of the convergence correction signal will be described with reference to the drawings.

FIG. 14 is a block diagram showing a sixth embodiment of the present invention. In FIG. 14, components (ie, 1 to 11) that perform the same operations as those in FIG. 1 are denoted by the same reference numerals as those in FIG. In addition, reference numeral 25 denotes the most significant bit of the V address counter 5 and the
An EXOR circuit that performs an exclusive OR operation on the outputs of the EXOR circuit 25, an analog switch 26 that is turned off when the output of the EXOR circuit 25 is logic 0 and turned on when the output of the EXOR circuit 25 is logic 1, and 27, 28, and 29 are resistors R1, R2, and R3, respectively. The amplitude control unit 30 is constituted by the components 26 to 29.

FIG. 15 is a diagram showing a vertical convergence correction output. In FIG. 15, the horizontal axis indicates the vertical position of the screen, and the vertical axis indicates the convergence correction amount. Also, 151,15
3 is the convergence correction amount of the even field at the top and bottom of the screen, and 152 and 154 are the convergence correction amounts of the odd field at the bottom of the screen.

FIG. 15A is a general explanatory diagram of vertical convergence distortion on a screen, and corresponds to FIG.

In FIG. 15A, the screen is equivalent to a 1 V period vertically and 1 horizontal.
This corresponds to the H period. The raster at the top of the screen is generally 1H
Positive distortion (correction amount ΔU) occurs near both ends of the period, and negative distortion (correction amount ΔL) occurs near the center. The same applies to the raster at the bottom of the screen. In the raster at the center of the screen (the center of the 1V period), no distortion occurs and the raster is zero.

Referring again to FIG. 15 with the general tendency of such vertical convergence distortion in mind, the meaning of FIG. 15 will be better understood.

FIG. 16 is a timing chart showing the operation of the configuration shown in FIG. 14. Reference numerals 161, 162, and 163 denote the output of the EXOR circuit 25 and the most significant bit of the field determination unit 11, the V address counter 5, respectively, in FIG.

First, the principle of a method for eliminating raster unevenness by the amplitude control method will be described.

Here, the term "amplitude control" has the following meaning. That is, in FIG. 15, the required correction amount 151 for the raster of the even field at the top of the screen has a pulse-like waveform,
The amount of correction required for the odd field raster at the top of the screen 15
Similarly, 2 also has a loose waveform and both are similar, but 151 is larger than 152 as a whole.

In the lower part of the screen, the required correction amount 153 for the even field raster has an inverted pulse-like waveform,
Similarly, the correction amount 154 required for the odd field raster has an inverted pulse-like waveform and is similar to each other, but 153 is smaller than 154 as a whole in the future.

Therefore, once the waveform of the required correction amount 151 for the raster of the even field at the top of the screen is created, the waveform of the required correction amount 152 can be created by controlling the amplitude thereof. Similarly, after the waveform of the required correction amount 153 for the raster of the even field at the bottom of the screen is created, the waveform of the required correction amount 154 can be created by controlling the amplitude of the waveform. The amplitude control means such a thing.

Now, since the output of the conventional digital convergence correction device having the configuration shown in FIG. 2 has only the convergence correction data of the even field, the convergence correction data 152 and 154 of the odd field should be output.
Instead, it outputs convergence correction data 151 and 153 for even fields. For this reason, the correction amount in the vertical direction is discontinuous, and raster unevenness occurs.

However, it can be seen from FIG. 15 that the convergence correction data 152 of the odd field above the center of the screen can be approximated to the convergence correction data 151 of the even field whose amplitude is reduced as described above. In addition, the convergence correction data 154 of the odd field below the center of the screen can be approximated to the convergence correction data 153 of the even field whose amplitude is increased.

In order to perform the above-described amplitude control, three types of gains of the amplitude control unit must be switched. Therefore, by lowering the gain of the convergence correction signal of the even field below the center of the screen and not changing the gain of the convergence correction signal of the odd field, the same raster unevenness reduction effect can be obtained by switching the two types of gain. be able to.

Next, a configuration for performing the above operation will be described. The field discriminator 11 outputs a signal 161 that is a logical 0 in an even field and a logical 1 in an odd field. Also,
From the most significant bit of the V address counter 5, a signal 16 which becomes logic 0 above the center of the screen and logic 1 below the center of the screen
2 is output. Therefore, from the EXOR circuit 25, in the even field, the logic 0 is above the center of the screen, and
That is, in the odd field, a signal 163 is output which is a logic 1 above the center of the screen and a logic 0 below the center of the screen.

When the output of the EXOR circuit is logic 0, the analog switch 26 is turned off. Is input to AMP9. When the output of the EXOR circuit is logic 1, the analog switch 26 is turned on. Thus, the gain is smaller than when the output of the EXOR circuit is logic 0.

Therefore, above the center of the screen, the convergence correction amount of the odd field becomes smaller than that of the even field, and below the center of the screen, the convergence correction amount of the even field becomes smaller than that of the odd field.
As a result, the correction amount in the vertical method becomes continuous, and it is possible to reduce raster unevenness.

According to this embodiment, it is possible to reduce raster unevenness with a simple circuit. Further, in this embodiment, when the amplitude is continuously modulated, it is possible to correct the raster unevenness more accurately.

It is needless to say that in all the above embodiments, a configuration in which the even field and the odd field are considered in reverse can be realized.

In all of the above embodiments, the interlaced scanning is performed. However, in the case of sequentially scanning, the convergence correction data is stored for every other scan line, and the convergence correction is performed. If the output of the least significant bit of the vertical address counter 5 is used instead of the output, the same effect can be obtained.

〔The invention's effect〕

According to the present invention, the memory storing the convergence correction data of one field is used at the time of the interlaced scanning, or the memory storing the convergence correction data at every other scan is used at the time of the sequential scanning. In addition, since the raster unevenness on the screen can be eliminated or reduced, the image quality can be improved after reducing the cost of the expensive memory by half and reducing the cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing a conventional example of a digital convergence correction device, and FIG. 3 is a diagram explaining the relationship between the vertical scanning line position and the convergence correction amount therewith. FIG. 4 is an explanatory diagram showing a raster state after convergence correction, FIG. 5 is a timing chart showing signal timings of main parts in FIG. 1, and FIG. 6 is a graph showing an improvement in raster unevenness according to the embodiment of FIG. FIG. 7 is an explanatory view showing the effect of improving raster unevenness when a low-pass filter is added to the embodiment of FIG. 1, and FIG. 8 is a block diagram showing another embodiment of the present invention. FIG. 9 is a timing chart showing signal timings of main parts in FIG. 8, FIG. 10 is an explanatory diagram showing the effect of improving the unevenness of the raster in the embodiment of FIG. 8, and FIGS. 11 to 14.
FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG.
FIG. 15 is a waveform diagram showing a convergence correction waveform in the vertical direction of the screen to be realized in the embodiment of FIG. 14, and FIG.
Explanatory diagram showing convergence distortion on the screen corresponding to the convergence correction waveform shown in FIG. 5, FIG. 16 is a timing chart showing the signal timing of the main part in FIG. 14,
It is. Description of reference numerals 4 ... H address counter, 5 ... V address counter, 6 ... Digital memory, 7 ... Digital / analog converter, 11 ... Field discriminator, 12,15 ... AND circuit, 13 ... V address adder, 14 ... frame counter, 16 ... 1H delay circuit, 17 ... average calculation circuit, 22 ... raster unevenness correction signal generator, 30 ... amplitude control unit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kosuke Ozeki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Yokohama Factory, Hitachi, Ltd. (72) Inventor Makoto Shiomi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock Shares (72) Inventor Michitaka Osawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi, Ltd. Consumer Electronics Laboratory (56) References JP-A-63-221788 (JP, A)

Claims (5)

(57) [Claims] 1. Convergence correction data at each grid point of a grid pattern arbitrarily set on a cathode ray tube screen by a raster scan method, wherein scanning lines are set as horizontal stripes and virtual lines perpendicular to the scanning lines are set as vertical stripes. Memory for generating and storing the digital signal, an address signal for specifying a horizontal address and a vertical address of the memory in synchronism with a raster scan on the cathode ray tube screen, and an address signal generating means. A digital-to-analog converter that reads convergence correction data from the digital memory in accordance with the address signal obtained, converts the digital-to-analog data, and outputs the digital-to-analog data. Scanning odd positions Lines and scanning lines at even positions, one of which is a first scanning line group and the other is a second scanning line group, and only the convergence correction data related to the first scanning line group is described above. When the first scanning line group is scanned in a digital memory, the convergence correction data is read out from the digital memory in accordance with the address signal generated by the address signal generating means and input to the digital / analog converter. When scanning the second scanning line group, in the one scanning period, the first scanning line group and the scanning line adjacent to the one scanning line belonging to the second scanning line group belong to the second scanning line group. The lower adjacent scanning line is selected, and the convergence correction data related to the upper adjacent scanning line and the convergence correction data related to the lower adjacent scanning line are extracted for the scan in the one scanning period. Te, convergence correction data operating means for inputting to the digital / analog converter is read alternately every grid point in the horizontal direction from said digital memory, a digital convergence correction device characterized by equipped. 2. A digital convergence correction apparatus according to claim 1, wherein said convergence correction data operation means scans said second scanning line group during said one scanning period for each frame. Among the scanning lines adjacent to and above the one scanning line belonging to the second scanning line group in the second scanning line group, the convergence correction data related to the upper adjacent scanning line and the convergence correction data related to the lower adjacent scanning line. A digital convergence correction device comprising means for alternately reading convergence correction data relating to a scanning line from the digital memory for each frame and inputting the data to the digital / analog converter. 3. The digital convergence correction apparatus according to claim 1, wherein said convergence correction data operation means scans said second scanning line group during said one scanning period. Among the scan lines adjacent to and above the one scan line belonging to the second scan line group belonging to the second scan line group, the convergence correction data related to the upper adjacent scan line and the scan line related to the lower adjacent scan line A digital convergence correction device comprising: means for reading convergence correction data from the digital memory, calculating an average value thereof, and inputting the average value to the digital / analog converter. 4. A convergence correction data at each grid point of a grid pattern arbitrarily set as a horizontal stripe on a scanning line and a vertical line on a virtual line orthogonal to the scanning line on a cathode ray tube screen by a raster scan method. Memory for generating and storing the digital signal, an address signal for specifying a horizontal address and a vertical address of the memory in synchronism with a raster scan on the cathode ray tube screen, and an address signal generating means. A digital-to-analog converter that reads convergence correction data from the digital memory in accordance with the address signal obtained, converts the digital-to-analog data into digital-to-analog data, and outputs the converted data. Scanning odd positions Lines and scanning lines at even positions, one of which is a first scanning line group and the other is a second scanning line group, and only the convergence correction data related to the first scanning line group is described above. In addition to storing in digital memory,
In synchronization with the raster scan on the cathode ray tube screen,
A raster unevenness correction signal generation circuit, which is preset to generate an analog waveform output equivalent to the difference between the convergence correction data related to the second scanning line group and that related to the first scanning line group, is prepared. When scanning the first scanning line group, convergence correction data is read from the digital memory in accordance with the address signal generated by the address signal generation means, input to the digital / analog converter, and the output thereof is subjected to convergence correction. When scanning the second scanning line group, the convergence correction data is read from the digital memory when scanning the first scanning line group, and the output from the digital / analog converter is input to the second scanning line group. The correction signal output from the raster unevenness correction signal generation circuit is added to generate a convergence correction output. A digital convergence correction device comprising an adding means for outputting the output signal. 5. A convergence correction data at each grid point of a grid pattern arbitrarily set as a horizontal stripe on a scanning line and a vertical line on a virtual line perpendicular to the scanning line on a cathode ray tube screen by a raster scan method. Memory for generating and storing the digital signal, an address signal for specifying a horizontal address and a vertical address of the memory in synchronism with a raster scan on the cathode ray tube screen, and an address signal generating means. A digital-to-analog converter that reads convergence correction data from the digital memory in accordance with the address signal obtained, converts the digital-to-analog data into digital-to-analog data, and outputs the converted data. Scanning odd positions Lines and scanning lines at even positions, one of which is a first scanning line group and the other is a second scanning line group, and only the convergence correction data related to the first scanning line group is described above. When the convergence correction data is read from the digital memory in accordance with the address signal generated by the address signal generation means and input to the digital / analog converter and the output thereof is used as a convergence correction output,
The output of the digital / analog converter is input and its amplitude is increased or reduced during a period of scanning the upper half of the screen of the first scanning line group and a period of scanning the lower half of the screen of the second scanning line group. A digital convergence correction device comprising amplitude control means, wherein the output whose amplitude is controlled is used as a convergence correction output.