JPH0690388A - Moire cancellation circuit - Google Patents

Abstract

PURPOSE:To reduce moire phenomena due to an interference between a picture signal pattern and a shadow mask pitch of a CRT. CONSTITUTION:A display device including a synchronizing separator circuit 2, a video circuit 3, a CRT 4 and a deflection circuit 5 is provided with a moire cancellation circuit 8. First and second pictures in which a horizontal scanning start position in a frame differs are set and the scanning start position of the 1st picture is deviated from that of the 2nd picture by using a specific function. Upon the receipt of a vertical synchronizing signal from the synchronizing separator circuit 2, an arithmetic operation control section 10 uses a coefficient of a function stored in a memory 9 to generate the respective position data corresponding to each horizontal synchronizing signal. When the data are given to the deflection circuit 5 via a D/A converter 11, a picture with high quality with less moire interference is outputted from a CRT 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moiré canceling circuit for reducing an image moiré phenomenon in a display device using a cathode ray tube (hereinafter referred to as CRT).

[0002]

2. Description of the Related Art A raster scan type display device used in a television receiver or a computer displays an image by repeating scanning of an electron beam in the horizontal direction and moving the scanning line (scanning line) in the vertical direction. is doing. In a display device using a CRT, the pitch of the shadow mask determines the dot pitch of phosphors that emit light in the video signal. Therefore, for example, when an ON / OFF luminance signal is applied to each dot in the horizontal direction, the pitch of the image display pattern and the pitch of the shadow mask of the CRT cause mutual interference, and a moire phenomenon occurs in the image.

In order to reduce such a moire phenomenon,
In the conventional display device, the following methods have been used in combination. (1) By changing the size of the image display area,
The pattern pitch of the image displayed on the CRT is changed to reduce mutual interference with the shadow mask. (2) By changing the pitch of the shadow mask,
Mutual interference between the shadow mask and the image display pattern is reduced. (3) The focus of the electron beam is deteriorated and the size of one dot of the image display pattern is increased. Then,
The contrast of mutual interference becomes small, and the moire phenomenon becomes inconspicuous.

[0004]

However, the conventional method as described above has the following problems. (1) With the method of changing the size of the display area of the image, it is difficult to determine the size of the display area for each image each time. (2) Changing the pitch of the shadow mask changes the design of the CRT including the shadow mask, which itself requires a considerable development period and development cost. (3) With the method of deteriorating the focus and increasing the spot size, it is difficult to reduce the moire phenomenon and maintain a predetermined resolution.

In recent years, display monitors are required to have various horizontal frequencies and vertical frequencies due to higher resolution and diversification. In such a multi-scan display device, it is impossible to reduce the moire phenomenon for all images and to eliminate the problem in practical use by the method described above. Further, the shadow mask pitch of the CRT is different between the center of the screen and the periphery of the screen, and even if the entire screen is uniformly corrected, it is difficult to reduce the uniform moire phenomenon on the entire screen.

The present invention has been made in view of the above-mentioned conventional problems, and it is possible to reduce the moire phenomenon in all operation modes and to suppress the deterioration of image resolution to a minimum. The purpose is to provide a circuit.

[0007]

SUMMARY OF THE INVENTION The present invention includes a sync separation circuit for separating vertical and horizontal sync signals from a video signal, and a deflection circuit for outputting vertical and horizontal deflection currents to a deflection coil of a cathode ray tube. Is a moire canceling circuit for reducing the image moire phenomenon caused by the interference between the pattern of the video signal and the pitch of the shadow mask of the cathode ray tube, the horizontal scanning line of the cathode ray tube being arranged at a constant pitch.
And the second screen is divided, and the data of the scanning start position of the first screen, which is different for each horizontal scanning line, and the data of the constant scanning start position of the second screen regardless of the horizontal scanning line, are sent to each horizontal scanning line. And a D / A converter that converts the data output from the calculation control unit into an analog signal and outputs a signal that controls the scanning start position of the horizontal deflection current to the deflection circuit. The deflection circuit delays a horizontal synchronizing signal output from the sync separation circuit by a delay time proportional to the output signal of the D / A converter to generate a horizontal deflection current. .

[0008]

According to the present invention having such characteristics, the sync separation circuit separates the vertical and horizontal sync signals from the video signal input to the display device, and supplies these signals to the arithmetic control section. Then, the arithmetic control unit generates data indicating the horizontal scanning start position with respect to the first and second screen positions in synchronization with the synchronization signal for each horizontal scanning period. The D / A converter converts this data into an analog signal and outputs it to the deflection circuit. Then, the deflection circuit generates a sawtooth wave current at a time controlled by the output signal of the D / A converter and applies the deflection current to the deflection coil. By doing so, the moire phenomenon of the image caused by the interference between the pattern of the image signal and the pitch of the shadow mask of the cathode ray tube is reduced.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A moire cancel circuit for a display device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a display device including a moire cancel circuit. 2 is an explanatory view of a display screen showing the operation of the moire cancel circuit of this embodiment.

In the display device shown in FIG. 1, an input terminal 1 is a terminal to which a video signal including R, G and B luminance signals is input, and is connected to a sync separation circuit 2 and a video circuit 3. The sync separation circuit 2 is a circuit for separating the horizontal and vertical sync signals from the video signal. The video circuit 3 includes an image amplification circuit and outputs the R, G, B luminance signals to the CRT 4. The deflection circuit 5 is a circuit that generates vertical and horizontal deflection currents based on the vertical and horizontal synchronization signals output from the sync separation circuit 2 and outputs the currents to the deflection coil 6. The deflection circuit 5 includes a horizontal deflection circuit (not shown) and a phase shifter 7 for a horizontal synchronizing signal, and generates a sawtooth wave current necessary for deflection. In the deflection circuit 5,
The signal at the scanning start position of the video signal including the dot signal is given by the moire cancel circuit described later. The phase shifter 7 is, for example, a circuit that generates a delay pulse proportional to the input signal with respect to the horizontal synchronizing signal, and the deflection circuit 5 applies a sawtooth-shaped horizontal deflection current to the deflection coil 6 from the time when the output pulse of the phase shifter 7 is generated. It is a circuit to flow.

Now, the display device has a moire canceling circuit 8
Is provided. The moire canceling circuit 8 includes a memory 9, an operation control unit 10, and a D / A converter 11, and outputs a scanning start position signal of each horizontal scanning line in one frame of a video signal to the deflection circuit 5. The memory 9 is composed of, for example, a non-volatile memory such as an EEPROM, and stores parameters (correction coefficients) required for calculating first position data and second position data described later.

As shown in FIG. 2, one frame of the CRT 4 is composed of a plurality of 1,2,3 ... X..N..M scanning lines. Here, the first screen shown by the dotted line is composed of odd-numbered scanning lines, and the scanning start position H1 of each line is determined by a function specified as described later. The solid line is composed of the second screen, that is, the even scanning lines, and the scanning start position H2 of each line has a fixed phase with respect to the horizontal synchronizing signal.

The scanning start position H1 on the first screen shown in FIG. 2 satisfies the following expression (1) with respect to the scanning start position H2 on the second screen. H1 = H2 + A (X−N) ² + B (1) H1, H2: Position data indicating the scan start position of the first and second screens X: Scan line number A: Change indicating the degree of curvature of a quadratic function Amount counting B: Amount of parallel movement of the first screen with respect to the second screen N: Scan line number at the center position of the frame

The maximum value of H1-H2 in the equation (1) is 1
The amount is equal to or less than the dot pitch of the video signal included in the horizontal scanning line, and FIG. 2 is an enlarged display in one frame of the video. The values of the correction coefficients A, B and N are respectively determined by the characteristics of the display device including the CRT 4, and are stored in the memory 9 together with the second position data (H2).

The operation control unit 10 is configured to include a microcomputer, counts the number of horizontal synchronizing signals in each vertical synchronizing period, reads the correction coefficient from the memory 9 in each horizontal scanning period, and for each horizontal scanning line. This is a circuit for performing the calculation of the equation (1). That is, the arithmetic control unit 10 stores the data of the scanning start position H2 of the second screen and the correction coefficients A, B and N in the memory 9.
Is read from, and the value of Expression (1) is calculated and added to H2.
Next, the D / A converter 11 is a circuit that converts the calculation result of the calculation control unit 10 into an analog signal. D / A converter 11
Is output to the phase shifter 7 in the deflection circuit 5.

In the moire cancel circuit 8 having the above-described structure, when the display device starts operating, the input terminal 1
The video signal is input to. The sync separation circuit 2 separates the vertical and horizontal sync signals from this video signal and supplies them to the arithmetic control unit 10. The arithmetic control unit 10 resets the address of the memory 9 by the vertical synchronizing signal and reads the correction coefficients A, B, N in the memory 9. When the signal of the first horizontal scanning line is input to the video circuit 3, the arithmetic control unit 10 transfers the data of the scanning start position H1 corresponding to the time t ₁ to the D / A converter 11 as shown in FIG. give. The D / A converter 11 converts this data into an analog voltage and supplies it to the deflection circuit 5. Then, the phase shifter 7 in the deflection circuit 5 delays the phase of the horizontal synchronizing signal by the input position signal,
Horizontal deflection current is generated from time t ₁ .

Next, when the signal of the second horizontal scanning line is input, the arithmetic control unit 10 reads the data at the scanning start position H2 of the second screen of the memory 9, and the data is D
/ A converter 11 At this time, the D / A converter 11 outputs an analog signal corresponding to time t ₀ in FIG. 2 to the deflection circuit 5. Then, the deflection circuit 5 generates a horizontal deflection current from time t ₀ .

Similarly, when the signal of the third horizontal scanning line is input, the arithmetic control unit 10 generates the data of the first scanning start position H1. Further, when the signal of the fourth horizontal scanning line is input, the arithmetic control unit 10 generates the data of the second scanning start position H2. Like this first
The data of the scanning start position and the data of the second scanning start position are alternately generated, and the signal processing is continued until the Mth horizontal scanning line. Then, the video signal output from the video circuit 3 is displayed on the CRT 4.

By such an operation, the display position of each horizontal scan is shifted to the left and right relative to each horizontal synchronizing signal. Therefore, the odd-numbered scan lines and the even-numbered scan lines are deviated, and the phase of the image display pattern and the interference wave of the shadow mask of the CRT 4 are not fixed. Therefore, the contrast due to the moire phenomenon becomes weak, and a delicate image is faithfully output on the display screen. Further, since the data of the first scanning start position is calculated by the arithmetic control unit 10 every horizontal scanning, even if the data of the first scanning start position H1 is different for each scanning position, all these values are stored. Therefore, the capacity of the memory 9 can be reduced.

In the multi-scan type display device,
For various display modes (when the frame frequency and the number of scanning lines are different), the coefficients A, B, N and the second position data H2 are stored in the memory 9 for each mode so as to minimize the moire phenomenon. Then, the optimum image is always displayed on the CRT 4.

In the present embodiment, the first screen position H1 is calculated according to the relation of the expression (1), but it goes without saying that other calculation expressions may be used.

[0022]

As described in detail above, according to the present invention, the data indicating each horizontal scanning start position is generated by the arithmetic control unit and is supplied to the deflection circuit, so that the video signal of each horizontal scanning is horizontally transmitted. It can be output by shifting a predetermined pitch from the synchronization signal. Therefore, the dot pitch of the video signal and the pitch of the shadow mask of the cathode ray tube will be independent of the type of display image, without lowering the image resolution,
The moire phenomenon of an image can be reduced. Therefore, an effect that a high quality image can be displayed is produced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a display device including a moire cancel circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a display screen showing the operation of the moire cancel circuit in the present embodiment.

[Explanation of symbols]

 1 Input Terminal 2 Sync Separation Circuit 3 Video Circuit 4 CRT 5 Deflection Circuit 6 Deflection Coil 7 Phase Shifter 8 Moire Cancel Circuit 9 Memory 10 Operation Control Unit 11 D / A Converter

Claims (4)

[Claims] 1. A pattern of a video signal of a display device and a sync circuit for separating a vertical and horizontal sync signal from a video signal, and a deflection circuit for outputting vertical and horizontal deflection currents to a deflection coil of a cathode ray tube. A moire canceling circuit for reducing a moire phenomenon of an image caused by interference with a pitch of a shadow mask of a cathode ray tube, wherein horizontal scanning lines of the cathode ray tube are divided into a first screen and a second screen at a constant pitch, And a calculation control unit for outputting data of the scanning start position of the first screen, which is different for each scanning line, and constant scanning start position of the second screen regardless of the horizontal scanning line, according to each horizontal scanning line. , A D / A converter that converts the data output from the arithmetic control unit into an analog signal and outputs a signal for controlling the scanning start position of the horizontal deflection current to the deflection circuit. The deflection circuit delays the horizontal synchronization signal output from the synchronization separation circuit by a delay time proportional to the output signal of the D / A converter to generate a horizontal deflection current. A moire canceling circuit characterized by being 2. The arithmetic control unit is configured to set a scanning start position H of the second screen with respect to a horizontal synchronizing signal.
2. A screen movement amount B indicating parallel movement of the first screen with respect to the second screen, and a change amount coefficient A indicating change amount of each delay time of each horizontal scanning line of the first screen, respectively. Using the scanning start positions H1 of the first and second screens
2. The moire cancel circuit according to claim 1, wherein data indicating H2 is output for each horizontal scanning line. 3. A non-volatile memory for storing a scan start position H2 of the second screen, a screen movement amount B which is a correction coefficient of the first screen, and a change amount coefficient A, respectively. The moire canceling circuit according to claim 2. 4. The scanning start position H1 of the first screen output from the arithmetic and control unit is: If the number of the horizontal scanning line at the center of one frame is N and the number of any horizontal scanning line is X, The X-th scanning start position H1 included in the first screen is H1 = H2 + A
The moire cancel circuit according to claim 2, wherein the relationship (X-N) ² + B is satisfied.