JP3077440B2 - Display monitor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cathode ray tube (hereinafter referred to as CR).
The present invention relates to a circuit for reducing a horizontal moiré phenomenon on a display screen of a raster scan type display monitor (hereinafter, referred to as a display monitor) using a display monitor (hereinafter referred to as T).

[0002]

2. Description of the Related Art A display monitor of a raster scan system displays an image by repeating scanning of an electron beam in a horizontal direction and moving the scanning line in a vertical direction. In a CRT, the dot pitch of a fluorescent material that can emit light is determined by the aperture pitch of a shadow mask. Therefore, for example, when a pattern in which the display is repeatedly turned on and off every dot in the horizontal direction is displayed, the pitch of the video display pattern and the pitch of the shadow mask of the CRT interfere with each other, and a horizontal moire phenomenon occurs. . To reduce such horizontal moiré phenomenon,
Conventionally, the following methods have been combined.

[0003] 1. By changing the size of the image display area, the pitch of the image display pattern is changed to reduce mutual interference with the shadow mask.

[0004] 2. The mutual interference between the shadow mask and the image display pattern is reduced by changing the pitch of the shadow mask.

[0005] 3. The size of one dot of the video display pattern by deteriorating the focus (hereinafter referred to as spot size)
And the contrast (shade) of the interference fringe pattern is reduced to make the moiré phenomenon less noticeable.

[0006]

However , the conventional method has the following problems.

[0007] 1. Depending on the number of display dots in the horizontal direction of the image, the moiré phenomenon may not be reduced even if the size of the display area is slightly changed.

[0008] 2. When changing the pitch of the shadow mask, in the case of a CRT of a television receiver, the number of display dots is substantially determined by the broadcasting method, and the display size is substantially determined by the size of the CRT. , But it is possible to select and produce an aperture pitch that does not produce moiré. However, since the production volume of a display monitor is small, it is not possible in terms of cost to produce a CRT with a different aperture pitch according to the display specifications. .

3. In the method of deteriorating the focus and increasing the spot size to reduce the contrast (shading) of the interference fringe pattern so as to make the moiré phenomenon inconspicuous, especially when high resolution is required, it is a contradictory request and cannot be adopted. .

[0010] 4. In recent years, display monitors have often been required to be of a so-called multi-scan type, which supports various horizontal frequency modes with a single unit due to higher resolution and diversification. It was impossible to make the moiré phenomenon inconspicuous and not set so as to have no practical problem, and there was no other way but to take a compromise in each mode.

5. In recent years, since the number of display monitors controlled by a microcomputer has been increasing, there has been a strong demand for enabling any control with a DC voltage so that the microcomputer can easily control the display monitor.

In view of the above problems, the present invention provides a display monitor having a moiré canceling circuit which can be set to reduce the moiré phenomenon in any mode and minimize the deterioration of resolution. It is intended to do so.

[0013]

In order to achieve the above object, according to the present invention, a control signal is inputted to a horizontal deflection block, and the control signal shifts the display position of a scanning line relatively horizontally in each horizontal cycle. By doing so, the horizontal moiré phenomenon is reduced.

[0014]

According to the circuit of the present invention, the horizontal moiré phenomenon can be reduced regardless of various modes, various display area sizes, and the aperture pitch of the shadow mask, and can be realized with a simple configuration. Therefore, it can be configured at a low cost.

[0015]

(Embodiment 1) FIG. 1 is a block diagram showing an embodiment of a moiré canceling circuit according to the present invention. In FIG. 1, reference numeral 1 denotes a frequency dividing circuit, 2 denotes a horizontal position shift circuit, 3 denotes a horizontal deflection block including a synchronization signal processing circuit 4, a horizontal output circuit 5, and a horizontal deflection coil 6.

FIG. 2 shows an example of a display screen by the moiré cancellation circuit of the present invention. The relationship and operation of each component in FIG. 1 will be described below with reference to FIG.

[0017]

In order to achieve the above object, a display monitor according to the present invention comprises a horizontal output circuit.
Path, horizontal deflection coil and S-shaped correction capacitor are connected in series
In the horizontal deflection output circuit having the above configuration, the S-shaped correction is performed.
The first resistor and the switch circuit are connected in parallel with the capacitor.
With a constant voltage source whose output voltage can be controlled by the DC voltage
Connect a series circuit and open the switch circuit every horizontal cycle.
By closing, the current is added to the horizontal deflection current and the horizontal
The display position of the screen for each period is relatively shifted left and right,
Add the current to be added to the horizontal deflection current to the center of the display screen and to the left and right.
And shift the screen position to DC voltage.
A configuration having a moiré cancel circuit that is more controllable is adopted .

Embodiment 2 FIG. 3 is a block diagram showing a second embodiment of the present invention. 11
Is a frequency dividing circuit, 12 is a horizontal position shift circuit, 13 is a resistor, 14 is a switch, 15 is a horizontal output circuit, 16 is a horizontal deflection coil, and 17 is an S-shaped correction capacitor.

In this embodiment, a horizontal output circuit, a deflection coil,
In a horizontal deflection output circuit having a configuration in which a character correction capacitor is connected in series, a series circuit of a resistor and a switch circuit is connected in parallel with the S-character correction capacitor, and the switch circuit is turned on and off every horizontal cycle. By adding the current to the horizontal deflection current, the display position of the screen in each horizontal cycle is relatively shifted left and right, and the current to be added to the horizontal deflection current changes between the center and the left and right portions of the display screen. It is configured.

FIG. 4 is a timing chart of FIG. The relationship and operation of each component in FIG. 3 will be described below with reference to FIG.

The frequency dividing circuit 11 outputs a control signal (FIG. 4B) having a period twice as long as the horizontal period from the input horizontal synchronizing signal (FIG. 4A). The horizontal position shift circuit 12 switches the switch 14 on and off according to the input control signal. When the switch 14 is on, a current flows through the first resistor 13, and when the switch 14 is off, no current flows through the resistor 13. Therefore, the current shown in FIG. 4D is added to the horizontal deflection current. This current causes the display position of the screen to shift left and right every horizontal cycle, so that the contrast (shade) of the moire phenomenon is weakened, and the moire phenomenon on the display screen is reduced. By the way, the display screen of the CRT is not spherical but close to a plane. For this,
As the distance from the center of the screen increases, the amount of deflection with the same deflection current increases. In order to uniformly reduce the moire phenomenon on the display screen, it is necessary to increase the current to be added to the horizontal deflection current at the center of the screen and to reduce the current at the periphery of the screen.

In the embodiment of FIG. 3, when the switch 14 is on, the resistor 13 is connected in parallel with the S-shaped correction capacitor 17. As shown in FIG.
Since a parabolic waveform having a horizontal cycle corresponding to the curvature of the display screen of the CRT as shown in FIG. 4C is generated, the current added to the horizontal deflection current becomes parabolic as shown in FIG. That is, it is large at the center of the display screen and becomes smaller as the distance to the left and right, so that the moire phenomenon can be reduced uniformly over the entire screen without the need for a special modulation circuit or the like.

The horizontal shift amount of the screen position may be a small amount smaller than the interval of one dot of the video display pattern, and the value of the resistor 13 is set so as to be optimal depending on the state of the moire phenomenon.

[0024] (Example 3) Figure 5 than that shown in the embodiment of FIG. 3 shows an <br/> block diagram of an embodiment of a specific invention. In this circuit example, a transistor is used as a switch. In FIG. 5, reference numeral 21 denotes a frequency dividing circuit including a second resistor 22 and a flip-flop 23. 23 may be any circuit as long as its output logic is inverted by a clock signal (horizontal synchronization signal). 25 is the first
, 26 is a third resistor, and 27 is a horizontal position shift circuit composed of an NPN transistor. 28 is a horizontal output circuit, 29 is a horizontal deflection coil, and 30 is an S-shaped correction capacitor. 24 is a first resistor 25, a third resistor 25
Horizontal position consisting of resistor 26 and NPN transistor 27
A shift circuit.

The relationship and operation of each component in FIG. 5 will be described below with reference to FIG. The logic of the output Q of the flip-flop 23 is inverted by the clock signal. Since the clock signal is a horizontal synchronizing signal (FIG. 4A), the output Q of the flip-flop 23 is alternately output high and low every horizontal cycle (FIG. 4B). The output Q of the flip-flop 23 passes through the third resistor 26 and is input to the base of the NPN transistor 27. When the output Q of the flip-flop 23 is high, the NPN transistor 27 is turned on, and a parabolic current is added to the horizontal deflection current through the first resistor 25 and the NPN transistor 27. When the output Q of the flip-flop 23 is low, the NPN transistor 27 is turned off, and no current flows through the first resistor 25, so that no current is added to the horizontal deflection current (fourth current).
(D)). Since the display position of the screen is shifted in the horizontal direction by adding the current to the horizontal deflection current, the display position of the screen is relatively shifted in the horizontal direction every horizontal cycle, thereby reducing the moire phenomenon on the display screen. You. Since the value of the current added to the horizontal deflection current is determined by the value of the first resistor 25, by changing the value of the first resistor 25, various numbers of display dots in the horizontal direction, display screen dimensions,
It is possible to set so that the moire phenomenon is not noticeable for any value of the aperture pitch of the CRT mask.

In addition to the embodiment shown in FIG. 5, if the circuit can change and control the current to be added to the horizontal deflection current at the center and the left and right portions of the display position of the screen, the circuit can be added to the horizontal deflection current. The moiré phenomenon is made uniform over the entire screen by correcting the current to be applied so that it is large at the center of the display position of the screen and small at the left and right parts, and shifting the display position of the screen every twice the horizontal period. Can be reduced.

(Embodiment 4) FIG. 6 is a block diagram showing a fourth embodiment of the present invention. FIG.
31 is a frequency dividing circuit, 32 is a horizontal position shift circuit, 33 is a first resistor, 34 is a switch, 35 is a horizontal output circuit,
36 is a horizontal deflection coil, 37 is an S-shaped correction capacitor, 3
Reference numeral 8 denotes a constant voltage source whose output voltage can be controlled by a control DC voltage (hereinafter simply referred to as a constant voltage source).

The embodiment shown in FIG. 6 is a constant voltage controllable output voltage by a control DC voltage in series with a series circuit of a first resistor 33 and a switch 34 connected in parallel with an S-shaped correction capacitor 37. A source 38 is connected, and the output voltage of the constant voltage source 38 is changed by a control DC voltage to control a value of a current to be added to the horizontal deflection current, thereby controlling a shift amount of a display screen. is there.

According to the circuit of FIG. 6, the moiré phenomenon can be reduced uniformly over the entire screen for any value of the number of display dots in the horizontal direction, the display screen width, and the aperture pitch of the CRT shadow mask. In addition, it is possible to control the shift amount of the display screen by using a DC voltage.

The relationship and operation of each component of FIG. 6 will be described below with reference to the timing chart of FIG.

The frequency dividing circuit 31 outputs a control signal (FIG. 4B) having a period twice as long as the horizontal period from the input horizontal synchronizing signal (FIG. 4A). The horizontal position shift circuit 32 switches the switch 34 on and off according to the input control signal. When the switch 34 is on, a voltage corresponding to the difference between the voltage at the point a in FIG. 6 and the output voltage of the constant voltage source 38 is applied to both ends of the first resistor 33, and a current flows.
Since the current does not flow through the first resistor 33 when the switch 4 is off, the current shown in FIG. 4D is added to the horizontal deflection current. When the output voltage of the constant voltage source 38 is changed by the control DC voltage, the voltage applied to both ends of the first resistor 33 when the switch 34 is turned on changes, so that the current added to the horizontal deflection current (FIG. 4 (d)), the DC component changes, and the shift amount of the front screen changes. The current added to the horizontal deflection current has a parabolic shape as shown in FIG. 4D. The current is large at the center of the display screen and becomes smaller as the distance from the left or right, so that the moire phenomenon is uniform over the entire screen. To reduce. The horizontal shift amount of the screen position may be a small amount less than the horizontal dot interval of the video display pattern, and the output voltage of the constant voltage source 38 is set by the control DC voltage so as to be optimal depending on the state of the moire phenomenon. .

[0032] FIG. 7, specifically from those shown in the embodiment of FIG. 6
FIG. 1 is a block diagram of an exemplary embodiment of the present invention. 31 in FIG.
Is a frequency dividing circuit, 39 is a second resistor, and 40 is a flip-flop. Any circuit 40 may be used as long as the output signal is inverted by a clock signal (horizontal synchronization signal). 32
Is a horizontal position shift circuit, 41 is a third resistor, 42 is a first resistor, 43 is an NPN transistor, 43 is a horizontal output circuit, 44 is a horizontal deflection coil, 45 is an S-shaped correction capacitor, and 38 is a constant voltage. The circuit 46 is a PNP transistor.

The relationship and operation of each component of the circuit of FIG. 7 will be described below with reference to the timing chart of FIG.

The logic of the output Q of the flip-flop 40 is inverted by the clock signal. Since the clock signal is a horizontal synchronizing signal (FIG. 4A), the output Q of the flip-flop 40 is alternately output high and low every horizontal cycle (FIG. 4).
(B)). The output Q of the flip-flop 40 passes through the third resistor 41 and is input to the base of the NPN transistor 43. A control DC voltage is applied to the base of the PNP transistor 46. The control DC voltage applied to the base of the PNP transistor 46 is a flip-flop 40
Is set to a value within a range in which the NPN transistor 43 and the PNP transistor 46 are turned on when the output Q of is high. When the output Q of the flip-flop 40 is high, NP
The N transistor 43 and the PNP transistor 46 are turned on, and the first resistor 42, the NPN transistor 4
3. A parabolic current is added to the horizontal deflection current through the PNP transistor 46, and when the output Q of the flip-flop 40 is low, the NPN transistor 43 is turned off and no current flows through the first resistor 42. Therefore, no current is added to the horizontal deflection current, and a current having a waveform as shown in FIG. 4D is added to the horizontal deflection current. Since the display position of the screen is shifted in the horizontal direction by adding the current to the horizontal deflection current, the display position of the screen is relatively shifted in the horizontal direction every horizontal cycle, thereby reducing the horizontal moire phenomenon on the display screen. Is done. The value of the current added to the horizontal deflection current is the value of the first resistor 42 when the output Q of the flip-flop 40 is high.
And the voltage across the first resistor 42. The value of the control DC voltage applied to the base of the PNP transistor 46 determines the voltage across the first resistor 42 when the output Q of the flip-flop 40 is high. The shift amount of the display position of the screen can be controlled by the value of the applied control DC voltage, and the control can be performed by the control DC voltage so that the moire phenomenon is minimized.

FIG. 14 shows an embodiment of the present invention in consideration of compatibility with a wideband multi-scan type display monitor. In FIG. 14 , reference numeral 81 denotes a DC blocking capacitor, 82 denotes a DC regeneration diode, 83 denotes an inverting amplifier, 84 denotes an inverting amplifier transistor, 85 denotes a fourth resistor, and 86 denotes a fifth resistor. In a wide-band multi-scan type display monitor, the horizontal deflection circuit power supply voltage b greatly changes depending on the horizontal deflection frequency, and the voltage a across the S-shaped correction capacitor 87 greatly changes. Therefore, in the embodiment of FIG. 7, it is necessary to greatly change the control DC voltage in accordance with the horizontal deflection frequency. In the embodiment of FIG. 14, in addition to the embodiment of FIG. 7, an inverting amplifier 83 based on the horizontal deflection circuit power supply voltage b is provided, so that the control DC voltage is inverted based on the horizontal deflection circuit power supply voltage b. By inputting the output voltage to the amplifier 83 and inputting the output voltage as a DC voltage for control of a constant voltage source, even when the horizontal deflection frequency changes, the DC voltage of the horizontal deflection circuit power supply voltage b and the voltage a across the S-shaped correction capacitor 87 can be obtained. Since the voltage levels are almost the same, the DC component of the current 1 added to the horizontal deflection current is not affected by the change in the voltage a between both ends of the S-shaped correction capacitor 87 and the control component inputted to the inverting amplifier 83. Determined only by DC voltage. Since the control signal input to the base of the NPN transistor 89 is shifted by the DC level by the DC blocking capacitor 81 and the DC regeneration diode 82, the ON / OFF operation of the NPN transistor 89 does not pose any problem. For this reason, it is possible to reduce the required variable range of the control DC voltage of the moiré cancel circuit in a wideband multi-scan type display monitor by adding a simple circuit, and further increase the control DC voltage by the horizontal deflection frequency. The complicated control of changing is not required.

FIG. 8 shows an embodiment of a moiré canceling circuit which prevents the vertical line of the display screen from being bent even in the non-interlace system and improves the quality of the display screen. Until now
In the method of the embodiment, the number of scanning lines per frame is even.
In the case of numbers, vertical lines will bend jaggedly
There was a problem. Regarding this problem, FIGS.
This will be described below with reference to FIGS.

FIG . 10 shows one embodiment corresponding to one frame.
FIG. 11 shows an example of a display screen when the number of scanning lines is odd.
In the above embodiments, the number of scanning lines per frame is even.
13 is an example of a display screen in the case of. Figure 12 shows the previous implementation
Time when the number of scanning lines per frame is odd in the example
FIG. 13 is a diagram showing one example of the above embodiment.
3 is a timing chart when the number of scanning lines is even.

In the above embodiments, the running per frame
If the number of lines is odd, the output level of the horizontal frequency divider 1 in FIG.
The shift control signal is as shown in FIG.
Because the logic of the initial value of
In FIG. 10, the number of scanning lines shifted as shown in FIG.
Since the frame and the odd-numbered frame are exchanged, FIG.
(B) As shown in FIG.
It just makes the vertical lines look thicker. But this
In the above embodiments, the number of scanning lines per frame is an even number.
In this case, the position shift control signal of the output of the horizontal frequency dividing circuit 1 in FIG.
The signal is as shown in FIG. 13, where the initial value of the even frame and the odd
In order that the logic of the initial value of the frame is thus consistent, Figure 1
As shown in FIG. 1A, the scanning line to be shifted coincides between the even frame and the odd frame. FIG. 11
As shown in (b), the vertical line of the display screen is bent by the shift amount in the left-right direction, and the quality of the display screen is degraded. In the case of an interlaced display monitor, the number of scanning lines per frame is always an odd number, so there is no problem. However, in the case of a non-interlaced display monitor, the number of scanning lines per frame is odd or even. In either case, the above phenomenon occurs.

In the embodiment shown in FIG .
Shift control signal, and this position shift control signal
The display position of the scanning line in the horizontal direction
By shifting, the video display signal pattern and the CRT
Reduces horizontal moire phenomenon caused by mutual interference with shadow mask
A moiré cancellation circuit for reducing the initial value setting circuit
By adding the relative position of the scanning line.
Swap the initial value of the shift direction left and right every frame period
You.

According to the embodiment of FIG . 8, per frame
The vertical lines on the display screen are jagged, regardless of the number of scanning lines
Eliminating the phenomenon of shaking and improving the quality of the display screen
It is possible.

In FIG. 8, 51 is a horizontal frequency dividing circuit, 52 is a horizontal position shift circuit, 53 is a horizontal deflection block, 54 is a synchronization signal processing circuit, 55 is a horizontal deflection output circuit, 56 is a horizontal deflection coil, and 57 is an initial value. It is a setting circuit. The operation of FIG. 8 will be described below.

In FIG. 8, the initial value setting circuit 57 outputs an initial value control signal corresponding to the frame period to the horizontal frequency dividing circuit 51 from the input vertical synchronizing signal. Horizontal frequency divider 51
Outputs to the horizontal position shift circuit 52 a position shift control signal having a period twice as long as the horizontal period in which the initial value is inverted every frame period from the input horizontal synchronization signal and the initial value control signal. Horizontal position shift circuit 52 , horizontal deflection block 53
Determines whether to shift the display position of the screen in the horizontal direction based on the input position shift control signal, and shifts the display position of the screen in the horizontal direction every twice the horizontal period. As a result, the display position of the screen is relatively shifted left and right every horizontal cycle, and the video display pattern and C
When the phase of the interference wave of the RT shadow mask is shifted every horizontal cycle, the contrast (shade) of the moire phenomenon is weakened, and the moire phenomenon on the display screen is reduced. Since the initial value of the position shift control signal is inverted for each frame period by the initial value control signal, regardless of the number of scanning lines in the frame period, the number of scanning lines in the frame period in the conventional example is an odd number regardless of the number of scanning lines in the frame period. In the same state, the timing diagram of the position shift control signal is as shown in FIG.
Since the scanning lines to be shifted as shown in FIG. 10 (a) is replaced by the even frame and odd frame, look like a vertical line only the display screen shift amount in the horizontal direction as shown in FIG. 10 (b) is thickened By itself, the vertical lines on the display surface are not bent regardless of the number of scanning lines in the frame period, and the quality of the display screen is improved.

FIG. 9 shows an embodiment of the concrete circuit of FIG . This example is for a non-interlaced display monitor. 51 horizontal divider circuit in FIG. 9 (a), 61 is a JK flip-flop (hereinafter referred to as JKFF). 52 is a horizontal position shift circuit, 62 is a first resistor, 63 is a third resistor, and 64 is an NPN transistor. 53 is a horizontal deflection block, 54 is a synchronization signal processing circuit, 55 is a horizontal output circuit, 65 is a horizontal deflection coil,
66 is an S-shaped correction capacitor. 57 is a frame dividing circuit, 67 is a second resistor, 68 is a JKFF, 69 is a first AND circuit, 70 is a second AND circuit, 71 is a first AND circuit.
And 72 is a second inverter. FIG.
In (b) shows a timing diagram of the circuit of FIG. 9 (a). FIG.
In (b) , it is assumed that the initial value of the position shift control signal is high when the frame is an even frame and low when the frame is an odd frame, but this may be reversed depending on the initial value of the JKFF 68 .

[0044] The operation shown in FIG. 9 (a) will be described below with reference to FIG. 9 (b). Output Q and output of JKFF68

[0045]

[Outside 1]

The logic is inverted by the clock signal.
Since the clock signal of JKFF68 is a vertical synchronizing signal as shown in FIG. 9 (b), the output Q and the output of JKFF68 (outer 1) every vertical period while maintaining the opposite logic to each other as shown in FIG. 9 (b) High and low are output alternately. The second AND circuit 70 receives the vertical synchronizing signal and the JKF
Outputs a logic product of the output Q of the F68, the output of the second AND times <br/> circuit 70 is inverted by an inverter 72 FIG 9 (b)
Is input to the J terminal of the JKFF 61, the first AND circuit 69 outputs the logical product of the vertical synchronizing signal and the output (outside 1) of the JKFF 68,
The first output of the AND circuit 69 is inverted by the inverter 71 is the initial value control signal B as shown in FIG. 9 (b) JKF
The signal is input to the K terminal of F. As shown in FIG. 9B , in the case of an even frame, the position shift control signal (JKFF6
The initial value of the output Q) of 1 is low at the J terminal of the JKFF61,
The K terminal is high because it is high, and in the case of an odd frame, the initial value of the position shift control signal (the output Q of the JKFF 61) is low because the J terminal of the JKFF 61 is high and the K terminal is low. JKFF61 when the vertical sync signal is low
Since the J terminal is high and the K terminal is high, the logic of the position shift control signal (the output Q of the JKFF 61) is inverted by the clock signal. The clock signal of JKFF61 is shown in FIG.
(B) the so the horizontal synchronizing signal, as shown, (the output Q of JKFF61) the position shift control signal is high and low in every horizontal period are alternately output as shown in Figure 9 (b).
Since the pulse width of the vertical synchronizing signal is constant irrespective of the even frame or the odd frame, the logic (high and low) of the position shift control signal corresponding to each scanning line is switched between the even frame and the odd frame. The position shift control signal (J
The output Q) of the KFF 61 passes through the third resistor 63 and is NPN
The signal is input to the base of the transistor 64. When the position shift control signal (output Q of JKFF61) is high, N
The PN transistor 64 is turned on, and the first resistor 6
2. A current corresponding to the voltage across the first resistor 62 is added to the horizontal deflection current through the NPN transistor 64.
When the position shift control signal (output Q of the JKFF 61) is low, the NPN transistor 64 is turned off, and no current flows through the first resistor 62, so that no current is added to the horizontal deflection current. Since the display position of the screen is shifted in the horizontal direction by adding the current to the horizontal deflection current, the display position of the screen is relatively shifted in the horizontal direction each time the logic of the position shift control signal is inverted. . Since the phase of the vertical sync signal is usually within the video signal blanking period, the display position of the screen is relatively shifted left and right every horizontal cycle within the range of the video display screen, reducing the moire phenomenon on the display screen Is done. Since the value of the current added to the horizontal deflection current is determined by the value of the first resistor 62, the value of the first resistor 62 should be changed so that the moire phenomenon is not noticeable in various modes. Is possible. In combination with the embodiments of FIGS. 6 and 7, it is possible to control the moire phenomenon by using a DC voltage.

[0047]

As is apparent from the above description of the embodiment, according to the present invention, regardless of the horizontal aperture pitch of the shadow mask of the CRT, the width of the image display area, and the number of display dots in the horizontal direction. Less moiré phenomenon,
In addition, resolution degradation can be minimized, and it can be realized with a simple configuration. Therefore, especially for multi-scan type display monitors, development time is significantly reduced, development costs are significantly reduced, The display quality can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a horizontal moiré cancel circuit according to an embodiment of the present invention.

FIG. 2 is a display screen diagram of the moiré cancel circuit.

FIG. 3 is a block diagram showing the principle of a horizontal moiré cancel circuit according to one embodiment of the present invention.

FIG. 4 is a timing chart of the same.

FIG. 5 is a block diagram of the specific circuit.

FIG. 6 is a block diagram showing the principle of a horizontal moiré canceling circuit according to an embodiment of the present invention for controlling the reduction of the moiré phenomenon by a DC voltage.

FIG. 7 is a block diagram of a specific circuit.

FIG. 8 is a block diagram showing the principle of a horizontal moiré cancel circuit according to an embodiment having a position shift initial value setting circuit according to the present invention;

FIG. 9A is a block diagram of a specific circuit, and FIG. 9B is a timing chart of the specific circuit.

FIG. 10 is a diagram of a display screen when the number of scanning lines per frame is odd in the non-interlaced system.

FIG. 11 is a diagram of a display screen when the number of scanning lines per frame is an even number in the same non-interlace method.

FIG. 12 is a timing chart in the case where the number of scanning lines per frame is an odd number in the same non-interlaced system.

FIG. 13 is a timing chart in the case where the number of scanning lines per frame is an even number in the same interlace method.

FIG. 14 is a block diagram of an embodiment of the present invention in consideration of support for a wideband multi-scan type display monitor.

[Explanation of symbols]

 Reference Signs List 3 horizontal output circuit 5 constant voltage source 21 first resistor 22 switch circuit 41 horizontal deflection coil 42 S-shaped correction capacitor

──────────────────────────────────────────────────続 き Continued on the front page (31) Priority claim number Japanese Patent Application No. 4-53369 (32) Priority date March 12, 1992 (1992.3.12) (33) Priority claim country Japan (JP) (56) References JP-A-3-158894 (JP, A) JP-A-63-275284 (JP, A) JP-A-5-165419 (JP, A) JP-A-5-236290 (JP, A) Kaihei 5-236291 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 1/00 G09G 1/04 G09G 1/16 H04N 3/16

Claims (2)

(57) [Claims] 1. A horizontal deflection output circuit having a configuration in which a horizontal output circuit, a horizontal deflection coil, and an S-shaped correction capacitor are connected in series, wherein a first resistor, a switch circuit, and a control circuit are connected in parallel with the S-shaped correction capacitor. A series circuit with a constant voltage source whose output voltage can be controlled by a direct current voltage is connected, and the switch circuit is opened and closed every horizontal cycle to add a current to a horizontal deflection current to display a screen at each horizontal cycle. Display with a moiré cancel circuit that relatively shifts the horizontal direction and changes the current to be added to the horizontal deflection current at the center and left and right of the display screen, and that the shift amount of the screen position can be controlled by a DC voltage. monitor. 2. The display monitor according to claim 1 , further comprising a broadband multi-scan type moiré cancel circuit for supplying a DC voltage for controlling a shift amount of a screen position through an inverting amplifier using transistors based on a horizontal deflection circuit power supply voltage. Display monitor.