JP2000031418A5 - - Google Patents

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Publication number
JP2000031418A5
JP2000031418A5 JP1999127655A JP12765599A JP2000031418A5 JP 2000031418 A5 JP2000031418 A5 JP 2000031418A5 JP 1999127655 A JP1999127655 A JP 1999127655A JP 12765599 A JP12765599 A JP 12765599A JP 2000031418 A5 JP2000031418 A5 JP 2000031418A5
Authority
JP
Japan
Prior art keywords
thickness
multilayer capacitor
additional diffusion
barrier layer
barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1999127655A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000031418A (ja
Filing date
Publication date
Priority claimed from US09/074,882 external-priority patent/US6046059A/en
Application filed filed Critical
Publication of JP2000031418A publication Critical patent/JP2000031418A/ja
Publication of JP2000031418A5 publication Critical patent/JP2000031418A5/ja
Pending legal-status Critical Current

Links

JP11127655A 1998-05-08 1999-05-07 積層型キャパシタ中の電極とプラグとの間の導電率を改善する方法及び積層型キャパシタ Pending JP2000031418A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/074,882 US6046059A (en) 1998-05-08 1998-05-08 Method of forming stack capacitor with improved plug conductivity
US09/074882 1998-05-08

Publications (2)

Publication Number Publication Date
JP2000031418A JP2000031418A (ja) 2000-01-28
JP2000031418A5 true JP2000031418A5 (enExample) 2005-04-14

Family

ID=22122235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11127655A Pending JP2000031418A (ja) 1998-05-08 1999-05-07 積層型キャパシタ中の電極とプラグとの間の導電率を改善する方法及び積層型キャパシタ

Country Status (7)

Country Link
US (2) US6046059A (enExample)
EP (1) EP0955679B1 (enExample)
JP (1) JP2000031418A (enExample)
KR (1) KR100372404B1 (enExample)
CN (1) CN1235368A (enExample)
DE (1) DE69918219T2 (enExample)
TW (1) TW410429B (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6174799B1 (en) * 1999-01-05 2001-01-16 Advanced Micro Devices, Inc. Graded compound seed layers for semiconductors
US6624076B1 (en) * 2000-01-21 2003-09-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US6214661B1 (en) * 2000-01-21 2001-04-10 Infineon Technologoies North America Corp. Method to prevent oxygen out-diffusion from BSTO containing micro-electronic device
US6358855B1 (en) 2000-06-16 2002-03-19 Infineon Technologies Ag Clean method for recessed conductive barriers
US6297123B1 (en) * 2000-11-29 2001-10-02 United Microelectronics Corp. Method of preventing neck oxidation of a storage node
US6432725B1 (en) 2001-09-28 2002-08-13 Infineon Technologies Ag Methods for crystallizing metallic oxide dielectric films at low temperature
US6515325B1 (en) 2002-03-06 2003-02-04 Micron Technology, Inc. Nanotube semiconductor devices and methods for making the same
US7231839B2 (en) * 2003-08-11 2007-06-19 The Board Of Trustees Of The Leland Stanford Junior University Electroosmotic micropumps with applications to fluid dispensing and field sampling
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
CN120113025A (zh) * 2023-06-16 2025-06-06 株式会社村田制作所 电容器及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5381302A (en) * 1993-04-02 1995-01-10 Micron Semiconductor, Inc. Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same
US5504041A (en) * 1994-08-01 1996-04-02 Texas Instruments Incorporated Conductive exotic-nitride barrier layer for high-dielectric-constant materials
US6093615A (en) * 1994-08-15 2000-07-25 Micron Technology, Inc. Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug
JPH0945877A (ja) * 1995-07-31 1997-02-14 Matsushita Electron Corp 容量素子の製造方法
JP3388089B2 (ja) * 1996-04-25 2003-03-17 シャープ株式会社 不揮発性半導体メモリ素子の製造方法
KR100226772B1 (ko) * 1996-09-25 1999-10-15 김영환 반도체 메모리 장치 및 그 제조방법
KR100445059B1 (ko) * 1997-06-30 2004-11-16 주식회사 하이닉스반도체 반도체장치의캐패시터제조방법

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