JP2000031378A - Power semiconductor module - Google Patents
Power semiconductor moduleInfo
- Publication number
- JP2000031378A JP2000031378A JP10208666A JP20866698A JP2000031378A JP 2000031378 A JP2000031378 A JP 2000031378A JP 10208666 A JP10208666 A JP 10208666A JP 20866698 A JP20866698 A JP 20866698A JP 2000031378 A JP2000031378 A JP 2000031378A
- Authority
- JP
- Japan
- Prior art keywords
- power semiconductor
- semiconductor chip
- soldered
- metal base
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は電力用半導体モジュ
ールに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor module.
【0002】[0002]
【従来の技術】この種の電力用半導体モジュールに図2
に示すようなものがある。図2において,1はIGB
T,MOSFET,バイポーラトランジスタ,サイリス
タ,ダイオード等の電力用半導体チップである。2はC
BC基板で,絶縁用のセラミックス板3の一方の表面に
は銅板4が分子結合された状態で貼り付けられ,また,
他方の表面には銅回路5がセラミックス板3に分子結合
された状態で張り付けられている。この銅回路5上の所
要個所に一方の出力端子板6aが半田付けされ,さらに
出力端子板6a上には,電力用半導体チップ1が半田付
けされている。また,電力用半導体チップの上に他方の
出力端子板6bが半田付けされている。この電力用半導
体チップ1が搭載されたCBC基板が,銅,鉄などの金
属ベース8に半田付けされている。この後、金属ベース
8上に樹脂製ケース9を接着し,このケース内に樹脂1
0を注入して封止している。2. Description of the Related Art FIG.
There is something like that shown in In FIG. 2, 1 is IGB
It is a power semiconductor chip such as T, MOSFET, bipolar transistor, thyristor, diode and the like. 2 is C
On a BC substrate, a copper plate 4 is attached to one surface of an insulating ceramic plate 3 in a state of being molecularly bonded.
On the other surface, a copper circuit 5 is attached in a state of being molecularly bonded to the ceramic plate 3. One output terminal plate 6a is soldered to a required portion on the copper circuit 5, and the power semiconductor chip 1 is further soldered on the output terminal plate 6a. The other output terminal plate 6b is soldered on the power semiconductor chip. The CBC substrate on which the power semiconductor chip 1 is mounted is soldered to a metal base 8 such as copper or iron. Thereafter, a resin case 9 is bonded onto the metal base 8, and the resin 1 is placed in the case.
0 is injected for sealing.
【0003】この電力用半導体モジュールを実装し、電
流を流して使用した時,電力用半導体チップ1は発熱す
る。この発熱した電力用半導体チップ1の熱は,CBC
基板2を介して金属ベース8に伝導し,金属ベース8が
固定された放熱器から放出する。When the power semiconductor module is mounted and used by passing a current, the power semiconductor chip 1 generates heat. The generated heat of the power semiconductor chip 1 is converted into CBC
The electric current is transmitted to the metal base 8 via the substrate 2 and is emitted from the radiator to which the metal base 8 is fixed.
【0004】[0004]
【発明が解決しようとする課題】しかし,この電力用半
導体モジュールは,電力用半導体チップの一方向から金
属ベース8,放熱器を介して放熱されるので熱設計を十
分大きくとる必要があった。However, in this power semiconductor module, heat is radiated from one direction of the power semiconductor chip through the metal base 8 and the radiator, so that it is necessary to take a sufficiently large thermal design.
【0005】[0005]
【課題を解決するための手段】請求項1の電力用半導体
モジュールは,金属ベースと,この金属ベースに半田付
けされ,絶縁用のセラミックス板と,このセラミックス
板の一方の表面に貼られた銅板と,他方の表面に貼られ
た銅回路とにより構成されたCBC基板と,上記銅回路
上に半田付けされた電力用半導体チップと,上記電力用
半導体チップの上部に直接半田付けされ,かつ底部が上
記CBC基板に半田付けされた出力端子板とにより構成
されている。According to a first aspect of the present invention, there is provided a power semiconductor module, comprising: a metal base; a ceramic plate for soldering to the metal base; an insulating ceramic plate; and a copper plate attached to one surface of the ceramic plate. And a CBC substrate composed of a copper circuit adhered to the other surface, a power semiconductor chip soldered on the copper circuit, and a bottom part directly soldered to the top of the power semiconductor chip. And an output terminal board soldered to the CBC board.
【0006】すなわち,銅回路上に電力用半導体チップ
が半田付けされ,この銅回路を貼り付けたCBC基板を
金属ベースに半田付けされる。一方,電力用半導体チッ
プの上部に直接外部引き出し用の出力端子板が半田付け
され,さらにこの出力端子板が途中の底部でCBC基板
に半田付けされている。That is, a power semiconductor chip is soldered on a copper circuit, and a CBC substrate to which the copper circuit is attached is soldered to a metal base. On the other hand, an output terminal plate for external drawing is directly soldered to the upper part of the power semiconductor chip, and the output terminal plate is further soldered to the CBC substrate at the bottom partway.
【0007】従って電力用半導体モジュールを使用した
時に発生する電力用半導体チップの熱は,電力用半導体
チップの一方の表面は,CBC基板を介して金属ベース
に放出されるとともに,電力用半導体チップの他の表面
は外部引き出し用の出力端子板からCBC基板,金属ベ
ースを介して放出される。Accordingly, the heat of the power semiconductor chip generated when the power semiconductor module is used is released on one surface of the power semiconductor chip to the metal base via the CBC substrate, and the heat of the power semiconductor chip is reduced. The other surface is emitted from the output terminal plate for external drawing through the CBC substrate and the metal base.
【0008】[0008]
【発明の実施の形態】本発明の実施の形態を図1に基づ
いて説明する。図1において,図2と同一符号のものは
同一機能のものを示す。図1が図2と異なる点は,図2
では電力用半導体チップ1に直接又は銅回路上に板状の
出力端子板6a,6bが設けられ,樹脂ケースの外部に
引き出されているのに対し,図1では電力用半導体チッ
プ上に設けられた出力端子は,一旦CBC基板の銅回路
に半田付けされた後,樹脂ケースの外部に引き出されて
いる点にある。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. In FIG. 1, those having the same reference numerals as those in FIG. 2 indicate those having the same functions. FIG. 1 differs from FIG.
In FIG. 1, the plate-like output terminal plates 6a and 6b are provided directly on the power semiconductor chip 1 or on a copper circuit, and are drawn out of the resin case. The output terminals are once drawn out of the resin case after being soldered to the copper circuit of the CBC board.
【0009】すなわち,1はIGBT,MOSFET,
バイポーラトランジスタ,サイリスタ等の電力用半導体
チップである。2はCBC基板で,絶縁用のセラミック
ス板3の一方の表面には,分子結合された状態で張り付
けられ,また,他方の表面には銅回路5がセラミックス
板3に分子結合された状態で貼り付けられている。8は
金属ベースで,金属ベース8の上に半田箔が搭載又はク
リーム半田が塗布され,この半田上にCBC基板2が搭
載される。CBC基板の所定個所に半田箔が搭載,又は
クリーム半田が塗布され,この半田上に外部に引き出す
第1の出力端子板7aが搭載される。この出力端子板7
aの上に,半田箔が搭載,又はクリーム半田が塗布さ
れ,この半田上に電力用半導体チップ1が搭載される。
さらに,この電力用半導体チップ1の上に半田箔が搭
載,又はクリーム半田が塗布され,外部に引き出す第2
の出力端子板7bが搭載される。That is, 1 is an IGBT, MOSFET,
It is a power semiconductor chip such as a bipolar transistor and a thyristor. Reference numeral 2 denotes a CBC substrate, which is attached to one surface of an insulating ceramic plate 3 in a state of being molecularly bonded, and a copper circuit 5 is bonded to the other surface in a state of being molecularly bonded to the ceramic plate 3. It is attached. Reference numeral 8 denotes a metal base on which a solder foil is mounted or cream solder is applied, and the CBC substrate 2 is mounted on the solder. A solder foil is mounted on a predetermined portion of the CBC substrate, or cream solder is applied, and a first output terminal plate 7a to be drawn out is mounted on the solder. This output terminal plate 7
a, a solder foil or cream solder is applied, and the power semiconductor chip 1 is mounted on the solder.
Further, a solder foil is mounted on the power semiconductor chip 1 or cream solder is applied thereon, and a second
Is mounted.
【0010】上記,第2の出力端子板7bは,一旦下方
に折り曲げられ,底部7b1がCBC基板2に接触して
いる。この出力端子7bの底部7b1と,CBC基板2
との間には,半田が設けられている。そして,これをリ
フロー炉に投入し,金属ベース8,CBC基板2,第1
出力端子板7a,電力用半導体チップ1,第2の出力端
子7bが半田付けされるとともに,第2の出力端子板7
bとCBC基板2との間も半田付けされる。この後,金
属ベース8上に,樹脂ケース9を接着し,このケース内
に樹脂10を注入して,電力用半導体チップ1が封止さ
れている。The above-mentioned second output terminal plate 7b is once bent downward, and the bottom 7b1 is in contact with the CBC substrate 2. The bottom 7b1 of the output terminal 7b and the CBC substrate 2
Is provided between them. Then, this is put into a reflow furnace, and the metal base 8, the CBC substrate 2, the first
The output terminal plate 7a, the power semiconductor chip 1 and the second output terminal 7b are soldered and the second output terminal plate 7
b and the CBC board 2 are also soldered. Thereafter, a resin case 9 is adhered onto the metal base 8, and a resin 10 is injected into the case, whereby the power semiconductor chip 1 is sealed.
【0011】この電力用半導体モジュールを実装し,電
流を流して使用したとき,電力用半導体チップ1は発熱
する。この発熱した電力用半導体チップ1の熱は,出力
端子板7a,CBC基板2を介して金属ベース8に伝導
するとともに,電力用半導体チップ1の熱は,第2の出
力端子板7bとその底部7b1,CBC基板2を介して
金属ベース8に伝導する。そして,熱は金属ベース8か
ら図示しない放熱器を介して効率よく放出される。When the power semiconductor module is mounted and used by passing a current, the power semiconductor chip 1 generates heat. The generated heat of the power semiconductor chip 1 is conducted to the metal base 8 via the output terminal plate 7a and the CBC substrate 2, and the heat of the power semiconductor chip 1 is transferred to the second output terminal plate 7b and the bottom thereof. 7b1 and the metal base 8 via the CBC substrate 2. Then, heat is efficiently released from the metal base 8 via a radiator (not shown).
【0012】すなわち,電力用半導体チップ1の熱は両
面から金CBC基板2,金属ベース6を介して放出され
る。このため,金属ベース6が取れ付けられる放熱器を
小さくすることができる。That is, the heat of the power semiconductor chip 1 is released from both sides through the gold CBC substrate 2 and the metal base 6. Therefore, the size of the radiator to which the metal base 6 can be attached can be reduced.
【0013】上記実施の形態では,1個の電力用半導体
チップについて説明しているが,2個以上のものにも適
用できる。In the above embodiment, one power semiconductor chip is described, but the present invention can be applied to two or more power semiconductor chips.
【0014】[0014]
【発明の効果】本発明の電力用半導体モジュールによる
と,その使用時に電力用半導体チップから発生する熱
は,電力用半導体チップの両面からCBC基板を介して
金属ベースから効率よく放出される。According to the power semiconductor module of the present invention, heat generated from the power semiconductor chip during use is efficiently radiated from the metal base from both sides of the power semiconductor chip via the CBC substrate.
【図1】本発明の電力用半導体モジュールの一実施の形
態を示す断面図である。FIG. 1 is a sectional view showing an embodiment of a power semiconductor module of the present invention.
【図2】従来の電力用半導体モジュールの断面図であ
る。FIG. 2 is a sectional view of a conventional power semiconductor module.
1 電力用半導体チップ 2 CBC基板 3 セラミックス板 4 銅板 5 銅回路 7a 第1の出力端子板 7b 第2の出力端子板 7b1 底部 8 金属ベース 9 樹脂ケース REFERENCE SIGNS LIST 1 power semiconductor chip 2 CBC board 3 ceramic plate 4 copper plate 5 copper circuit 7 a first output terminal plate 7 b second output terminal plate 7 b 1 bottom 8 metal base 9 resin case
Claims (1)
けされ,絶縁用のセラミックス板とこのセラミックス板
の一方の表面に貼られた銅板と他方の表面に貼られた銅
回路とにより構成されたCBC基板と,上記銅回路上に
半田付けされた電力用半導体チップと,上記電力用半導
体チップの上部に直接半田付けされ,かつ底部が上記C
BC基板に半田付けられた外部引き出し用の出力端子板
とにより構成された電力用半導体モジュール。1. A semiconductor device comprising: a metal base; a ceramic plate for insulation, which is soldered to the metal base; a copper plate bonded to one surface of the ceramic plate; and a copper circuit bonded to the other surface. A CBC substrate, a power semiconductor chip soldered on the copper circuit, and soldering directly on top of the power semiconductor chip, and
A power semiconductor module comprising an external lead-out output terminal plate soldered to a BC substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20866698A JP3403338B2 (en) | 1998-07-08 | 1998-07-08 | Power semiconductor module |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20866698A JP3403338B2 (en) | 1998-07-08 | 1998-07-08 | Power semiconductor module |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000031378A true JP2000031378A (en) | 2000-01-28 |
JP3403338B2 JP3403338B2 (en) | 2003-05-06 |
Family
ID=16560050
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20866698A Expired - Fee Related JP3403338B2 (en) | 1998-07-08 | 1998-07-08 | Power semiconductor module |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3403338B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006280059A (en) * | 2005-03-28 | 2006-10-12 | Matsushita Electric Works Ltd | Power converter |
US7671382B2 (en) | 2005-12-19 | 2010-03-02 | Mitsubishi Electric Corporation | Semiconductor device with thermoplastic resin to reduce warpage |
JP2019021684A (en) * | 2017-07-12 | 2019-02-07 | 株式会社東芝 | Semiconductor package |
-
1998
- 1998-07-08 JP JP20866698A patent/JP3403338B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006280059A (en) * | 2005-03-28 | 2006-10-12 | Matsushita Electric Works Ltd | Power converter |
JP4674482B2 (en) * | 2005-03-28 | 2011-04-20 | パナソニック電工株式会社 | Power converter |
US7671382B2 (en) | 2005-12-19 | 2010-03-02 | Mitsubishi Electric Corporation | Semiconductor device with thermoplastic resin to reduce warpage |
JP2019021684A (en) * | 2017-07-12 | 2019-02-07 | 株式会社東芝 | Semiconductor package |
Also Published As
Publication number | Publication date |
---|---|
JP3403338B2 (en) | 2003-05-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3773268B2 (en) | Microelectronic components with sandwich structure | |
KR100536115B1 (en) | Power semiconductor device | |
KR940010293A (en) | Power module | |
US20020185726A1 (en) | Heat pipe thermal management of high potential electronic chip packages | |
JP7238330B2 (en) | Semiconductor device and method for manufacturing semiconductor device | |
US20140110833A1 (en) | Power module package | |
JP3129020B2 (en) | Semiconductor device | |
US20070108594A1 (en) | Semiconductor apparatus | |
JP3403338B2 (en) | Power semiconductor module | |
CN108735722B (en) | Semiconductor device and method for manufacturing semiconductor device | |
JP2005332918A (en) | Electronic apparatus | |
WO2020241239A1 (en) | Semiconductor device | |
JP3855726B2 (en) | Power module | |
JPH1117081A (en) | Semiconductor module for power | |
KR100244826B1 (en) | A semiconductor device and method for manufacturing the same | |
JPH0922970A (en) | Electronic component | |
JPH08148647A (en) | Semiconductor device | |
JP3048707B2 (en) | Hybrid integrated circuit | |
JP2000031357A (en) | Power semiconductor module | |
JP3321092B2 (en) | Power semiconductor module | |
JP3221844B2 (en) | Power semiconductor module | |
JP2022110873A (en) | Semiconductor device | |
JPH05235567A (en) | Hybrid integrated circuit device | |
JP2006173509A (en) | Semiconductor device and manufacturing method therefor | |
CN115985866A (en) | Power module |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090228 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090228 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100228 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100228 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110228 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110228 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120229 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120229 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130228 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130228 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140228 Year of fee payment: 11 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |