JP2000031328A - Multilayered ceramic wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered ceramic wiring board in which the occurrence of warps is suppressed, though the board incorporates a capacitor near its IC chip mounting surface. SOLUTION: A multilayered alumina ceramic wiring board having a front surface 100a, which is formed as an IC chip mounting surface and a rear surface 100b, incorporates a capacitor 10 composed of molybdenum-added dielectric layers 11-14 and electrode layers 21-25 which are formed in square shapes on nearly the whole upper and lower surfaces of the layers 11-14 by integral sintering and composed mainly of tungsten near the front surface 100a, and is provided with a conductor layer 61 made of the same material composed mainly of tungsten as that of the electrode layers 21-25 near the rear surface 100b. Even when the coefficients of firing shrinkage of ceramic layers 1-5 are different from those of the electrode layers 21-25, the conductor layer 6 having nearly the same coefficient of firing shrinkage as the electrode layer 21, etc., has is formed on the rear surface side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic multilayer wiring board, and more particularly to a ceramic multilayer wiring board having a built-in capacitor.

[0002]

2. Description of the Related Art Hitherto, in order to remove electromagnetic noise that enters a ground potential or a power supply potential of an IC chip, a capacitor has been built in a ceramic multilayer wiring board that houses and mounts the IC chip. In order to form such a capacitor in a ceramic multilayer wiring board (hereinafter, also simply referred to as a board), the following method can be used. That is, a ceramic layer made of the same ceramic (for example, alumina) as a normal ceramic layer, or a ceramic layer containing ceramic (for example, alumina) as a main component and adding a metal such as tungsten or molybdenum or other components to increase the dielectric constant. Is used as a dielectric layer and sandwiched between electrode layers formed over substantially the entire surface of the dielectric layer,
It is formed simultaneously with sintering of the substrate by integral sintering. By the way, in forming the built-in capacitor in this way, it is necessary to make the firing shrinkage of the electrode layer coincide with the firing shrinkage of the ceramic layer. The electrode layer is often formed over as large an area as possible in order to increase the capacitance of the capacitor. For this reason, in general, unlike a wiring layer having a small area, the influence of the firing shrinkage becomes large. That is, if the firing shrinkage ratios do not match, the substrate may be warped or distorted due to the difference in firing shrinkage during firing.

[0003]

However, the electrode layer is mainly composed of tungsten, molybdenum or other metal, while the ceramic layer is mainly composed of ceramic such as alumina. For this reason, at the time of baking, it is difficult to completely match the baking shrinkage ratios, and eventually, there is a slight discrepancy in the baking shrinkage ratios. On the other hand, when forming a capacitor in a substrate, it is desired to form the capacitor as close to the IC chip mounting surface as possible. This is because the noise removal effect can be enhanced by approaching the IC chip.

For this reason, when the capacitor is formed near the IC chip mounting surface, the electrode layers having different firing shrinkage concentrations are concentrated on the IC chip mounting surface in the thickness direction of the substrate. As viewed in the vertical direction, the firing shrinkage rate becomes non-uniform, and warpage tends to occur after firing. The use of a warped substrate is not preferable because mounting and connecting an IC chip becomes difficult and connection reliability is reduced. In particular, in a ceramic multilayer wiring board for flip chip connection for connecting an IC chip to a bump provided on a substrate surface, in order to make the position of the top of the bump uniform.
Since coplanarity values are often severely limited,
The warpage makes it easy to determine that the product is defective, and lowers the yield.

[0005] However, this warpage defect is caused by providing a cavity (recess) on the surface of the substrate and mounting the IC chip on the bottom of the cavity to perform wire bonding connection or the like, without providing the cavity and providing the surface of the substrate. To IC
A chip-mounting surface is used, and an IC chip is mounted on the surface and flip-chip connection is performed. In the type with a cavity, a ceramic layer is also formed around the cavity, so that even if the capacitor, that is, the electrode layer is located relatively near the center in the thickness direction of the substrate and the firing shrinkage differs, warpage occurs. It is thought that it is difficult.

The present invention has been made in view of the above problems, and is a ceramic multi-layer wiring board having a substantially plate shape, in which a capacitor is built in near a mounting surface of an IC chip while suppressing warpage. An object is to provide a multilayer wiring board.

[0007]

Means for Solving the Problems, Function and Effect The solution of the present invention is a substantially multilayer ceramic multilayer wiring board having a front surface forming an IC chip mounting surface and a back surface thereof.
A capacitor comprising a dielectric layer mainly composed of ceramic and an electrode layer formed on substantially the entire upper and lower surfaces of the dielectric layer is integrally incorporated near the surface, and formed on substantially the entire surface of the ceramic layer. This is a ceramic multilayer wiring board provided with a conductor layer made of substantially the same material as the layer near the back surface.

In the ceramic multilayer wiring board of the present invention having the above structure, the electrode layer of the capacitor is located on the front surface, ie, near the IC chip mounting surface, in the thickness direction of the substrate, but also on the substantially entire surface of the ceramic layer near the back surface. Are provided with a conductor layer of substantially the same material. Therefore, even if there is a difference in the firing shrinkage between the ceramic layer and the electrode layer, the electrode layer is located near the front surface, and the conductor layer of substantially the same material is located near the back surface over substantially the entire surface. The unevenness of the firing shrinkage ratio is balanced in the thickness direction of the substrate, so that a ceramic multilayer wiring substrate with less warpage can be obtained.

Here, the material of the ceramic constituting the substrate may be appropriately selected in consideration of the required strength, electrical characteristics, and the like, and examples thereof include alumina, mullite, aluminum nitride, and glass ceramic. In addition, the wiring may be appropriately selected according to the material of the ceramic, and examples thereof include tungsten, molybdenum, molybdenum-manganese, copper, silver, silver-palladium, and silver-platinum. The dielectric layer is made of the same material (for example, alumina or aluminum nitride) as the ceramic constituting the substrate, or a metal such as tungsten or molybdenum or T
A material whose dielectric constant is increased by adding io2 or the like can be used. One or more dielectric layers can be provided depending on the required capacitance. The electrode layer only needs to be configured to form a capacitor with the dielectric layer interposed therebetween.
At least two layers are formed. Also, an appropriate number of conductor layers may be formed so that the warpage of the substrate is sufficiently small.

Here, it is preferable that the dielectric layer is mainly composed of the ceramic constituting the ceramic layer and to which a metal component constituting the electrode layer is added. As the dielectric layer, there is a case in which a ceramic used for a ceramic layer such as alumina is added with a metal such as tungsten or molybdenum used for an electrode layer to improve the dielectric constant. In this case, a normal ceramic is used. It may be closer to the firing shrinkage of the electrode layer than the layer, and as a result, the firing shrinkage may differ from the ordinary ceramic layer. In this case, not only the electrode layer but also the dielectric layer has a different firing shrinkage from the ceramic layer, so that warpage is likely to occur, but the conductor layer can effectively suppress the warpage.

Further, in the ceramic multilayer wiring board, it is preferable that the conductor layer formed near the back surface is thicker than the electrode layer of the capacitor.

At least two electrode layers are required to constitute a capacitor. Therefore, when only one conductive layer is formed and has the same thickness as the electrode layer, the firing shrinkage cannot be sufficiently balanced, and warpage may not be sufficiently suppressed. Therefore, it is conceivable to increase the number of conductor layers (for example, to increase the number of layers to two or more). However, in order to increase the number of conductor layers, it is necessary to also add a ceramic layer between the conductor layers, thereby increasing cost. become. Further, the thickness of the entire substrate is increased, which may not be preferable. On the other hand, when the thickness of the conductor layer is increased as in the present invention, there is no need to add a ceramic layer, so the cost is hardly changed, and the thickness is the same as the increase in the thickness of the conductor layer. You can stop just increasing it.
Needless to say, the thickness of the conductor layer can be increased and the number of conductor layers can be two or more.

Further, in the above-mentioned ceramic multilayer wiring board, it is preferable that the thickness of the conductor layer is 50 μm or less.

It is preferable to increase the thickness of the conductor layer as described above because addition of a ceramic layer is suppressed. However, since the conductor layer is formed between the ceramic layers, if the thickness of the conductor layer exceeds 50 μm, the lower portion provided in the conductor layer in order to keep insulation from the peripheral portion of the substrate or the penetrating vias. In addition, the adhesiveness between the upper and lower ceramic layers is reduced, and a gap is easily formed between the two, and the insulating property is reduced. Therefore, the thickness of the conductor layer is preferably set to 50 μm or less. Further, the thickness is preferably 30 to 40 μm.

Further, it is preferable that the conductor layer is connected to a ground terminal or a power terminal of the ceramic multilayer wiring board. Usually, most (sometimes about half) of the terminals (flip chip bumps and wire bonding pads) formed on an IC chip are ground terminals and power supply terminals. For example, when the ground potential is set, the ground potential is easily extracted. In addition, since the ground potential and the power supply potential are desired to have low resistance in order to suppress potential fluctuation due to current fluctuation, the conductor layer having a large area is also set to the ground potential and the power supply potential in this regard. And the resistance value drops and IC
The chip can be driven more stably. In particular, it is more preferable that the thickness of the conductor layer be large, because the resistance of the conductor layer itself decreases. Further, it is preferable that at least two conductor layers are provided and connected to one of a ground terminal and a power supply terminal to form a capacitor. It is generally desired that a capacitor built in a substrate has a large capacitance.
This is because a capacitor having a larger capacitance can be obtained.

[0016]

(Embodiment 1) A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a partially enlarged cross-sectional view of the ceramic multilayer wiring board 100 of the present embodiment. Although not shown, the substrate 100 is a square plate having an outer shape of 40 mm square × 1.5 mm thick, and an IC (not shown) is mounted on its surface (IC chip mounting surface, upper surface in the figure) 100a.
A large number of flip chip pads 7 for connecting and mounting chips by a flip chip connection method are formed.
Also, near the periphery of the back surface (the lower surface in the figure) 100b,
Nail head pins 9 made of metal are erected by brazing via a large number of pin pads 8 provided at predetermined intervals to form a so-called PGA type substrate.

This substrate 100 has ceramic layers 1 to 6 made of alumina ceramic having a thickness of about 200 μm. Among them, the ceramic layers 5, 6 near the surface 100a
In the meantime, molybdenum powder is
%, The dielectric constant is increased, and the four dielectric layers 11 to 14 whose thickness is reduced to about 50 μm are formed. Above and below each of the dielectric layers 11 to 14, five electrode layers 21 to 25 each having a thickness of 15 μm and containing tungsten as a main component are formed, and the two constitute the capacitor 10. It is preferable that the thickness of the dielectric layers 11 to 14 is smaller because the capacitance of the capacitor 10 increases. However, if the thickness is less than 20 μm, for example, the insulating property is reduced. Then, it is preferable to select an appropriate thickness of 20 μm or more. The electrode layers 21 to 25
Is substantially all over the dielectric layers 11 to 14, and
0 is formed over almost the entire surface (about 38 mm square) in plan view. This is for increasing the electrode area as much as possible to increase the capacitance of the capacitor 10.

A wiring layer 40 having a thickness of 15 μm and having a predetermined pattern containing tungsten as a main component is formed between the ceramic layers 2, 3, 4, 5 (interlayer). With this, it is connected to the flip chip pad 7. The wiring layer 40 is formed by the via 5
0 is also connected to the pin pad 8. Thereby, each flip chip pad 7 is electrically connected to the pin 9. In the capacitor 10, the electrode layers 21, 23, 23
25 is electrically connected to the flip chip pad 7a by being connected to the via 31, and similarly, the electrode layers 22, 24 are also electrically connected to the flip chip pad 7b by being connected to the via 32.
It is conducting. Further, the electrode layers 11, 13, 15
The electrode layers 12 and 14 are also connected to each other by the vias 34 provided at various locations. This is because the number of connection points between the electrode layers is increased to reduce the resistance of the electrode layers.

On the other hand, between the ceramic layers 1 and 2 near the back surface 100b, a conductor layer 61 containing tungsten as a main component is formed like the electrode layers 21 to 25.
The conductor layer 61 has a thickness of 45 μm and has substantially the same shape (38 mm square) as the electrode layers 21 to 25. However, the electrode layers 21 to 25 have a large number of circular down portions 15 having a diameter of 200 to 300 μm in order to maintain insulation from the vias 30.
They differ from each other in that they have a large number of circular pull-down portions 63 having a diameter of 300 to 500 μm for passing 0.

Although not explicitly shown in FIG. 1, the electrode layers 22,
Reference numeral 24 is connected to a pin (power supply terminal) 9 connected to a power supply potential through a via 32, a wiring layer 40, and a via 50. The electrode layers 21, 23, and 25 are connected to a pin (ground terminal) 9 connected to a ground potential through a via 31, a conductor layer 61, and a via (not shown) connected to the via. As a result, the conductor layer 61 is also set to the ground potential. However, since the conductor layer 61 having a large area and a large thickness has a smaller resistance than the wiring layer 40, by setting the conductor layer 61 to the ground potential, The resistance of the ground potential can be reduced.

In the present embodiment, the thickness of the conductor layer 61 is 45 μm. However, if the thickness of the conductor layer 61 is larger than 50 μm, the distance between the ceramic layers 1 and 2 at the periphery of the conductor layer 61 is reduced. There is a gap in the lower part 63
In such a case, a gap is formed, and problems such as a decrease in insulating property are likely to occur. Therefore, in this embodiment,
The thickness is set to 45 μm which is close to the upper limit. This substrate 1
Five substrates (not shown) having the same shape as that of No. 00 and only the conductor layer 61 were manufactured, and the amount of warpage was measured. The results were as follows. The amount of warpage was measured by measuring the height of the substrate surface on a diagonal line using a surface roughness meter, and taking the difference between the maximum value and the minimum value in the resulting graph as warpage. The larger one of the warpage values was taken as the measured value (actually measured value). The direction of the warp at which the surface 100a of the substrate becomes convex is defined as the positive direction.

[0022]

[Table 1]

As can be seen from Table 1, in the comparative example in which the conductor layer 61 is not formed, the average value is 108 μm, and the warpage is large. This is the ceramic layer 1
5 and the dielectric layers 11 to 14, compared to the electrode layers 21 to
25 and the firing shrinkage of the dielectric layers 11 to 14 are slightly small, so that when viewed in the thickness direction of the substrate 100 (vertical direction in the figure),
It is assumed that the firing shrinkage on the surface 100a side where the electrode layers and the dielectric layers are densely packed becomes relatively unbalanced due to a relatively small shrinkage, and the back surface side shrinks relatively and the front surface side becomes convex and the warpage is large. Conceivable. On the other hand, the warpage of the substrate 100 is as small as 73 μm on average. 38 m of substantially the same shape as the electrode layers 21 to 25 on the back surface 100 b side
Since the conductor layer 61 having an m-square and a thickness of 45 μm and made of substantially the same material was formed, the electrode layers 21 to 25 having a small firing shrinkage and the conductor layer 61 were positioned near the front surface 100a and the back surface 100b. It is considered that the firing shrinkage in the thickness direction was balanced. As described above, according to the present embodiment, even when the capacitor 10 is formed near the front surface (IC chip mounting surface) 100a, the warp deformation is suppressed by forming the conductor layer 61 near the rear surface 100b. Can be. This effect is similarly effective when the firing shrinkage of the electrode layer and the ceramic layer is reversed, that is, when the firing shrinkage of the electrode layer is larger than that of the ceramic layer.

The substrate 100 can be manufactured by the same manufacturing method as that of a conventional ceramic multilayer wiring board. That is, an alumina ceramic green sheet having a predetermined size and a dielectric green sheet formed by kneading alumina powder and molybdenum powder are prepared. Next, through holes are formed in these predetermined positions, and metalized ink containing tungsten as a main component is filled. Further, a metallized ink containing tungsten as a main component is applied in a predetermined pattern to a predetermined thickness by screen printing, and dried. Thereafter, the substrates are stacked in a predetermined order, pressed, and fired to manufacture the substrate 100. However, in the substrate 100 of the present embodiment, it is necessary to apply a thicker (about 2 to 3 times thicker) than usual to form a metallized ink layer to be the conductor layer 61. Therefore, application and drying are repeated several times (for example, three times) to increase the thickness.

(Embodiment 2) Next, a second embodiment of the present invention will be described. The substrate 200 of the present embodiment
Adds a ceramic layer 201 between the ceramic layers 1 and 2 near the substrate back surface 200b, and further adds a ceramic layer 1
And 201, a conductor layer 262 similar to the conductor layer 61 is formed, and is different from the substrate 100 of the first embodiment. Only different parts will be described. The substrate 200 has a ceramic layer 201 added thereto and, like the conductor layer 61,
The electrode layer 21 having a thickness of 45 μm and mainly containing tungsten
A conductor layer 262 having a plane shape substantially the same as the plane shape (38 mm square) of No. 25 to 25 is formed on substantially the entire surface of the ceramic layer 201. The conductor layer 262 maintains insulation from the via 50 by the lowered portion 264.

When the substrate 200 was manufactured and its warpage was measured in the same manner as in the first embodiment, the warpage could be further reduced as shown in Table 1 above. This is presumably because the addition of the conductor layer 262 to the substrate 100 further reduced the firing shrinkage on the back surface 200b side of the substrate, thereby further improving the balance of the firing shrinkage in the thickness direction. As described above, the number of conductor layers may be an appropriate number in consideration of the magnitude of warpage.
In addition, the thickness of the conductor layer may be set to an appropriate thickness in the same manner. It is clear that the substrate 200 can be manufactured by substantially the same method as that of the substrate 100, and a description thereof will be omitted. Further, in the substrate 200, when the electrode layers 22, 24 and the conductor layer 262 are connected by the via 232 which is an extension of the via 32 as shown by the broken line in FIG. 2, the conductor layers 61 and 262 and the ceramic layer 201 are connected. , And the capacitor C. Therefore, the capacitance of the capacitor built in the substrate is increased by the capacitor C, which is more preferable.

In the above, the present invention has been described with reference to the embodiment. However, the present invention is not limited to the above-described embodiment, and it is needless to say that the present invention can be appropriately modified and applied without departing from the gist thereof. Nor. For example, in the above-described embodiment, a PGA type substrate having a large number of pins 9 on the back surfaces 100b and 200b is shown. However, a BGA type substrate having ball-shaped terminals or an LGA having only pads (lands) 8 is also provided. It can also be a mold substrate or the like. In the above-described embodiment, an example in which a large number of flip chip pads 7 are formed on the surfaces 100a and 200a has been described. However, the IC chip is fixed to the surface of the substrate face-up so that wire bonding connection can be performed. A large number of pads may be formed. As the capacitor 10, four dielectric layers 11 to 14 and five electrode layers 21
Although an example including the number of the dielectric layers and the electrode layers is required in consideration of the required capacitance. In the above embodiment, the dielectric layers 11 to 11 are used.
Although the electrode layers 21 to 25 are formed in a square shape on substantially the entire surface of the electrode layer 14, the electrode layer is formed in another shape, for example, a substantially whole square shape in which a central portion of the electrode layer is partially cut out. In this case, the conductor layer may be formed on substantially the entire surface of the ceramic layer in substantially the same shape (for example, a rectangular shape) as the electrode layer.

[Brief description of the drawings]

FIG. 1 is a partially enlarged cross-sectional view of a ceramic multilayer wiring board according to a first embodiment.

FIG. 2 is a partially enlarged sectional view of a ceramic multilayer wiring board according to a second embodiment;

[Explanation of symbols]

100, 200 Ceramic multilayer wiring board 100a, 200a Front surface 100b, 200b Back surface 1, 2, 3, 4, 5, 6, 201 Ceramic layer 7, 7a, 7b Flip chip pad 8 Wire bonding pad 9 Pin 10 Capacitor 11, 12, 13, 14 Dielectric layer 15 Downward portion 21, 22, 23, 24, 25 Electrode layer 30, 31, 32, 33, 34 Via 40 Wiring layer 50 Via 61, 262 Conductive layer 63, 264 Downward portion

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E346 AA13 AA15 AA24 AA43 BB02 BB03 BB04 BB07 BB15 BB16 BB20 CC17 CC18 CC32 CC35 CC36 CC38 CC39 DD07 DD34 EE24 FF18 FF45 GG06 GG09 HH11

Claims (3)

[Claims] 1. A substantially plate-shaped ceramic multilayer wiring board having a front surface forming an IC chip mounting surface and a back surface thereof, wherein the dielectric layer is mainly composed of ceramic, and is formed over substantially the entire upper and lower surfaces of the dielectric layer. A ceramic multilayer wiring board integrally including a capacitor formed of an electrode layer formed in the vicinity of the front surface and being formed on substantially the entire surface of the ceramic layer, and having a conductor layer made of substantially the same material as the electrode layer near the rear surface. 2. The ceramic multilayer wiring board according to claim 1, wherein the conductor layer formed near the back surface is thicker than an electrode layer of the capacitor. . 3. The ceramic multilayer wiring board according to claim 2, wherein said conductor layer has a thickness of 50 μm or less.