JP2000020034A - Picture display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cope with increase in transfer of picture data. SOLUTION: The device is equipped with a display panel 1 in which a scanning signal electrode and an information signal electrode are arranged in matrix, with information signal line drivers 18, 19 arranged on both sides of the display panel 1 so as to impress the information signal to its electrode, and with a drive controller 24 which transfers picture data and the sampling clock to these information signal line drivers 18, 19 on both sides; these drivers 18, 19 sample the picture data from their signals by a sampling clock to generate the information signals. In the above picture display device, sampling is performed in such a manner that the driver 18 on one side samples with the rise timing of the sampling clock and that the driver 19 on the other side samples with the fall timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device having an improved image data transfer technique.

[0002]

2. Description of the Related Art Conventionally, as an image display device, for example,
2. Description of the Related Art A liquid crystal image display device that transfers image data from a liquid crystal drive controller to an information signal line driver and displays an image is known. FIG. 2 is a system block diagram of this conventional liquid crystal image display device. In the figure, reference numeral 1 denotes a liquid crystal display panel in which scanning signal electrodes and information signal electrodes are arranged in a matrix, 2 denotes a segment driver which is an information signal line driver arranged to apply an information signal to the information signal electrodes, 3 Denotes a common driver which is a scanning signal line driver, 4
-1 is an upper segment bus board, 4-2 is a lower segment bus board, 5 is a common bus board, 6 is a liquid crystal drive controller, 7 (7-1, 7-2) is an image data bus, and 8 is an image data sampling clock. Signal (SCLK) line,
9 is an image data input control signal (SDI) line, 10 is a latch signal (LATCH) line, 11 is a common control signal line group,
12 is a graphic controller, 13 is an image data bus, 14 is an image data sampling clock signal (FC
LK) line 15 is an image data transfer enable signal (EN)
ABLE) line, 16 is a horizontal synchronization signal (Hsync) line,
Reference numeral 17 denotes a vertical synchronization signal (Vsync) line.

As shown in FIG. 2, the arrangement of the segment driver 2 of the liquid crystal panel is such that information signal lines are arranged above and below the liquid crystal panel 1 in order to restrict the mounting pitch on the liquid crystal panel 1 and to reduce the frequency of the image data sampling clock. It is a "two-sided arrangement" that takes out and mounts on both sides. for that reason,
Transfer of image data from the liquid crystal drive controller 6 to the segment driver 2 is performed separately using two systems, a transmission line (7-1) for the upper segment driver and a transmission line (7-2) for the lower segment driver. It has been done.

[0004] Then, as shown in FIG.
Segment drivers 2 (2
-1, 2-2,..., 2- (n-1), 2-n) include an image data bus 7, an image data sampling clock signal (SCLK) line 8, and a latch signal (LATCH) line 1.
0 are connected in common, and an image data input control signal (SDI) line 9, SDO * (SDO1,..., SDOn)
Each is cascaded by -1). This SDO * also means a signal output from each segment driver 2 at a timing described later.

The graphic controller 12 receives image data and control signals from the host computer, and sends the image data buses 13 to the liquid crystal drive controller 6 in a predetermined transfer format as shown in FIGS. The signals ID0 to ID35, the sampling clock FCLK, the horizontal synchronization signal Hsync for setting one horizontal scanning period (1H), and the vertical synchronization signal Vsync for setting one frame period are transferred.

Here, the bus width of the image data bus 13 is 36 bits. This means that the display performance of the liquid crystal panel 1 is 262, 1 as a 6-gradation expression for each of R, G, and B colors.
In the case of a 44-color display, each of R, G, and B colors is 6
The data for the upper segment and the data for the lower segment are sent to the liquid crystal panel 1 in two systems, bit by bit.
This is because x6x2 = 36 bits. FIG. 6 is a diagram showing an example of the correspondence between the image data buses ID0 to ID35 and the image data.

As shown in FIG. 4, each image data is represented by a signal E.
Data Va valid during the high period of NABLE
The lid is transferred and sampled by the liquid crystal drive controller 6 at the rising edge of the sampling clock FCLK as shown in FIG. The sampled image data is equivalent to one horizontal scanning period (one scanning line of the liquid crystal panel) at the High timing of the horizontal synchronization signal Hsync.
Is latched by the liquid crystal drive controller 6 as the image data. Before and after the High period of the signals Vsync and Hsync, the signal ENABLE is set to Low, and the image data in this period is invalidated (usually,
The image data during this period is set to Low).

The transfer of control signals and image data from the liquid crystal drive controller 6 to the liquid crystal display panel 1 is performed as follows. That is, the liquid crystal drive controller 6
A scanning timing control signal for the common driver 3 is generated based on the signals Vsync and Hsync from the graphic controller 12 and sent to the common bus board 5 via the common control signal line group 11. The image data sampled and latched by the liquid crystal drive controller 6 as described above is distributed to the upper segment driver data and the lower segment driver data each having a width of 18 bits. Bus 7-
1 and 7-2, the upper segment bus board 4-
1 and the lower segment bus board 4-2.

FIG. 8 shows a conventional upper segment driver 2.
5 shows a method of transferring image data. FIG. 9 is a diagram showing an example of the correspondence between the image data buses IDU0 to IDU17 and the image data at that time. As shown in FIG. 8, the image data is 18 bits wide (IDU0 to IDU17), and all the drivers of the upper segment driver 2 are serially transferred. The first data of the image data, that is, data UD0, UD1,. , UD16 and UD17 are sent, and at the same time, the image data input control signal SDI becomes High. Then, the first segment driver 2-1 of FIG.
Starts sampling the image data at the rising edge of the sampling clock SCLK and starts counting the number of cycles of the clock SCLK. When the image data for the number of output lines × the number of gradations of the segment driver is sampled, for example, in the case of a segment driver having 240 outputs, the clock SCLK is set to 8
When 0 counts (240 lines × 6 gradation data / 18-bit bus = 80), the first segment driver 2-1
Completes the sampling of the image data, and outputs the image data input control signal SDO to the second segment driver.
1 is set to High. Second segment driver 2-2
Is the data UD144 after the signal SDO1 becomes High in the same manner as the first segment driver 2-1.
., UD1441,..., UD1456, and UD1457 are sampled. Thereafter, similarly, the third, fourth,... Segment drivers 2-3, 2-
.. Perform sampling of image data.

As described above, conventionally, in the transfer of image data, the data for the upper segment driver and the data for the lower segment driver are transferred by the same transfer method as shown in FIG.
Upper and lower image data buses 7-1 and 7-2
Via another system. In the transfer of the image data from the liquid crystal drive controller 6 to the segment driver 2, the sampling of the image data is always performed only at the rising edge or the falling edge of the sampling clock SCLK. ), The sampling clock of the image data requires twice the frequency of the data transfer frequency.

[0011]

By the way, as the number of display colors and the definition of a liquid crystal panel increase, the image data from the graphic controller 12 to the liquid crystal drive controller 6 and from the liquid crystal drive controller 6 to the segment driver 2 are increased. The transfer volume is steadily increasing. In order to cope with the transfer of more image data, it is possible to simply increase the data transfer bus width or increase the data transfer frequency.

However, if the bus width is widened, problems such as wiring routing on a printed circuit board, an increase in the number of connection cables, and an increase in connectors will arise. On the other hand, increasing the clock frequency or the data transfer frequency increases unnecessary radiation noise, increases the power consumption of the system, and increases the transmission line impedance characteristics due to the shape of the segment bus board 4 shown in FIG. There is a problem, and considering the propagation delay of a signal, there is a limit in increasing the frequency.

An object of the present invention is to provide an image display apparatus capable of coping with an increase in the transfer amount of image data without causing the above-mentioned problems in view of the problems of the prior art.

[0014]

According to the present invention, there is provided a display panel in which scanning signal electrodes and information signal electrodes are arranged in a matrix, and a display panel for applying an information signal to the information signal electrodes. An information signal line driver disposed on both sides of the display panel; and a drive controller for transferring image data and a sampling clock thereof to the information signal line drivers on both sides. The information signal line drivers on both sides are provided by the sampling clock. In an image display device which generates the information signal by sampling image data from a signal of image data, an information signal line driver on one side performs the sampling at a rising timing of the sampling clock, and an information signal on the other side. The line driver sets the timing of the falling edge of the sampling clock. Characterized in that it is intended to perform the sampling at.

[0015] According to this, the information signal line driver on one side performs the sampling of the image data, which has conventionally been performed only at either the rising edge or the falling edge of the sampling clock, at the timing of the rising edge of the sampling clock. Since the information signal line driver on the other side is performed at the timing of the falling edge of the sampling clock, the data transfer path for the image data is unified (the bus width is reduced), and the image data is transferred without increasing the sampling clock frequency. An image display device capable of coping with an increase in the amount of image data transferred due to multi-color display, high definition, and the like is achieved.

[0016]

In a preferred embodiment of the present invention, the signal of the image data is common to the information signal line drivers on each side including image data for the information signal line drivers on each side alternately. The sampling clock has the same frequency as the transfer frequency of the image data. The transfer of image data to the information signal line drivers on both sides is performed by the same image data bus. In this case, if the frequency of the sampling clock is the same as the conventional one, the bus width of the image data from the drive controller can be reduced to half.

As the information signal line drivers on both sides,
It is possible to use a driver having the same configuration that can set whether sampling of image data is performed at the timing of the rising edge or the timing of the falling edge of the sampling clock. Further, the information signal line drivers on both sides have the same configuration, and whether to perform sampling of image data at the rising edge timing or at the falling edge timing of the sampling clock is set by a hard pattern at the time of mounting. It may be something. Specifically, this can be realized by providing an inverter for the sampling clock in the information signal line driver on one side and providing a buffer for the sampling clock in the information signal line driver on the other side. As the display panel, for example, a liquid crystal panel such as a ferroelectric liquid crystal panel can be used.

[0018]

[Embodiment 1] FIG. 1 is a system block diagram of a liquid crystal device according to a first embodiment of the present invention. In the figure, 1 is a liquid crystal display panel in which scanning signal electrodes and information signal electrodes are arranged in a matrix, and 18 and 19 are upper segment drivers and lower segment drivers arranged to apply information signals to the information signal electrodes. , 20 is a common driver, 21-1 is an upper segment bus board, 21-
2 is a lower segment bus board, 22 is a common bus board,
23-1 is a common / upper segment connection line group, 23-
2 is a common / lower segment connection line group, 24 is a liquid crystal drive controller that transfers image data and the like to the segment drivers 18 and 19, 25 is a segment common data bus, and 26 is an image data sampling clock signal (SC).
LK) line, 27 is an upper segment image data input control signal (USDI) line, 28 is a lower segment image data input control signal (LSDI) line, and 29 is a latch signal (LAT).
CH) line, 30 is a common control signal line group, 31 is a graphic controller, 32 is an image data bus, 33 is an image data sampling clock signal (FCLK) line, 34
Is an image data transfer enable signal (ENABLE) line,
Reference numeral 35 denotes a horizontal synchronization signal (Hsync) line, and reference numeral 36 denotes a vertical synchronization signal (Vsync) line.

Image data and signals SCLK, USDI, LATCH transmitted from the liquid crystal drive controller 24 via the data bus 25 and the signal lines 26, 27, 29
Is connected from the common bus board 22 to the upper segment bus board 2 via the common / upper segment connection line group 23-1.
1-1. Similarly, the liquid crystal drive controller 2
4 and the image data and signals SCLK and LS transmitted from the data bus 25 and the signal lines 26, 28 and 29.
DI and LATCH are supplied from the common bus board 22 to the lower segment bus board 21-2 via the common / lower segment connection line group 23-2.

As shown in FIG. 10, each upper segment driver 18-
, 18-n are connected to the segment common data bus 25 and the image data sampling clock signal (SC).
LK) line and the latch signal (LATCH) line are connected in common, and the upper segment image data input control signal (USDI) line 27 and USDO * (USDO) line are connected.
1,..., USDOn-1) are cascaded. USDO * also means a signal output from each upper segment driver 18 at a timing described later.

The transfer of image data from the graphic controller 31 to the liquid crystal drive controller 24 is performed in the same manner as in the above-described conventional example.

The transfer of control signals and image data from the liquid crystal drive controller 24 to the liquid crystal display panel 1 will be described below. The liquid crystal drive controller 24 receives the common driver 20 from the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync from the graphic controller 31.
Of the common control signal line group 3
0 to the common bus board 22.

On the other hand, the graphic controller 3 sampled and latched by the liquid crystal drive controller 24
The image data from 1 is shared by the segment common data bus 2
5, common bus board 22, common / upper segment connection line group 23-1, common / lower segment connection line group 2
3-2, via the upper segment bus board 21-1
And transferred to the lower segment bus board 21-2.

FIG. 11 shows a method of transferring image data to each segment driver 18. As shown in the figure, the image data has an 18-bit width (SCID0 to SCID17),
The upper segment data (UD *) and the lower segment data (LD *) are serially transferred alternately via the image data bus 25. First data of the image data, that is, upper segment data UD0, U
, UD16, UD17 are sent, and at the same time, the upper segment image data input control signal USDI is set to Hig.
h. Then, the first segment driver 1 shown in FIG.
8-1 starts sampling the image data at the rising edge of the sampling clock SCLK and starts counting the number of cycles of the clock SCLK. When the sampling of the image data of the number of outputs × the number of gradations of the segment driver 18 is completed, for example, when the number of outputs is 240, the first upper segment driver 18-1 is counted at the time of counting 80 clocks SCLK. Completes the sampling of the image data, and sets the image data input control signal USDO1 to the second upper segment driver 18-2 to High. The second upper segment driver 18-2 outputs the signal USDO1 at the H level.
the first upper segment driver 1
8-1, the image data UD1440, UD1
,..., UD1456, and UD1457 are sampled. Thereafter, similarly, the third,
Fourth,... Upper segment drivers 2-3, 2-4,.
Also performs sampling of image data.

On the other hand, as shown in FIG. 11, when the lower segment data LD0, LD1,..., LD16, LD17 are sent and the lower segment image data input control signal LSDI goes High, as shown in FIG. First
The lower segment driver 19-1 starts sampling the image data at the falling edge of the sampling clock SCLK and starts counting the number of cycles of the clock SCLK. Thereafter, like the upper segment driver 18, the lower segment driver 1
9 is performed to sample the image data.

As described above, in the sampling of the image data in the image data transfer from the liquid crystal drive controller 24 to the segment drivers 18 and 19,
The upper segment driver 18 has a sampling clock S
At the timing of the rising edge of CLK, the lower segment driver 19 performs sampling at the timing of the falling edge of the clock SCLK, so that the frequency of the sampling clock SCLK and the transfer frequency of the image data are the same.

Compared with the conventional example, since the data for the upper segment and the data for the lower segment are transferred on the same bus via the common bus board and sampled at both the rising and falling edges of the sampling clock, The bus width between the drive controller and the liquid crystal panel is halved, and the frequency of the sampling clock is the same.

That is, the sampling of the image data, which was conventionally performed only at either the rising edge or the falling edge of the sampling clock, is mounted on both sides of the liquid crystal panel by setting the sampling clock frequency and the data transfer frequency to be the same. In the segment driver, one segment driver performs the timing at the rising edge of the sampling clock and the other segment driver performs the timing at the falling edge, so that the data transfer path is integrated into one system (reducing the bus width) and sampling is performed. Without increasing the clock frequency, it is possible to realize optimal image data transfer in order to cope with multi-color display and high definition of the liquid crystal panel.

In this embodiment, the upper segment driver 1
8 is used for sampling on the rising edge and the lower segment driver 19 is used for sampling on the falling edge, thus requiring a separate and different segment driver. According to Example 2 below, The same effect can be obtained by using the same segment driver for the upper side and the lower side.

[Embodiment 2] FIGS. 13 and 14 are connection diagrams of upper and lower segment drivers in a liquid crystal image display device according to a second embodiment of the present invention. Upper segment drivers 18-1, 18-2, ..., 18- (n-
1), 18-n and lower segment driver 19-
, 19- (n-1) and 19-n are the same as those in FIGS. The input signals are the same as those in FIGS. 10 and 12 except for the following points.

That is, as shown in FIG. 13, the sampling clock (SCL) to the upper segment driver 18 is
K) A buffer 131 is provided on a line 26, and an inverter 14 is provided on a sampling clock (SCLK) line 26 for the lower segment driver 19, as shown in FIG.
1 is inserted. The buffer 131 is the inverter 14
1 is inserted to make the delay time equal to 1. The same driver (driver performing rising edge sampling) is used for the upper and lower segment drivers by inverting the polarity of the sampling clock SCLK by the inverter 141 and performing data sampling and clock counting with the inverted clock. Thus, the same effect as in the first embodiment can be obtained.

[Embodiment 3] FIG. 15 is a block diagram showing a configuration of a segment driver in a liquid crystal image display device according to a third embodiment of the present invention. In the figure, reference numeral 37 denotes an image data sampling clock SCLK and a latch signal LATC.
H and image data input control signals SDI (USDI, L
SDI, USDO *, LSDO *), and a control circuit for controlling the timing of sampling and latching of image data.
A data multiplexer for receiving image data from 5;
9 is a data latch for latching data from the data multiplexer 38, 40 is a level shifter circuit for converting the data of the data latch 39 to a predetermined liquid crystal panel drive voltage,
41 is a driver circuit for driving the liquid crystal panel.

The segment driver 18 or 19 uses a terminal SDP to set the direction of the sampling edge,
That is, the configuration is such that it is possible to set whether to perform sampling at the rising timing or the falling timing of the sampling clock.

FIG. 16 shows the upper segment driver 18.
(18-1, 18-2, ..., 18- (n-1), 18-
FIG. 17 shows the lower side segment driver 19.
(19-1, 19-2, ..., 19- (n-1), 19-
It is a connection diagram of n). For example, as shown in FIGS. 16 and 17, it can be set via the terminal SDP to perform “rising edge sampling” by pulling up to the logic potential VDD and “falling edge sampling” by pulling down to the ground potential. By doing so, the same effect can be obtained without an external buffer or inverter as in the second embodiment.

[0035]

As described above, according to the present invention, the sampling of the image data, which has conventionally been performed only at either the rising edge or the falling edge of the sampling clock, is performed by the segment driver on one side. And the segment driver on the other side is performed at the falling edge timing, so that the data transfer path for image data from the drive controller is integrated into one system (reducing the bus width) and the sampling clock It is possible to realize an image display device that can appropriately cope with an increase in the amount of image data due to multi-color display and high definition of the liquid crystal panel without increasing the frequency.

[Brief description of the drawings]

FIG. 1 is a system block diagram of a liquid crystal image display device according to a first embodiment of the present invention.

FIG. 2 is a system block diagram of a conventional liquid crystal image display device.

FIG. 3 is a connection block diagram of a segment driver of the liquid crystal image display device of FIG. 2;

FIG. 4 is a signal transfer format diagram from a graphic controller to a liquid crystal drive controller of the liquid crystal image display device of FIG. 2;

FIG. 5 is a reduced signal transfer format diagram from a graphic controller to a liquid crystal drive controller of the liquid crystal image display device of FIG. 2;

FIG. 6 is a diagram illustrating an example of correspondence between image data and image data from a graphic controller to a liquid crystal drive controller.

FIG. 7 is an enlarged signal transfer format diagram from a graphic controller to a liquid crystal drive controller of the liquid crystal image display device of FIG. 2;

FIG. 8 is a signal transfer format diagram from a liquid crystal drive controller to a segment driver of the liquid crystal image display device of FIG. 2;

FIG. 9 is a diagram showing an example of correspondence between an image data bus from a liquid crystal drive controller to a segment driver and image data.

FIG. 10 is a connection block diagram of an upper segment driver of the liquid crystal image display device of FIG. 1;

11 is a signal transfer format diagram from a graphic controller to a liquid crystal drive controller of the liquid crystal image display device of FIG. 1;

FIG. 12 is a connection block diagram of a lower segment driver of the liquid crystal image display device of FIG. 1;

FIG. 13 is a connection block diagram of an upper segment driver of a liquid crystal image display device according to a second embodiment of the present invention.

14 is a connection block diagram of a lower segment driver in the embodiment of FIG.

FIG. 15 is a block diagram illustrating a configuration of a segment driver in a liquid crystal image display device according to a third embodiment of the present invention.

16 is a connection block diagram of the upper segment driver in the embodiment of FIG.

17 is a connection block diagram of a lower segment driver in the embodiment of FIG.

[Explanation of symbols]

1: liquid crystal display panel, 2: segment driver, 3: common driver, 4: segment bus board, 5: common bus board, 6: liquid crystal drive controller, 7: image data bus, 8, 26: image data sampling clock signal (SCLK) ) Line, 9: segment image data input control signal (SDI) line, 10, 29: latch signal (LATC)
H) line, 11, 30: common control signal line group, 12, 3
1: graphic controller, 13, 32: image data bus, 14, 33: image data sampling clock signal (FCLK) line, 15, 34: enable signal (E)
NABLE) lines, 16, 35: horizontal synchronization signal (Hsyn)
c) lines, 17, 36: vertical synchronization signal (Vsync) line,
18: upper segment driver, 19: lower segment driver, 20: common driver, 21: segment bus board, 22: common bus board, 23: common-segment connection line group, 24: liquid crystal drive controller, 25:
Segment common data bus, 27: upper segment image data input control signal (USDI) line, 28: lower segment image data input control signal (LSDI) line, 37: control circuit, 38: data multiplexer, 39:
Data latch, 40: level shifter circuit, 41: driver circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA11 NA43 NA53 NA64 NC12 NC16 NC23 NC26 NC27 ND06 ND17 ND20 ND34 ND39 ND40 ND52 NF19 5C006 AF51 BA12 BB11 BC13 BF04 BF11 BF27 FA13 FA42 FA48 5C080 AA12 BB23 DD02 DD08 DD08

Claims (7)

[Claims] A display panel on which scanning signal electrodes and information signal electrodes are arranged in a matrix; information signal line drivers arranged on both sides of the display panel so as to apply information signals to the information signal electrodes; A drive controller for transferring image data and its sampling clock to the information signal line drivers on both sides; the information signal line drivers on both sides sample image data from the image data signal by the sampling clock to produce the information signal. The information signal line driver on one side performs the sampling at the rising timing of the sampling clock, and the information signal line driver on the other side performs the sampling at the falling timing of the sampling clock. Specially Image display device. 2. The signal of the image data is common to the information signal line drivers on each side including image data for the information signal line drivers on each side alternately, and the sampling clock is a signal of the image data. The image display device according to claim 1, wherein the image display device has the same frequency as the transfer frequency. 3. The image display device according to claim 1, wherein the transfer of the image data to the information signal line drivers on both sides is performed by the same image data bus. 4. The information signal line driver on both sides is a driver having the same configuration that can set whether to perform sampling of image data at a rising edge timing or a falling edge timing of a sampling clock. The image display device according to claim 1, wherein: 5. The information signal line drivers on both sides have the same configuration, and whether to perform sampling of image data at the rising edge timing or at the falling edge timing of a sampling clock is determined by a hard pattern at the time of mounting. The image display device according to claim 1, wherein the image display device is set. 6. The image display device according to claim 1, wherein the display panel is a liquid crystal panel. 7. The image display device according to claim 6, wherein said liquid crystal panel is a ferroelectric liquid crystal panel.