JP3416045B2 - Liquid crystal display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a technique for transferring display data to a data driver.

[0002]

2. Description of the Related Art A conventional liquid crystal display device is a liquid crystal controller for converting an input video signal and a synchronizing signal into a signal corresponding to each driver in the device, and a drive voltage corresponding to display data. , And a data driver for outputting to the liquid crystal panel. A plurality of data drivers are provided in a liquid crystal display device that performs high-resolution display. The display data generated by the liquid crystal controller is transferred to the data driver via the data bus and displayed. For example,
In a liquid crystal display device that displays 260,000 colors (64 gradations for each of R, G, and B), 1994 SID (SOCIETY FOR INFORMATION)
DISPLAY) INTERNATIONAL SYMPOSIUM DIGEST OF TECHNIC
As described in the paper 23.2 of AL PAPERS VOLUME XXV, the liquid crystal controller and a plurality of data drivers are connected by a common data bus of 18 bits (6 bits for each of R, G, B), Display data was transferred via the data bus.

A specific example of such a liquid crystal display device will be described with reference to FIGS.

As shown in FIG. 2, this liquid crystal display device has
It has a liquid crystal panel 204, a liquid crystal controller 201, a scan driver 203, a plurality of data drivers 202, a data bus 207, and synchronization signal groups 208 to 212.
Here, the liquid crystal panel 204 has a resolution of 1024 × 76.
8 pixels (1 pixel consists of 3 dots of R, G, B),
Display of 262144 colors (64 gradations for each of R, G, and B) is possible. The data driver 202 has 8
Individually provided and commonly connected to the data bus 207.

The liquid crystal controller 201 receives the display data 205 and the sync signal group 206 from a system device such as a personal computer, and outputs various sync signals and display data 207 corresponding to the driver. Display data 2
05 is input at a speed of 65 to 75 MHz via a bus having a width of 18 buses. The sync signal to be output includes a data transfer clock 208 (CL2) and a data horizontal sync signal 209.
(CL1), a frame synchronization signal 211 (FLM), a scanning horizontal synchronization signal 212 (CL3), and a data valid signal 210 which gives a display data transfer period.

The data bus 207 to which the eight data drivers 102 are connected is a high load transmission path and is represented by the equivalent circuit shown in FIG. When the display data is transferred on the data bus 207 at the same speed as the transfer rate (65 to 75 MHz) of the display data 205 from the system unit, waveform rounding or reflection occurs, and the data driver outputs normal data. It becomes impossible to capture. Therefore, the data bus 207 has, for example, a double bus width of 36.
32.5 to 37.5M, which is 1/2 and the transfer speed is 1/2
It is set to Hz. Further, the liquid crystal controller 201 parallelizes the input display data 205 into a set of two pixels and transfers the set.

As shown in FIG. 3, each data driver 202 includes a buffer circuit 301 and an enable control circuit 30.
2, latch address generation circuit 303, latch circuit 304
And 305, and a liquid crystal drive circuit 306. When the data valid signal 210 output from the liquid crystal controller 201 becomes valid, the latch address generation circuit 303 in the frontmost data driver 202-1 starts generating the latch signal, and the display data of the data bus 207 is sequentially latched by the latch circuit. Latch 304. When all the display data shared by the own driver is latched by the latch circuit 304, the enable control circuit 302 causes the next-stage data driver 202-2.
To enable the data valid signal 210-2 to be supplied to start data fetching. As a result, each data driver 202 sequentially fetches the corresponding display data,
The display data for one line is latched by the eight data drivers 202. Then, the data horizontal synchronization signal 209
According to (CL1), in each data driver 202, the latch circuit 305 simultaneously latches the latch output of the latch circuit 304, the liquid crystal drive circuit 306 generates the liquid crystal drive voltage corresponding to this display data, and the liquid crystal panel 204 displays the liquid crystal drive voltage. Output. Then, a display corresponding to the liquid crystal drive voltage is displayed on the line selected by the scan driver 203.
The above operation is sequentially repeated for each line of the liquid crystal panel 204.

[0008]

Particularly, in a laptop computer, it is required to reduce a frame portion (frame) surrounding a liquid crystal panel of a liquid crystal display device. For example, the frame width of the upper part of the liquid crystal panel needs to be at least as wide as the width of the data driver and the width of the data bus.

However, in the above-mentioned conventional technique, in order to transmit normal display data to the data driver, it is necessary to widen the bus width of the data bus to reduce the transfer speed. Therefore, it is difficult to reduce the width of the frame of the liquid crystal panel. As the display resolution becomes higher, the bus width of the data bus needs to be wider, and the above problem becomes more serious.

Therefore, it is an object of the present invention to provide a liquid crystal display device capable of supplying signals to a plurality of data drivers with a smaller number of transmission lines.

[0011]

In order to achieve the above object, the present invention provides a liquid crystal panel, a plurality of data drivers for applying a gray scale voltage corresponding to input display data to the liquid crystal panel, and the liquid crystal. A scan driver that sequentially selects the scan lines of the panel, a liquid crystal control circuit that supplies synchronization signals and display data to the data driver and the scan driver, and the liquid crystal control circuit and each data driver are connected in series to display A plurality of transmission lines that transmit data and a clock for data transfer, the data driver is inserted between the transmission lines on the input side and the output side, and the impedance of the transmission line on the input side is the output side. Characterized by having an impedance cutoff circuit that does not affect the impedance of the transmission line To provide a liquid crystal display device.

According to such a liquid crystal display device, it is possible to increase the transmission speed of the transmission line and reduce the number of transmission lines accordingly.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described below with reference to FIGS. 1 and 6 to 13.

FIG. 1 is a diagram showing the configuration of the liquid crystal display device according to the present embodiment. As shown, the liquid crystal display device
LCD controller 101, multiple data drivers 10
2, the scan driver 103, the liquid crystal panel 104, and
It has a data bus 107.

In the present embodiment, the liquid crystal panel 104 is displayed with a resolution of 1280 × 1024 pixels (one pixel is composed of 3 dots of R, G, B) and 16777216 color display (R,
Each of G and B has 256 gradations. Ten data drivers 102 are provided, and each of them shares display of 128 pixels. The data bus 107 has a bus width of 2
It has 4 bits (8 bits for each of R, G, and B) and simultaneously transmits display data for one pixel. In addition,
This bus width is the same as the display data bus 105 input to the liquid crystal controller 101.

The data bus 107 is the liquid crystal controller 1
01 and all the data drivers 102 are connected in series. That is, the data bus 107-1 is provided between the liquid crystal controller 101 and the data driver 102-1 and the data bus 10 is provided between the data drivers 102-1 and 102-2.
7-2, ..., Data drivers 102-9 and 102-
The data buses 107-10 are connected to each other. Similarly, the transmission line (108-
1 to 108-10) also connects the liquid crystal controller 101 and all the data drivers 102 in series.

FIG. 6 shows the configuration of the data driver 102. In the figure, 601 is an enable control circuit for managing the display data acquisition period, 602 is an input / output buffer circuit for the data bus 107, and 603 is the data transfer clock 1.
08 input / output buffer circuit, 604 a latch address generation circuit for generating a display data latch signal, 605
Is a latch circuit for sequentially latching display data from the data bus 107, 606 is a latch circuit for simultaneously latching the latch output of the latch circuit 605 in one line cycle, and 607 is a liquid crystal drive voltage based on the latch output of the latch circuit 606. It is a liquid crystal drive circuit that operates.

The input / output buffer circuit 602 is provided for each transmission line of the data bus 107. Further, the input / output buffer circuits 602 and 603 have an impedance blocking function that prevents the impedance of the input side transmission line from affecting the impedance of the output side transmission line, and shapes and outputs the transmission signal into a normal waveform. .

FIG. 7 shows the configuration of the liquid crystal controller 101. In the figure, 701 is a liquid crystal display control signal generation circuit for generating a synchronizing signal for liquid crystal driving based on the inputted synchronizing signal group 106, and 702 is a liquid crystal driving display by adjusting the timing of the input display data 105. A liquid crystal display data timing control circuit for generating data, and an output buffer circuit 703 for outputting various generated signals to the outside.
The output buffer circuit 703 includes a plurality of buffer circuits provided for each transmission line of the data bus 107.

Here, the input synchronizing signal group 106 includes a vertical synchronizing signal VSYNC and a horizontal synchronizing signal HSYNC.
C, data clock DCLK, and DTMG are included. The data transfer clock 108 (CL2) and the data horizontal sync signal 10 are included in the output sync signal group for driving the liquid crystal.
9 (CL1), a frame synchronization signal 111 (FLM), a scanning horizontal synchronization signal 112 (CL3), and a data valid signal 110 indicating a display data transfer period.

Next, the operation of the liquid crystal display device of this embodiment will be described with reference to FIG.

The liquid crystal controller 101 includes display data 105 and synchronization signal group 1 from a system device such as a personal computer.
06, and synchronizing signal groups 108 to 11 for driving the liquid crystal.
2 and display data 107 are output. Display data to be output is in 1-pixel units (24 bits) on the data bus 107.
Transferred to. Among the signals output from the liquid crystal controller 101, the high-speed display data (107-1) and the data transfer clock 108-1 are sequentially transferred from the data driver 102-1 in the first stage to the data driver 102-10 in the last stage. To be done.

Each data driver 102 has a display data 107 and a data transfer clock 10 as shown in FIG.
8 is supplied, and when the display data shared by the driver 102 is completely taken in, the input / output buffer circuits 602 and 6
The display data 107 and the data transfer clock 108 are started to be output to the data driver 102 of the next stage via 03. The fact that the data transfer to the own driver 102 has started can be known from the data valid signal 110 output from the liquid crystal controller 101 or the data driver 102 in the preceding stage. By repeating the above operation, the display data for one line is latched by the ten data drivers 102 in one cycle of the data horizontal synchronizing signal 109.

The operation of the data driver 102 will be described in more detail. In FIG. 6, when the input data valid signal 110-IN becomes valid (low level),
The latch address generation circuit 604 starts generation of the latch signal 611 in synchronization with the input data transfer clock 108-IN, and displays the display data 107-IN for 128 pixels.
Is latched by the latch circuit 605 pixel by pixel.

When the display data for 128 pixels is latched, the enable control circuit 601 validates the data valid signal 110-OUT output to the data driver 102 in the next stage. At the same time, the enable control circuit 601
Enables the output circuits of the input / output buffer circuits 602 and 603, and the input data transfer clock 108-
The IN and the display data 107-IN start to be output as the data transfer clock 108-OUT and the data bus 107-OUT.

When the display data for one line is latched by the ten data drivers 102, the latch outputs of the latch circuit 605 are simultaneously latched by the latch circuit 606 in synchronization with the data horizontal synchronizing signal 109. LCD drive circuit 6
07 is a latch output of the latch circuit 606 (display data)
The liquid crystal drive voltage 113 corresponding to
Is generated by using the above, and is output to the liquid crystal panel 104.

The scan driver 103 sequentially applies the selection voltage to the liquid crystal panel 104 line by line in synchronization with the scan horizontal synchronization signal 112, and applies the selection voltage to all the lines in one cycle of the frame synchronization signal 111. . Then, on the line to which the selection voltage is applied, the data driver 102
Color display is performed according to the liquid crystal drive voltage 113 output from the.

Next, a specific example of the signal interface used to transfer the display data 107 and the data transfer clock 108 will be described with reference to FIGS. 9 to 11.

The signal interface indicates an input / output system including a transmission line (for example, data bus 107) and buffer circuits (for example, buffer circuits 703 and 602) connected to both ends thereof. The buffer circuits 602 and 603 of the data driver 102 have the same configuration, and both are composed of an input buffer circuit and an output buffer circuit. This output buffer circuit has a common configuration with the buffer circuit 703 of the liquid crystal controller 101. Therefore, the location of the buffer circuit will not be explicitly described in the following description.

FIG. 9 is a diagram showing a circuit configuration of the signal interface. In the circuit configuration shown in the figure, the output buffer of the CMOS outputs V in accordance with the input signal (for example, display data).
Switch to GND (ground potential) or Vcc. The input buffer circuit connected to the output buffer via the transmission line (for example, the data bus 107) makes a logical determination of the transmission voltage by the CMOS transistor.

FIG. 10 shows another example of the signal interface. The signal interface shown in the figure is, for example, GTL (Gunni
ng tranceiver logic) and other open drain type configurations. ON / OF of transistor of output buffer circuit
The level of the transmission line voltage input to the input buffer circuit by F is the voltage V1 or V which is approximately equal to the voltage Vter.
Change to voltage V2 which is smaller than 1 by a certain amount (here, VGND
<V2 <Vref <V1 <Vcc. The input buffer circuit uses the reference voltage Vref as a threshold value to make a logical determination of the transmission voltage. According to this configuration, since the change width of the transmission line voltage can be reduced, high-speed data transmission becomes possible.

FIG. 11 shows another implementation example of the signal interface. The signal interface shown has a push-pull type configuration. Turning on the transistor of the output buffer circuit
By turning on / off, the level of the transmission line voltage input to the input buffer circuit is a voltage Vter larger than the voltage Vter by a predetermined amount.
1 or a voltage V2 smaller than the voltage Vter by a predetermined amount (here, VGND <V2 <Vter, Vref <V1
<Vcc). The input buffer circuit uses the reference voltage Vref as a threshold value to make a logical determination of the transmission voltage. According to this configuration, the change width of the transmission line voltage can be made small like the signal interface of FIG. 10, so that high-speed data transfer is possible.

As described above, in the present embodiment, all the data drivers 102 are connected in series by the data bus 107, and the transfer signal is transferred to the next stage via the buffer circuit. It is represented by the equivalent circuit shown in FIG. As shown in the figure, the load on the transmission line between the buffer circuits is significantly reduced as compared with the conventional example. Therefore, in the data bus 107, waveform rounding and reflection are alleviated, and signal transmission can be performed more reliably and faster than in the conventional example. That is, according to the present embodiment, the data bus 10
It is possible to increase the transmission speed at 7 or the like, and it is possible to supply a signal to the data driver by a smaller number of transmission lines. Then, by reducing the number of transmission lines, the outer frame of the liquid crystal panel can be narrowed.

In addition, in the present embodiment, the number of transmission lines is reduced, and since the data driver 102 that has not finished fetching the display data 107 does not transmit to the next stage, the power consumed for signal transmission is also reduced. Will be reduced.

Next, regarding the second embodiment of the present invention,
This will be described with reference to FIGS. 13 to 15.

In the liquid crystal display device according to the present embodiment, the buffer circuit in the data driver and the control method thereof are different from those in the first embodiment. In the following, the configuration and operation different from those of the first embodiment will be mainly described.

FIG. 13 shows the data driver 1 of this embodiment.
The configuration of No. 02 is shown. As shown, the data driver 102 includes input / output buffer circuits 1302 and 13 having output buffer circuits that invert the logic level of transfer signals.
03 and an exclusive OR circuit (Ex-OR) inserted into the output side of the input buffer circuit. The other components have the same functions as in the first embodiment.

Ex-OR is for returning the logic level of the signal taken in by the driver 102 to the original logic level. The Ex-OR outputs the output of the input buffer circuit as it is according to the DREV signal or outputs it after inverting the logic level. In this embodiment, odd-numbered data drivers (102-1, 102-3, ...)
In the Ex-OR, the input signal is output as it is, and in the even-numbered data drivers (102-2, 102-4, ...) The Ex-OR inverts the logic level of the input signal and then outputs it. Since the logic level of the DREV signal is fixed at each data driver 102, a corresponding voltage (Vcc or VGND) is supplied to the input terminal of the DREV signal by wiring on the substrate, for example.

The operation of the data driver 102 of this embodiment will be described. The display data 107 and the data transfer clock 108 input to the data driver 102 are
The logic level is the same as when the liquid crystal controller 101 outputs the signal, which is output from the Ex-OR and latched by the latch circuit 1305. When all display data 107 to be shared is latched, the control signal 13 of the enable control circuit 1301
01 allows input / output buffer circuits 1302 and 130
The output buffer circuit of No. 3 is enabled, and the input display data 107 and the data transfer clock 108 have their logic levels inverted, and then the data driver 102 of the next stage.
Transferred to. The same operation is repeated in each data driver 102, and the display data 107 for one line is latched by the latch circuits 1305 of all the data drivers 102.
The subsequent operation is similar to that of the first embodiment.

When pulse transmission is performed by connecting multiple buffer circuits of the same structure that do not invert the logic level, the duty ratio of the transmission pulse changes. For example, when the buffer circuit has a slow response characteristic at the rising edge compared to the falling edge of the transmission pulse, the rising edge of the transmission signal is delayed each time the signal passes through the buffer circuit, as shown in FIG. Transmission quality is degraded due to the reduction in pulse width.

In the present embodiment, as shown in FIG. 15, the logical level of the transmission signal (display data 107 and data transfer clock 108) is inverted every time it passes through the output buffer circuit of the data driver 102. It is possible to prevent one of the rising edge and the falling edge from being extremely delayed. Therefore, according to the present embodiment, the transmission quality is improved as compared with the first embodiment, and it becomes easier to increase the speed of the transmission signal and reduce the bus width of the data bus 107.

Next, regarding the third embodiment of the present invention,
This will be described with reference to FIGS. 16 and 17.

In this embodiment, each signal (1 bit) of the display data 107 and the data transfer clock 108 is transmitted by two signals (hereinafter referred to as differential signals) whose signal polarities are mutually inverted. However, it is different from the first embodiment. Hereinafter, the functions and operations different from those of the first embodiment will be mainly described.

FIG. 16 shows the data driver 1 of this embodiment.
The configuration of No. 02 is shown. The data driver 102 includes a differential input / output buffer circuit 16 for transmitting / receiving a differential signal.
02 and 1603 and a PLL circuit 1616 for generating a high-speed clock based on the data transfer clock 108.
And a serial / parallel conversion circuit 1617 for parallelizing the output signal of the differential input / output buffer circuit 1602. The other components have the same functions as in the first embodiment.

FIG. 17 shows the configuration of the liquid crystal controller 101 of this embodiment. This liquid crystal controller 101 is
A liquid crystal display data parallel / serial control circuit 1702 that generates display data for driving liquid crystal by timing control and serialization of the input display data 105, and a PLL circuit 1704 that generates a high-speed clock based on the data transfer clock DCLK. , Data transfer clock 1
08 and the display data 107 are output as a differential signal.

FIG. 18 shows the circuit configuration of the differential signal interface of the liquid crystal controller 101 and the data driver 102. The configuration shown in the figure is provided corresponding to each bit of display data to be transmitted and each of the data transfer clocks 108, and one signal is a differential signal in which the signal polarities (+, −) are mutually inverted, It transmits and receives via two transmission lines. This signal interface makes it possible to greatly improve the transmission speed.

In this embodiment, in contrast to the first embodiment,
The display data 107 is transmitted at a quadruple transfer rate. Further, as the display data 107, 6 bits, which is a 1/4 bit number, are simultaneously transferred via the data bus 107 including 12 transmission lines. That is, in this embodiment,
The number of transmission lines of the data bus 107 is half that of the first embodiment.

Next, the data transfer operation in this embodiment will be described.

In the liquid crystal controller 101, the PLL circuit 1704 generates a quadruple speed clock 1706 which is four times as fast as the data transfer clock DCLK. The liquid crystal display data parallel / serial control circuit 1702 controls the 24-bit (parallel) input display data 105 to be output every 6 bits (parallel) in synchronization with the quadruple speed clock 1706. This allows 6 bits (parallel)
Display data 1713 of the data transfer clock DCLK
Is output to the differential buffer circuit 1705 at a speed four times faster than The differential buffer circuit 1705 converts the input data transfer clock CL2 and display data into differential signals, respectively, and uses the two transmission lines to transfer the data transfer clock CL2.
The liquid crystal display data 107 is transmitted through 8 and 12 transmission lines, respectively.

When the input of the display data 107 is started,
In the data driver 102, the PLL circuit 1616 generates a quadruple speed clock 1618 that is four times as fast as the data transfer clock 108. The serial / parallel conversion circuit 1617 takes in the display data 1619 input in 6 bits (parallel) in synchronization with the quadruple speed clock 1618, and displays the display data 1612 in 24 bits (parallel).
Convert to. The display data 1612 is latched by the latch circuit 1605 on a pixel-by-pixel basis. The subsequent operation is similar to that of the first embodiment.

As described above, according to the present embodiment, the display data is transferred by the differential signal, and the parallel / serial conversion and the speed conversion are performed, so that the transmission speed is increased as compared with the first embodiment. Moreover, the number of transmission lines can be reduced.

[0052]

As described above, according to the present invention, it is possible to provide a liquid crystal display device capable of supplying signals to a plurality of data drivers with a smaller number of transmission lines. .

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a liquid crystal display device to which the present invention is applied.

FIG. 2 is a block diagram of a conventional liquid crystal display device.

FIG. 3 is a block diagram of a conventional data driver.

FIG. 4 is a diagram showing a transfer timing of display data in a conventional example.

FIG. 5 is a diagram showing an equivalent circuit of a conventional data bus.

FIG. 6 is a block diagram of a data driver of the first embodiment.

FIG. 7 is a block diagram of the liquid crystal controller according to the first embodiment.

FIG. 8 is a diagram showing a transfer timing of display data according to the first embodiment.

FIG. 9 is a configuration diagram (1) of a signal interface circuit according to the first embodiment.

FIG. 10 is a configuration diagram (2) of a signal interface circuit.

FIG. 11 is a configuration diagram (3) of a signal interface circuit.

FIG. 12 is a diagram showing an equivalent circuit of a data bus in the first embodiment.

FIG. 13 is a block diagram of a data driver according to the second embodiment of the present invention.

FIG. 14 is a diagram showing changes in signal waveforms on a data bus.

FIG. 15 is a diagram showing changes in signal waveforms in the data bus of the second embodiment.

FIG. 16 is a block diagram of a data driver according to a third embodiment of the present invention.

FIG. 17 is a block diagram of a liquid crystal controller according to a third embodiment.

FIG. 18 is a configuration diagram of a signal interface circuit according to a third embodiment.

[Explanation of symbols]

101 ... Liquid crystal controller, 102 ... Data driver,
103 ... Scan driver, 104 ... Liquid crystal panel, 105 ...
Input display data, 106 ... Display synchronization signal group, 107 ... Data bus, 108 ... Data transfer clock, 109 ... Data horizontal synchronization signal, 110 ... Data valid signal, 111 ... Frame synchronization signal, 112 ... Scanning horizontal synchronization signal, 601 ...
Enable control circuit, 602 ... Data input / output buffer circuit, 603 ... Data transfer clock input / output buffer circuit,
Reference numeral 604 ... Latch address generation circuit, 605 ... Latch circuit, 606 ... Latch circuit, 607 ... Liquid crystal drive circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideki Osaka 1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Hitachi, Ltd. System Development Laboratory (72) Inventor Satoru Tsunekawa 5-2-1, Kamimizumoto-cho, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division (72) Inventor Hiroshi Kurihara 3300 Hayano, Mobara-shi, Chiba Hitate Co., Ltd. Electronic Device Division (72) Inventor Atsushi Higa 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi Image Information System (72) Inventor Masashi Nakamura 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (56) References JP-A-8-22268 (JP, A) JP-A-7-212692 (JP , A) JP-A-8-101666 (JP, A) JP-A-9-16128 (JP, A) JP-A-8-101666 (JP, A) 9-90896 (JP, A) JP-A-9-152849 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505-580

Claims (3)

(57) [Claims] 1. A liquid crystal panel and a display data to be input.
A plurality of data which apply the corresponding gradation voltage to the liquid crystal panel.
Driver and scan line of the LCD panel are selected sequentially
Status scan driver, sync signal and display data
For supplying to the data driver and scan driver
Crystal control circuit and the liquid crystal control circuit and
And each data driver in series to display data and
And multiple transmission lines for transmitting the data transfer clock.
The data driver has the transmission line on the input side and the output side.
A buffer circuit inserted between the transmission line and
Captures and retains display data shared by the data driver
And a latch circuit for storing the data, and the buffer circuit outputs data to the transmission line.
Inverts the logic level of the transmission clock and display data
The data driver is used for the display data and data
The logic level of the data transfer clock is set to the liquid crystal controller.
Circuit for returning to the logic level at the output of the circuit
A liquid crystal display device further comprising: 2. The liquid crystal display device according to claim 1, wherein the data driver is connected to a transmission line of the buffer circuit.
Output of the display data shared by the own data driver.
Control circuit that performs control that becomes effective when loading is completed
A liquid crystal display device further comprising: 3. The liquid crystal display device according to claim 1 or 2.
There, the transmission signal in the transmission line, the liquid crystal controller
The width of the change in the signal level inside the
Further has a means for transmitting with a change width smaller than
A liquid crystal display device characterized by the following.