JP2000020035A - Matrix driving type picture display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cope with the transfer of more picture data without need of changing a data transfer format, increasing the power consumption of a display driving controller, and causing problems such as an unnecessary radiation noise. SOLUTION: This picture display device is provided with a frequency divider circuit 17 that halves the frequency of a sampling clock, a first sampling means 21, 18-1, 19-1 to 19-(N/2) that sample picture data at the time of rising of the clock signal the frequency of which is halved by the frequency divider circuit, and a second sampling means 22, 18-2, 19-(N/2+1) to 19-N that sample the picture data at the time of falling of the same clock signal similarly; thus, the device halves the frequency of the sampling clock, and samples at both points of time of the rising and the falling by the first and the second sampling means respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix-driven image display device which samples image data from a signal of the image data based on a sampling clock and displays an image.

[0002]

2. Description of the Related Art Conventionally, as such a matrix drive type image display device, there is known a liquid crystal image display device which transfers image data to a liquid crystal drive controller and further transfers this image data to an information signal line driver to display an image. Have been. FIG. 2 is a system block diagram of the liquid crystal image display device using the conventional data transfer method. In the figure, 1
Is a liquid crystal display panel in which scanning signal electrodes and information signal electrodes are arranged in a matrix, 2 is a segment driver which is an information signal line driver for applying an information signal to each information signal electrode based on image data, 3 is a scanning signal 4-1 is an upper segment bus board, 4-2 is a lower segment bus board, 5 is a common bus board, 6 is a liquid crystal drive controller, 7-1 is an upper segment image data bus, 7-2 Is a lower segment image data bus, 8 is an image data sampling clock signal (S
CLK) line, 9 is a segment control signal line group, 10 is a common control signal line group, 11 is a graphic controller, 1
2 is an image data bus, 13 is an image data sampling clock signal (FCLK) line, 14 is an image data transfer enable signal (ENABLE) line, 15 is a horizontal synchronization signal (Hsync) line, and 16 is a vertical synchronization signal (Vsync).
Line.

As shown in FIG. 2, the arrangement of the segment driver 2 of the liquid crystal panel is such that the information signal lines are arranged above and below the liquid crystal panel 1 in order to restrict the mounting pitch on the liquid crystal panel 1 and to reduce the frequency of the image data sampling clock. "Double-sided arrangement" is performed, which is taken out and mounted on both sides. for that reason,
The transfer of image data from the liquid crystal drive controller 6 to the segment driver 2 is performed using two systems: a transmission line (7-1) for the upper segment driver and a transmission line (7-2) for the lower segment driver. Are done separately.

The graphic controller 11 receives image data and control signals from the host computer, and, based on the image data and control signals, uses a predetermined transfer format as shown in FIGS. The image data of ID 35, the sampling clock FCLK, the horizontal synchronization signal Hsync for setting the horizontal scanning period (1H), and the vertical synchronization signal Vsync for setting one frame period are sent to the liquid crystal drive controller 6.

Here, the bus width of the image data bus 12 is 36 bits. This means that the display performance of the liquid crystal panel 1 is 262, 14
In the case of a four-color display, it is necessary to send the data for the upper segment and the lower segment to the liquid crystal panel 1 in two systems, each of 6 bits for each of the three colors R, G, and B, so that 3 × 6 × This is because a width of 2 = 36 bits is required.
FIG. 5 is a diagram showing an example of the correspondence between the image data buses ID0 to ID35 and the image data.

As shown in FIG. 6, each image data bus ID0
As the image data of ID35 to ID35, valid data (Valid data) is transferred during the High period of the image data transfer enable signal ENABLE, and the rising edge of the image data sampling clock signal FCLK causes
It is sampled by the liquid crystal drive controller 6.

FIG. 8 shows one of ID0 to ID35.
1 shows an example of a circuit configuration for sampling and latching image data in one image data bus (ID *).
In the figure, reference numeral 25 denotes a control circuit which receives the signals ENABLE and FCLK and generates a sampling timing signal for the next-stage flip-flop circuit, and 26 (26-1 to 26-26)
-N) is a flip-flop circuit for sampling image data (N is the number of bits of image data sampled in a period 1H via a certain image data bus (ID *)), and 27 is a signal from each flip-flop circuit 26. N which latches data at the timing of the horizontal synchronization signal Hsync.
It is a bit latch circuit.

The control circuit 25 and the flip-flop circuit 26 control the signal ENABLE to be High.
The image data sampled at the timing of each rising edge of the signal FLCK during the (high) period is, as shown in FIG. 3, image data for one horizontal scanning period 1H at the High timing of the horizontal synchronizing signal Hsync as a latch circuit. 27. Signals Vsync and Hsync
Before and after the High period of c, the signal ENABLE is at L level.
ow (low), and the image data in this period is invalidated (normally, the image data in this period is low).

The transfer of control signals and image data from the liquid crystal drive controller 6 to the liquid crystal display panel 1 is performed as follows. That is, the liquid crystal drive controller 6
Is a signal Vsyn from the graphic controller 11
A segment control signal of the segment driver 2 and a scan timing control signal of the common driver 10 are generated from c and Hsync.
The signal is sent to the segment bus board 4 (4-1, 4-2) and the common bus board 5 via the common control signal line group 10. As described above, the liquid crystal drive controller 6
The image data sampled and latched by
The data is divided into 8-bit data for the upper segment driver and data for the lower segment driver.
The data is transmitted to the upper segment bus board 4-1 and the lower segment bus board 4-2 via the lower segment image data bus 7-2 of the bit width.

As described above, conventionally, in the image data transfer from the graphic controller to the liquid crystal drive controller, the sampling of the image data is always performed only at the rising edge or the falling edge of the signal FCLK (here, the timing of the rising edge). Only the case described above), the sampling clock of the image data requires twice the frequency of the data transfer frequency.

[0011]

By the way, as the number of display colors and the definition of a liquid crystal panel are increased, the transfer amount of image data from a graphic controller to a liquid crystal drive controller is increasing. In order to cope with the transfer of more image data, it is possible to simply increase the data transfer bus width or increase the data transfer frequency. Also, Japanese Patent Application Laid-Open No. 6-95618
As disclosed in Japanese Patent Application Laid-Open Publication No. HEI 10-115, it is conceivable to transmit image data at both rising and falling edge timings.

However, if the bus width is widened, problems such as wiring routing on a printed circuit board, an increase in the number of connection cables, and an increase in connectors will arise. On the other hand, increasing the clock frequency and the data transfer frequency not only increases unnecessary radiation noise and system power consumption, but also increases the transmission line impedance characteristics resulting from the shape of the segment bus board 4 shown in FIG. There is the above problem, and considering the propagation delay of a signal, there is a limit in increasing the frequency. When data is transmitted at the timing of both edges, the conventional data transfer format transmitted at the timing of one edge needs to be changed, which causes a problem that a standard graphic chip cannot be used.

An object of the present invention is to provide a matrix-driven image display device,
An object of the present invention is to make it possible to cope with transfer of more image data without causing the above-described problem.

[0014]

According to the present invention, there is provided a display panel in which a scanning signal electrode and an information signal electrode are arranged in a matrix, and an information signal is applied to each information signal electrode based on image data. An information signal line driver for applying the image data, a display drive controller for transferring the image data to the information signal line driver, and a graphic controller for transferring the image data and its sampling clock to the display drive controller. Is a matrix drive type image display device which comprises sampling means for sampling image data from the graphic controller based on the sampling clock, and transfers the sampled image data to the information signal line driver. A ring circuit for dividing the frequency of the sampling clock by a factor of two, and a first circuit for sampling the image data at the time of the rising edge of the clock signal whose frequency is reduced by a factor of two by the frequency dividing circuit. It is characterized by comprising sampling means and second sampling means for sampling the image data at the time of falling of the clock signal whose frequency has been reduced by half by the frequency dividing circuit. The display panel corresponds to, for example, a ferroelectric liquid crystal panel.

According to this, the frequency of the sampling clock is halved, and sampling is performed at both the rising and falling times by the first and second sampling means. , The operating frequency of the display driving controller becomes の of the conventional one, and the power consumption and unnecessary radiation noise of the display driving controller are reduced. As a data transfer format for transferring data from the graphic controller to the display drive controller, a conventional data transfer format transmitted at one edge timing is used as it is.

[0016]

FIG. 1 shows an example of a circuit configuration for sampling and latching image data on one image data bus (ID *) of a liquid crystal image display device according to an embodiment of the present invention. Note that the system block diagram of the liquid crystal image display device is the same as the conventional one shown in FIG. The format of the data transfer is the same as the conventional one shown in FIGS.

In FIG. 1, reference numeral 17 designates a frequency division of the sampling clock FCLK by a factor of two, and a divided clock FCLK.
A frequency dividing circuit for transmitting CLK2 to a next-stage control circuit; a control circuit for receiving sampling signals ENABLE and FCLK2 to generate a sampling timing signal for a next-stage flip-flop circuit;
Reference numeral 19 (19-1 to 19-N) denotes a flip-flop circuit for sampling image data. N represents the number of bits of image data sampled from the one image data bus in one horizontal scanning period 1H. Reference numeral 20 denotes an N-bit latch circuit that latches data from each flip-flop 19 at the timing of the horizontal synchronization signal Hsync.

Control circuit 18-1 and flip-flop circuits 19-1 to 19- (N / 2) provide signal EN.
During the high period of the ABLE, as shown in FIG. 7, at the timing of the rising edge of the clock signal FCLK2,
Sampling of image data of a total of N / 2 bits is performed.
The control circuit 18-2 and the flip-flop circuits 19- (N / 2 + 1) to 19-N are connected to the signal ENABL.
During the High period of E, as shown in FIG.
At the timing of the falling edge of LK2, sampling of image data of a total of N / 2 bits is performed.

The control circuits 18-1 and 1
Since the buffer 21 and the inverter 22 are respectively inserted before the input of the clock signal FCLK2 to 8-2, the control circuits 18-1 and 18-2 can adopt the same circuit configuration.

The image data sampled as described above corresponds to the horizontal synchronizing signal Hsync as shown in FIG.
At the timing of gh, the image data is latched by the latch circuit 20 as image data for one horizontal scanning period 1H.

Note that before and after the High period of the vertical synchronizing signal Vsync and the horizontal synchronizing signal Hsync, the signal ENABLE is Low, and the image data in this period is invalidated. Usually, the image data in this period is set to Low.

According to the present embodiment, the parts other than the frequency dividing circuit 17 operate with the clock signal FCLK2 having a half frequency of the sampling clock FCLK, so that the power consumption required for the circuit operation is reduced. Unwanted radiation noise can also be reduced.

[0023]

As described above, according to the present invention, the sampling of the image data, which has been conventionally sampled only at the timing of either the rising edge or the falling edge of the data sampling clock, is replaced by the frequency of the sampling clock. , A first sampling means for sampling the image data when the divided sampling clock rises, and sampling the image data when the divided sampling clock falls. Since the second sampling means is provided and the sampling is performed at the timing of both edges, the operating frequency of the circuits other than the frequency dividing circuit is reduced to half that of the conventional circuit, and the power consumption of the display drive controller and unnecessary radiation noise are reduced. Can be. Further, the conventional data transfer format transmitted at one edge timing can be used as it is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a circuit configuration for sampling and latching image data on one image data bus of a liquid crystal image display device according to one embodiment of the present invention.

FIG. 2 is a system block diagram of a liquid crystal image display device to which the circuit configuration of FIG. 1 is applied, which is common to a conventional example.

3 is a signal transfer format diagram from a graphic controller to a liquid crystal drive controller of the liquid crystal image display device of FIG. 2;

FIG. 4 is an enlarged signal transfer format diagram from a graphic controller to a liquid crystal drive controller of the liquid crystal image display device of FIG. 2;

FIG. 5 is a diagram showing an example of correspondence between an image data bus and image data.

FIG. 6 is a further enlarged signal transfer format diagram from the graphic controller to the liquid crystal drive controller of the liquid crystal image display device of FIG. 2;

FIG. 7 is a signal transfer format diagram from a graphic controller to a liquid crystal drive controller in the liquid crystal image display device of FIG. 1;

8 is a block diagram showing a configuration of an image sampling circuit of a liquid crystal drive controller in the liquid crystal image display device of FIG.

[Explanation of symbols]

1: liquid crystal display panel, 2: segment driver, 3: common driver, 4: segment bus board, 5: common bus board, 6: liquid crystal drive controller, 7: image data bus, 8: SCLK line, 9: segment control line, 10: common control signal group, 11: graphic controller, 1
2: image data bus, 13: image data sampling clock (FCLK) line, 14: image data transfer enable signal (ENABLE) line, 15: horizontal synchronization signal (Hs)
sync) line, 16: vertical synchronization signal (Vsync) line, 1
7: frequency dividing circuit, 18: control circuit, 19: flip-flop circuit, 20: latch circuit, 21: buffer,
22: Inverter.

Continued on the front page F term (reference) 2H093 NA11 NA43 NA53 NC16 NC23 NC26 ND39 ND40 NF19 5C006 BA12 BB11 BC16 BF04 BF11 BF23 FA15 FA32 FA37 FA48 5C080 AA10 BB05 DD07 DD12 DD26 JJ02 JJ04

Claims (2)

[Claims] 1. A display panel in which scanning signal electrodes and information signal electrodes are arranged in a matrix, an information signal line driver for applying an information signal to each information signal electrode based on image data, and the information signal line driver. A display drive controller for transferring the image data, and a graphic controller for transferring the image data and its sampling clock to the display drive controller, wherein the display drive controller converts the image data from the graphic controller based on the sampling clock. A matrix drive type image display device, which comprises sampling means for sampling the image data, and transferring the image data sampled by the sampling means to the information signal line driver. A frequency dividing circuit for halving the frequency, first sampling means for sampling the image data at the time of the rising edge of the clock signal whose frequency is halved by the frequency dividing circuit; And a second sampling means for sampling the image data at the time of falling of a clock signal having a frequency of / 2 times. 2. The matrix driven image display device according to claim 1, wherein said display panel is a ferroelectric liquid crystal panel.