ITUD20020238A1 - Metodo per la stesura controllata a getto d'inchiostro di polimeri per isolamento e/o protezione di circuiti stampati - Google Patents

Metodo per la stesura controllata a getto d'inchiostro di polimeri per isolamento e/o protezione di circuiti stampati

Info

Publication number
ITUD20020238A1
ITUD20020238A1 IT000238A ITUD20020238A ITUD20020238A1 IT UD20020238 A1 ITUD20020238 A1 IT UD20020238A1 IT 000238 A IT000238 A IT 000238A IT UD20020238 A ITUD20020238 A IT UD20020238A IT UD20020238 A1 ITUD20020238 A1 IT UD20020238A1
Authority
IT
Italy
Prior art keywords
insulation
protection
jet
printed circuits
laying
Prior art date
Application number
IT000238A
Other languages
English (en)
Inventor
Cesare Fumo
Jozef Vodopivec
Original Assignee
New System Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New System Srl filed Critical New System Srl
Priority to IT000238A priority Critical patent/ITUD20020238A1/it
Priority to EP03775811A priority patent/EP1563720B1/en
Priority to AT03775811T priority patent/ATE322805T1/de
Priority to PCT/IT2003/000709 priority patent/WO2004045261A1/en
Priority to DK03775811T priority patent/DK1563720T3/da
Priority to DE60304491T priority patent/DE60304491T2/de
Priority to ES03775811T priority patent/ES2261987T3/es
Priority to SI200330328T priority patent/SI1563720T1/sl
Priority to CNB200380103049XA priority patent/CN100482040C/zh
Priority to KR1020057007369A priority patent/KR101051854B1/ko
Publication of ITUD20020238A1 publication Critical patent/ITUD20020238A1/it
Priority to US11/125,482 priority patent/US8236373B2/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/013—Inkjet printing, e.g. for printing insulating material or resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0597—Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Treatment Of Fiber Materials (AREA)
  • Ink Jet (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Ink Jet Recording Methods And Recording Media Thereof (AREA)
IT000238A 2002-11-11 2002-11-11 Metodo per la stesura controllata a getto d'inchiostro di polimeri per isolamento e/o protezione di circuiti stampati ITUD20020238A1 (it)

Priority Applications (11)

Application Number Priority Date Filing Date Title
IT000238A ITUD20020238A1 (it) 2002-11-11 2002-11-11 Metodo per la stesura controllata a getto d'inchiostro di polimeri per isolamento e/o protezione di circuiti stampati
DE60304491T DE60304491T2 (de) 2002-11-11 2003-10-31 Verfahren zur kontrollierten tintenstrahlverteilung von polymeren zum isolieren und/oder schützen von gedruckten schaltungen
AT03775811T ATE322805T1 (de) 2002-11-11 2003-10-31 Verfahren zur kontrollierten tintenstrahlverteilung von polymeren zum isolieren und/oder schützen von gedruckten schaltungen
PCT/IT2003/000709 WO2004045261A1 (en) 2002-11-11 2003-10-31 Method for controlled ink-jet spreading of polymers for the insulation and/or protection of printed circuits
DK03775811T DK1563720T3 (da) 2002-11-11 2003-10-31 Fremgangsmåde til styret ink-jet-spredning af polymerer til isolering og/eller beskyttelse af printkredslöb
EP03775811A EP1563720B1 (en) 2002-11-11 2003-10-31 Method for controlled ink-jet spreading of polymers for the insulation and/or protection of printed circuits
ES03775811T ES2261987T3 (es) 2002-11-11 2003-10-31 Metodo para la aplicacion controlada de chorro de tinta de polimeros para el aislamiento y/o proteccion de circuitos impresos.
SI200330328T SI1563720T1 (sl) 2002-11-11 2003-10-31 Postopek za kontrolirano crnilno brizgano razdeljevanje polimerov za izolacijo in/ali zascito tiskanih vezij
CNB200380103049XA CN100482040C (zh) 2002-11-11 2003-10-31 印刷电路绝缘和/或保护聚合物的受控喷墨涂布方法
KR1020057007369A KR101051854B1 (ko) 2002-11-11 2003-10-31 인쇄회로의 절연/보호용 폴리머의 잉크젯 도포 방법
US11/125,482 US8236373B2 (en) 2002-11-11 2005-05-10 Method for controlled ink-jet spreading of polymers for the insulation and/or protection of printed circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000238A ITUD20020238A1 (it) 2002-11-11 2002-11-11 Metodo per la stesura controllata a getto d'inchiostro di polimeri per isolamento e/o protezione di circuiti stampati

Publications (1)

Publication Number Publication Date
ITUD20020238A1 true ITUD20020238A1 (it) 2004-05-12

Family

ID=32310210

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000238A ITUD20020238A1 (it) 2002-11-11 2002-11-11 Metodo per la stesura controllata a getto d'inchiostro di polimeri per isolamento e/o protezione di circuiti stampati

Country Status (10)

Country Link
US (1) US8236373B2 (it)
EP (1) EP1563720B1 (it)
KR (1) KR101051854B1 (it)
CN (1) CN100482040C (it)
AT (1) ATE322805T1 (it)
DE (1) DE60304491T2 (it)
DK (1) DK1563720T3 (it)
ES (1) ES2261987T3 (it)
IT (1) ITUD20020238A1 (it)
WO (1) WO2004045261A1 (it)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006002695A1 (de) * 2006-01-11 2007-08-09 Siemens Ag Piezostack mit neuartiger Passivierung
US9237655B1 (en) * 2013-03-15 2016-01-12 Lockheed Martin Corporation Material deposition on circuit card assemblies
JP2017147388A (ja) * 2016-02-19 2017-08-24 株式会社デンソー 電子装置の製造方法
EP3434081A4 (en) * 2016-03-26 2020-07-01 Nano-Dimension Technologies, Ltd. MANUFACTURE OF PRINTED CIRCUIT BOARD AND FLEXIBLE CIRCUIT BOARD WITH TRACKS AND / OR SHIELDED COMPONENTS BY THREE-DIMENSIONAL INK JET PRINTING
US12046575B2 (en) 2019-05-01 2024-07-23 Io Tech Group Ltd. Method to electrically connect chip with top connectors using 3D printing
US11528802B2 (en) * 2019-12-23 2022-12-13 Tactotek Oy Integrated functional multilayer structure and method of manufacture therefor
US11446750B2 (en) 2020-02-03 2022-09-20 Io Tech Group Ltd. Systems for printing solder paste and other viscous materials at high resolution
US11622451B2 (en) 2020-02-26 2023-04-04 Io Tech Group Ltd. Systems and methods for solder paste printing on components
US11497124B2 (en) * 2020-06-09 2022-11-08 Io Tech Group Ltd. Methods for printing conformal materials on component edges at high resolution
US11691332B2 (en) 2020-08-05 2023-07-04 Io Tech Group Ltd. Systems and methods for 3D printing with vacuum assisted laser printing machine

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508984A (en) * 1967-06-29 1970-04-28 Electro Connective Systems Inc Method of producing printed circuits
US5683924A (en) * 1994-10-31 1997-11-04 Sgs-Thomson Microelectronics, Inc. Method of forming raised source/drain regions in a integrated circuit
GB2369087B (en) * 1997-10-14 2002-10-02 Patterning Technologies Ltd Method of forming a circuit element on a surface
JP4003273B2 (ja) * 1998-01-19 2007-11-07 セイコーエプソン株式会社 パターン形成方法および基板製造装置
CN100530759C (zh) * 1998-03-17 2009-08-19 精工爱普生株式会社 薄膜构图的衬底及其表面处理
JP5016767B2 (ja) * 2000-03-07 2012-09-05 エーエスエム インターナショナル エヌ．ヴェー． 傾斜薄膜の形成方法
US6320137B1 (en) * 2000-04-11 2001-11-20 3M Innovative Properties Company Flexible circuit with coverplate layer and overlapping protective layer
US6710381B1 (en) * 2002-10-08 2004-03-23 Macronix International Co., Ltd. Memory device structure with composite buried and raised bit line

Also Published As

Publication number Publication date
DE60304491D1 (de) 2006-05-18
DE60304491T2 (de) 2006-12-07
CN100482040C (zh) 2009-04-22
CN1711810A (zh) 2005-12-21
KR101051854B1 (ko) 2011-07-25
ATE322805T1 (de) 2006-04-15
DK1563720T3 (da) 2006-08-07
WO2004045261A1 (en) 2004-05-27
US8236373B2 (en) 2012-08-07
KR20050053792A (ko) 2005-06-08
EP1563720A1 (en) 2005-08-17
US20050263875A1 (en) 2005-12-01
ES2261987T3 (es) 2006-11-16
EP1563720B1 (en) 2006-04-05

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