ITRM980544A0 - Circuito di lettura per dispositivi di memoria flash con perfezionati margini di programmazione e procedimento di funzionamento - Google Patents

Circuito di lettura per dispositivi di memoria flash con perfezionati margini di programmazione e procedimento di funzionamento

Info

Publication number
ITRM980544A0
ITRM980544A0 IT98RM000544A ITRM980544A ITRM980544A0 IT RM980544 A0 ITRM980544 A0 IT RM980544A0 IT 98RM000544 A IT98RM000544 A IT 98RM000544A IT RM980544 A ITRM980544 A IT RM980544A IT RM980544 A0 ITRM980544 A0 IT RM980544A0
Authority
IT
Italy
Prior art keywords
flash memory
memory devices
operation procedure
reading circuit
improved programming
Prior art date
Application number
IT98RM000544A
Other languages
English (en)
Inventor
Giulio Marotta
Giovanni Santin
Michael C Smayling
Original Assignee
Texas Instruments Italia Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Italia Spa filed Critical Texas Instruments Italia Spa
Priority to IT1998RM000544A priority Critical patent/IT1302433B1/it
Publication of ITRM980544A0 publication Critical patent/ITRM980544A0/it
Priority to US09/372,730 priority patent/US6191976B1/en
Publication of ITRM980544A1 publication Critical patent/ITRM980544A1/it
Application granted granted Critical
Publication of IT1302433B1 publication Critical patent/IT1302433B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
IT1998RM000544A 1998-08-13 1998-08-13 Circuito di lettura per dispositivi di memoria flash con perfezionatimargini di programmazione e procedimento di funzionamento IT1302433B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT1998RM000544A IT1302433B1 (it) 1998-08-13 1998-08-13 Circuito di lettura per dispositivi di memoria flash con perfezionatimargini di programmazione e procedimento di funzionamento
US09/372,730 US6191976B1 (en) 1998-08-13 1999-08-11 Flash memory margin mode enhancements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT1998RM000544A IT1302433B1 (it) 1998-08-13 1998-08-13 Circuito di lettura per dispositivi di memoria flash con perfezionatimargini di programmazione e procedimento di funzionamento

Publications (3)

Publication Number Publication Date
ITRM980544A0 true ITRM980544A0 (it) 1998-08-13
ITRM980544A1 ITRM980544A1 (it) 2000-02-13
IT1302433B1 IT1302433B1 (it) 2000-09-05

Family

ID=11406103

Family Applications (1)

Application Number Title Priority Date Filing Date
IT1998RM000544A IT1302433B1 (it) 1998-08-13 1998-08-13 Circuito di lettura per dispositivi di memoria flash con perfezionatimargini di programmazione e procedimento di funzionamento

Country Status (2)

Country Link
US (1) US6191976B1 (it)
IT (1) IT1302433B1 (it)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6510082B1 (en) 2001-10-23 2003-01-21 Advanced Micro Devices, Inc. Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold
US6529412B1 (en) 2002-01-16 2003-03-04 Advanced Micro Devices, Inc. Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge
US6819620B2 (en) * 2003-01-23 2004-11-16 Ememory Technology Inc. Power supply device with reduced power consumption
US6819591B1 (en) * 2004-01-20 2004-11-16 Spansion Llc Method for erasing a memory sector in virtual ground architecture with reduced leakage current
GB2412468A (en) * 2004-03-26 2005-09-28 Zarlink Semiconductor Ab Testing an EEPROM utilising an additional select transistor and test line
FR2874449B1 (fr) * 2004-08-17 2008-04-04 Atmel Corp Circuit de retard de programme auto-adaptatif pour memoires programmables
EP1782426B1 (en) * 2004-08-17 2015-10-28 Atmel Corporation Self-adaptive program delay circuitry for programmable memories
US7333379B2 (en) * 2006-01-12 2008-02-19 International Business Machines Corporation Balanced sense amplifier circuits with adjustable transistor body bias
FR2977047B1 (fr) * 2011-06-22 2013-08-16 Starchip Procede de gestion de l'endurance de memoires non volatiles.
US9384787B2 (en) 2014-09-03 2016-07-05 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Selecting a voltage sense line that maximizes memory margin
WO2017023245A1 (en) 2015-07-31 2017-02-09 Hewlett Packard Enterprise Development Lp Data sensing in crosspoint memory structures

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0154193B1 (ko) * 1994-12-30 1998-12-01 김주용 센스 앰프회로
EP0805454A1 (en) * 1996-04-30 1997-11-05 STMicroelectronics S.r.l. Sensing circuit for reading and verifying the content of a memory cell
US5973957A (en) * 1997-09-16 1999-10-26 Intel Corporation Sense amplifier comprising a preamplifier and a differential input latch for flash memories

Also Published As

Publication number Publication date
IT1302433B1 (it) 2000-09-05
ITRM980544A1 (it) 2000-02-13
US6191976B1 (en) 2001-02-20

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