IT987425B - Memoria monolitica perfezionata dotata di circuiti atti ad atti vare repentinamente i circuiti di lettura dopo un operazione di lettura - Google Patents
Memoria monolitica perfezionata dotata di circuiti atti ad atti vare repentinamente i circuiti di lettura dopo un operazione di letturaInfo
- Publication number
- IT987425B IT987425B IT7324073A IT2407373A IT987425B IT 987425 B IT987425 B IT 987425B IT 7324073 A IT7324073 A IT 7324073A IT 2407373 A IT2407373 A IT 2407373A IT 987425 B IT987425 B IT 987425B
- Authority
- IT
- Italy
- Prior art keywords
- circuits
- reading
- repentinally
- perfected
- varying
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/416—Read-write [R-W] circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US26898872A | 1972-07-05 | 1972-07-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IT987425B true IT987425B (it) | 1975-02-20 |
Family
ID=23025373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT7324073A IT987425B (it) | 1972-07-05 | 1973-05-15 | Memoria monolitica perfezionata dotata di circuiti atti ad atti vare repentinamente i circuiti di lettura dopo un operazione di lettura |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US3789243A (it) |
| JP (1) | JPS5524197B2 (it) |
| CA (1) | CA1012654A (it) |
| DE (1) | DE2333381C3 (it) |
| FR (1) | FR2191196B1 (it) |
| GB (1) | GB1369767A (it) |
| IT (1) | IT987425B (it) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5616718Y2 (it) * | 1974-12-30 | 1981-04-17 | ||
| US4272834A (en) * | 1978-10-06 | 1981-06-09 | Hitachi, Ltd. | Data line potential setting circuit and MIS memory circuit using the same |
| DE2855866C3 (de) * | 1978-12-22 | 1981-10-29 | Ibm Deutschland Gmbh, 7000 Stuttgart | Verfahren und Schaltungsanordnung zum Betreiben eines integrierten Halbleiterspeichers |
| DE2929384C2 (de) * | 1979-07-20 | 1981-07-30 | Ibm Deutschland Gmbh, 7000 Stuttgart | Nachladeschaltung für einen Halbleiterspeicher |
| JPH0648595B2 (ja) * | 1982-08-20 | 1994-06-22 | 株式会社東芝 | 半導体記憶装置のセンスアンプ |
| US4570090A (en) * | 1983-06-30 | 1986-02-11 | International Business Machines Corporation | High-speed sense amplifier circuit with inhibit capability |
| US4608667A (en) * | 1984-05-18 | 1986-08-26 | International Business Machines Corporation | Dual mode logic circuit for a memory array |
| US4598390A (en) * | 1984-06-25 | 1986-07-01 | International Business Machines Corporation | Random access memory RAM employing complementary transistor switch (CTS) memory cells |
| US4578779A (en) * | 1984-06-25 | 1986-03-25 | International Business Machines Corporation | Voltage mode operation scheme for bipolar arrays |
| US4596002A (en) * | 1984-06-25 | 1986-06-17 | International Business Machines Corporation | Random access memory RAM employing complementary transistor switch (CTS) memory cells |
| US5297089A (en) * | 1992-02-27 | 1994-03-22 | International Business Machines Corporation | Balanced bit line pull up circuitry for random access memories |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3609712A (en) * | 1969-01-15 | 1971-09-28 | Ibm | Insulated gate field effect transistor memory array |
| US3638039A (en) * | 1970-09-18 | 1972-01-25 | Rca Corp | Operation of field-effect transistor circuits having substantial distributed capacitance |
-
1972
- 1972-07-05 US US00268988A patent/US3789243A/en not_active Expired - Lifetime
-
1973
- 1973-05-15 IT IT7324073A patent/IT987425B/it active
- 1973-06-13 FR FR7322361A patent/FR2191196B1/fr not_active Expired
- 1973-06-15 GB GB2862973A patent/GB1369767A/en not_active Expired
- 1973-06-19 CA CA174,371A patent/CA1012654A/en not_active Expired
- 1973-06-22 JP JP6997573A patent/JPS5524197B2/ja not_active Expired
- 1973-06-30 DE DE2333381A patent/DE2333381C3/de not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| CA1012654A (en) | 1977-06-21 |
| FR2191196A1 (it) | 1974-02-01 |
| US3789243A (en) | 1974-01-29 |
| JPS4952936A (it) | 1974-05-23 |
| DE2333381A1 (de) | 1974-01-24 |
| DE2333381C3 (de) | 1981-03-12 |
| FR2191196B1 (it) | 1976-05-07 |
| JPS5524197B2 (it) | 1980-06-27 |
| GB1369767A (en) | 1974-10-09 |
| DE2333381B2 (de) | 1980-06-26 |
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