IT982699B - Memoria a semiconduttori perfezionata - Google Patents

Memoria a semiconduttori perfezionata

Info

Publication number
IT982699B
IT982699B IT22598/73A IT2259873A IT982699B IT 982699 B IT982699 B IT 982699B IT 22598/73 A IT22598/73 A IT 22598/73A IT 2259873 A IT2259873 A IT 2259873A IT 982699 B IT982699 B IT 982699B
Authority
IT
Italy
Prior art keywords
perfected
semiconductor memory
semiconductor
memory
perfected semiconductor
Prior art date
Application number
IT22598/73A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT982699B publication Critical patent/IT982699B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
    • G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Static Random-Access Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
IT22598/73A 1972-06-30 1973-04-05 Memoria a semiconduttori perfezionata IT982699B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26782772A 1972-06-30 1972-06-30

Publications (1)

Publication Number Publication Date
IT982699B true IT982699B (it) 1974-10-21

Family

ID=23020290

Family Applications (1)

Application Number Title Priority Date Filing Date
IT22598/73A IT982699B (it) 1972-06-30 1973-04-05 Memoria a semiconduttori perfezionata

Country Status (7)

Country Link
US (1) US3750116A (it)
JP (1) JPS5440183B2 (it)
CA (1) CA1019835A (it)
DE (1) DE2332555A1 (it)
FR (1) FR2191203B1 (it)
GB (1) GB1418552A (it)
IT (1) IT982699B (it)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4024509A (en) * 1975-06-30 1977-05-17 Honeywell Information Systems, Inc. CCD register array addressing system including apparatus for by-passing selected arrays
JPS5857838B2 (ja) * 1980-12-29 1983-12-22 富士通株式会社 デコ−ド回路
US4963769A (en) * 1989-05-08 1990-10-16 Cypress Semiconductor Circuit for selective power-down of unused circuitry
US5946257A (en) 1996-07-24 1999-08-31 Micron Technology, Inc. Selective power distribution circuit for an integrated circuit
US20030074610A1 (en) * 2001-10-16 2003-04-17 Umax Data Systems Inc. Method for improving utilization of a defective memory device in an image processing system
KR100481849B1 (ko) * 2001-12-04 2005-04-11 삼성전자주식회사 용량 변경이 가능한 캐쉬 메모리 및 이를 구비한 프로세서칩
JP2009093205A (ja) * 2009-02-02 2009-04-30 Hinomoto Gosei Jushi Seisakusho:Kk 分子模型

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3402398A (en) * 1964-08-31 1968-09-17 Bunker Ramo Plural content addressed memories with a common sensing circuit
US3422402A (en) * 1965-12-29 1969-01-14 Ibm Memory systems for using storage devices containing defective bits
US3588830A (en) * 1968-01-17 1971-06-28 Ibm System for using a memory having irremediable bad bits
US3659275A (en) * 1970-06-08 1972-04-25 Cogar Corp Memory correction redundancy system
US3688280A (en) * 1970-09-22 1972-08-29 Ibm Monolithic memory system with bi-level powering for reduced power consumption

Also Published As

Publication number Publication date
DE2332555A1 (de) 1974-01-17
FR2191203A1 (it) 1974-02-01
JPS4945650A (it) 1974-05-01
JPS5440183B2 (it) 1979-12-01
US3750116A (en) 1973-07-31
CA1019835A (en) 1977-10-25
GB1418552A (en) 1975-12-24
FR2191203B1 (it) 1976-04-30

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