IT950858B - Struttura circuitale per rilevare la presenza di errori in sistemi di elaborazione dei dati - Google Patents

Struttura circuitale per rilevare la presenza di errori in sistemi di elaborazione dei dati

Info

Publication number
IT950858B
IT950858B IT22530/72A IT2253072A IT950858B IT 950858 B IT950858 B IT 950858B IT 22530/72 A IT22530/72 A IT 22530/72A IT 2253072 A IT2253072 A IT 2253072A IT 950858 B IT950858 B IT 950858B
Authority
IT
Italy
Prior art keywords
errors
detect
data processing
circuit structure
processing systems
Prior art date
Application number
IT22530/72A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT950858B publication Critical patent/IT950858B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H04L1/0063—Single parity check
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L2001/0092—Error control systems characterised by the topology of the transmission link
    • H04L2001/0094—Bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
IT22530/72A 1971-06-26 1972-03-29 Struttura circuitale per rilevare la presenza di errori in sistemi di elaborazione dei dati IT950858B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2131787A DE2131787C3 (de) 1971-06-26 1971-06-26 Schaltungsanordnung zur Fehlerfeststellung bei Datenverarbeitungssystemen

Publications (1)

Publication Number Publication Date
IT950858B true IT950858B (it) 1973-06-20

Family

ID=5811858

Family Applications (1)

Application Number Title Priority Date Filing Date
IT22530/72A IT950858B (it) 1971-06-26 1972-03-29 Struttura circuitale per rilevare la presenza di errori in sistemi di elaborazione dei dati

Country Status (7)

Country Link
US (1) US3763470A (it)
JP (1) JPS5135334B1 (it)
CA (1) CA955686A (it)
DE (1) DE2131787C3 (it)
FR (1) FR2144292A5 (it)
GB (1) GB1372133A (it)
IT (1) IT950858B (it)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2242910A5 (it) * 1973-09-03 1975-03-28 Honeywell Bull Soc Ind
US3882460A (en) * 1973-11-02 1975-05-06 Burroughs Corp Serial transfer error detection logic
JPS5438844B2 (it) * 1974-07-19 1979-11-24
US3938083A (en) * 1974-11-27 1976-02-10 Burroughs Corporation Parity checking a double-frequency coherent-phase data signal
US4020459A (en) * 1975-10-28 1977-04-26 Bell Telephone Laboratories, Incorporated Parity generation and bus matching arrangement for synchronized duplicated data processing units
IT1149252B (it) * 1980-09-09 1986-12-03 Sits Soc It Telecom Siemens Modulo di ingresso-uscita per un elaboratore elettronico
US4414669A (en) * 1981-07-23 1983-11-08 General Electric Company Self-testing pipeline processors
US4420842A (en) * 1981-07-29 1983-12-13 Kuhn Loughrey R Fiber optic digital data transmitting system
NL8301098A (nl) * 1983-03-29 1984-10-16 Philips Nv Digitaal transmissiesysteem.
JPS6083475U (ja) * 1983-11-15 1985-06-08 滝崎　浩一 連続懸吊用ハンガ−
US4823347A (en) * 1987-05-18 1989-04-18 International Business Machines Corporation Deferred parity checking of control signals across a bidirectional data transmission interface
JPS6419380U (it) * 1987-07-28 1989-01-31
JP2863392B2 (ja) * 1992-12-09 1999-03-03 富士通株式会社 ネットワーク装置を試験するための装置
JP3217993B2 (ja) * 1997-07-09 2001-10-15 沖電気工業株式会社 パリティチェック回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3473150A (en) * 1966-08-10 1969-10-14 Teletype Corp Block synchronization circuit for a data communications system
US3525077A (en) * 1968-05-31 1970-08-18 Sperry Rand Corp Block parity generating and checking scheme for multi-computer system

Also Published As

Publication number Publication date
DE2131787A1 (de) 1973-01-11
JPS5135334B1 (it) 1976-10-01
DE2131787B2 (de) 1973-05-03
CA955686A (en) 1974-10-01
DE2131787C3 (de) 1973-12-20
GB1372133A (en) 1974-10-30
US3763470A (en) 1973-10-02
FR2144292A5 (it) 1973-02-09

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