IT945066B - Metodo per collegare un semicondut tore con un sostrato e circuito risultante - Google Patents

Metodo per collegare un semicondut tore con un sostrato e circuito risultante

Info

Publication number
IT945066B
IT945066B IT54241/71A IT5424171A IT945066B IT 945066 B IT945066 B IT 945066B IT 54241/71 A IT54241/71 A IT 54241/71A IT 5424171 A IT5424171 A IT 5424171A IT 945066 B IT945066 B IT 945066B
Authority
IT
Italy
Prior art keywords
semiconductor
substrate
resulting circuit
resulting
circuit
Prior art date
Application number
IT54241/71A
Other languages
English (en)
Original Assignee
Lucas Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB5572170A external-priority patent/GB1363431A/en
Application filed by Lucas Industries Ltd filed Critical Lucas Industries Ltd
Application granted granted Critical
Publication of IT945066B publication Critical patent/IT945066B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
IT54241/71A 1970-11-24 1971-11-22 Metodo per collegare un semicondut tore con un sostrato e circuito risultante IT945066B (it)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB5572170A GB1363431A (en) 1970-11-24 1970-11-24 Method of electrically connecting a semiconductor chip to a sub strate
GB548471 1971-02-25

Publications (1)

Publication Number Publication Date
IT945066B true IT945066B (it) 1973-05-10

Family

ID=26239922

Family Applications (1)

Application Number Title Priority Date Filing Date
IT54241/71A IT945066B (it) 1970-11-24 1971-11-22 Metodo per collegare un semicondut tore con un sostrato e circuito risultante

Country Status (4)

Country Link
AU (1) AU3588571A (it)
DE (1) DE2157956A1 (it)
FR (1) FR2115393A1 (it)
IT (1) IT945066B (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3997910A (en) * 1975-02-26 1976-12-14 Rca Corporation Semiconductor device with solder conductive paths
DE2704833C2 (de) * 1977-02-05 1982-05-27 Robert Bosch Gmbh, 7000 Stuttgart Leiterbahn-Endbereich zum Anlöten eines Halbleiterelementes in Flip-Chip- Technik

Also Published As

Publication number Publication date
FR2115393A1 (it) 1972-07-07
DE2157956A1 (de) 1972-05-31
AU3588571A (en) 1973-05-24

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