IT945066B - Metodo per collegare un semicondut tore con un sostrato e circuito risultante - Google Patents
Metodo per collegare un semicondut tore con un sostrato e circuito risultanteInfo
- Publication number
- IT945066B IT945066B IT5424171A IT5424171A IT945066B IT 945066 B IT945066 B IT 945066B IT 5424171 A IT5424171 A IT 5424171A IT 5424171 A IT5424171 A IT 5424171A IT 945066 B IT945066 B IT 945066B
- Authority
- IT
- Italy
- Prior art keywords
- semiconductor
- substrate
- resulting circuit
- resulting
- circuit
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB5572170A GB1363431A (en) | 1970-11-24 | 1970-11-24 | Method of electrically connecting a semiconductor chip to a sub strate |
| GB548471 | 1971-02-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IT945066B true IT945066B (it) | 1973-05-10 |
Family
ID=26239922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT5424171A IT945066B (it) | 1970-11-24 | 1971-11-22 | Metodo per collegare un semicondut tore con un sostrato e circuito risultante |
Country Status (4)
| Country | Link |
|---|---|
| AU (1) | AU3588571A (it) |
| DE (1) | DE2157956A1 (it) |
| FR (1) | FR2115393A1 (it) |
| IT (1) | IT945066B (it) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3997910A (en) * | 1975-02-26 | 1976-12-14 | Rca Corporation | Semiconductor device with solder conductive paths |
| DE2704833C2 (de) * | 1977-02-05 | 1982-05-27 | Robert Bosch Gmbh, 7000 Stuttgart | Leiterbahn-Endbereich zum Anlöten eines Halbleiterelementes in Flip-Chip- Technik |
-
1971
- 1971-11-18 AU AU35885/71A patent/AU3588571A/en not_active Expired
- 1971-11-22 IT IT5424171A patent/IT945066B/it active
- 1971-11-23 DE DE19712157956 patent/DE2157956A1/de active Pending
- 1971-11-24 FR FR7142146A patent/FR2115393A1/fr not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| FR2115393A1 (it) | 1972-07-07 |
| DE2157956A1 (de) | 1972-05-31 |
| AU3588571A (en) | 1973-05-24 |
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