IT1258990B - Dispositivo di memoria a semiconduttore con linee di alimentazione e di massa del terminale di ingresso isolate da quelle del terminale di uscita - Google Patents

Dispositivo di memoria a semiconduttore con linee di alimentazione e di massa del terminale di ingresso isolate da quelle del terminale di uscita

Info

Publication number
IT1258990B
IT1258990B ITMI921460A ITMI921460A IT1258990B IT 1258990 B IT1258990 B IT 1258990B IT MI921460 A ITMI921460 A IT MI921460A IT MI921460 A ITMI921460 A IT MI921460A IT 1258990 B IT1258990 B IT 1258990B
Authority
IT
Italy
Prior art keywords
power
memory device
semiconductor memory
output terminal
input terminal
Prior art date
Application number
ITMI921460A
Other languages
English (en)
Italian (it)
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI921460A0 publication Critical patent/ITMI921460A0/it
Publication of ITMI921460A1 publication Critical patent/ITMI921460A1/it
Application granted granted Critical
Publication of IT1258990B publication Critical patent/IT1258990B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211—Design considerations for internal polarisation
    • H10D89/213—Design considerations for internal polarisation in field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
ITMI921460A 1991-06-19 1992-06-12 Dispositivo di memoria a semiconduttore con linee di alimentazione e di massa del terminale di ingresso isolate da quelle del terminale di uscita IT1258990B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910010194A KR930001392A (ko) 1991-06-19 1991-06-19 반도체 메모리 장치의 전원 접지선 배선방법

Publications (3)

Publication Number Publication Date
ITMI921460A0 ITMI921460A0 (it) 1992-06-12
ITMI921460A1 ITMI921460A1 (it) 1993-12-12
IT1258990B true IT1258990B (it) 1996-03-11

Family

ID=19316015

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI921460A IT1258990B (it) 1991-06-19 1992-06-12 Dispositivo di memoria a semiconduttore con linee di alimentazione e di massa del terminale di ingresso isolate da quelle del terminale di uscita

Country Status (7)

Country Link
JP (1) JPH0719851B2 (en:Method)
KR (1) KR930001392A (en:Method)
DE (1) DE4219927A1 (en:Method)
FR (1) FR2678109B1 (en:Method)
GB (1) GB2256968A (en:Method)
IT (1) IT1258990B (en:Method)
TW (1) TW245835B (en:Method)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100249166B1 (ko) * 1997-03-07 2000-03-15 김영환 이에스디(esd) 보호회로 및 그 제조방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780828A (en) * 1980-11-07 1982-05-20 Hitachi Ltd Semiconductor integrated circuit device
JPS5922357A (ja) * 1982-07-28 1984-02-04 Toshiba Corp Ｃｍｏｓ形半導体集積回路
JPH0693497B2 (ja) * 1986-07-30 1994-11-16 日本電気株式会社 相補型ｍｉｓ集積回路
GB2199695B (en) * 1987-01-06 1990-07-25 Samsung Semiconductor Inc Dynamic random access memory with selective well biasing
US5023689A (en) * 1987-03-18 1991-06-11 Nec Corporation Complementary integrated circuit device equipped with latch-up preventing means

Also Published As

Publication number Publication date
KR930001392A (ko) 1993-01-16
JPH0719851B2 (ja) 1995-03-06
GB2256968A (en) 1992-12-23
ITMI921460A1 (it) 1993-12-12
DE4219927A1 (de) 1992-12-24
TW245835B (en:Method) 1995-04-21
FR2678109A1 (fr) 1992-12-24
FR2678109B1 (fr) 1994-01-21
JPH06112435A (ja) 1994-04-22
ITMI921460A0 (it) 1992-06-12
GB9212830D0 (en) 1992-07-29

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Legal Events

Date Code Title Description
0001 Granted