IT1245495B - DYNAMIC RANDOM ACCESS MEMORY HAVING A STACKED TYPE CAPACITOR AND ITS MANUFACTURING PROCEDURE - Google Patents

DYNAMIC RANDOM ACCESS MEMORY HAVING A STACKED TYPE CAPACITOR AND ITS MANUFACTURING PROCEDURE

Info

Publication number
IT1245495B
IT1245495B ITMI910177A ITMI910177A IT1245495B IT 1245495 B IT1245495 B IT 1245495B IT MI910177 A ITMI910177 A IT MI910177A IT MI910177 A ITMI910177 A IT MI910177A IT 1245495 B IT1245495 B IT 1245495B
Authority
IT
Italy
Prior art keywords
capacitors
capacitor
insulating layer
cylindrical
bit line
Prior art date
Application number
ITMI910177A
Other languages
Italian (it)
Inventor
Natsuo Ajika
Hideaki Arima
Atsushi Hachisuka
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2251306A external-priority patent/JP2528731B2/en
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI910177A0 publication Critical patent/ITMI910177A0/en
Publication of ITMI910177A1 publication Critical patent/ITMI910177A1/en
Application granted granted Critical
Publication of IT1245495B publication Critical patent/IT1245495B/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments

Landscapes

  • Semiconductor Memories (AREA)

Abstract

La DRAM secondo la presente invenzione comprende condensatori del tipo cosiddetto impilato cilindrici. Ciascuno dei condensatori di tipo impilato cilindrici comprende una porzione di base estendentesi di piatto su uno strato isolante ed una superficie di un substrato, ed una porzione cilindrica estendentesi verticalmente verso l'alto dalla porzione di base. Quindi, la porzione cilindrica sporge verticalmente verso l'alto da una posizione periferica più esterna della porzione di base. Di conseguenza, l'area ove vi sono gli elettrodi del condensatore e la capacità del condensatore possono essere aumentate. Inoltre, con una linea di bit disposta al di sotto di uno strato elettrodico del condensatore, condensatori adiacenti al di sopra della linea di bit possono essere isolati. Perciò, è possibile impedire, al contatto della linea di bit; di definire una distanza di isolamento tra i condensatori. Inoltre, uno strato isolante modellato mediante incisione, viene impiegato come una regione isolante tra i condensatori ed un elettrodo inferiore del condensatore è formato lungo una superficie dello strato isolante per formare una regione isolante tra i condensatori adiacenti. In aggiunta, l'elettrodo inferiore del condensatore di tipo impilato cilindrico è formato integralmente impiegando un gradino formato nello strato isolante. Di conseguenza la fase di fabbricazione viene semplificata.The DRAM according to the present invention comprises capacitors of the so-called stacked cylindrical type. Each of the cylindrical stacked type capacitors comprises a plate extending base portion on an insulating layer and a surface of a substrate, and a cylindrical portion extending vertically upwards from the base portion. Hence, the cylindrical portion protrudes vertically upward from a peripheral position more external than the base portion. As a result, the area where the capacitor electrodes are located and the capacitor capacity can be increased. Furthermore, with a bit line disposed below an electrode layer of the capacitor, adjacent capacitors above the bit line can be isolated. Therefore, it is possible to prevent contact of the bit line; to define an isolation distance between the capacitors. Furthermore, an insulating layer molded by etching is used as an insulating region between the capacitors and a lower electrode of the capacitor is formed along a surface of the insulating layer to form an insulating region between the adjacent capacitors. In addition, the bottom electrode of the cylindrical stacked type capacitor is integrally formed using a step formed in the insulating layer. Consequently, the manufacturing phase is simplified.

ITMI910177A 1990-01-26 1991-01-24 DYNAMIC RANDOM ACCESS MEMORY HAVING A STACKED TYPE CAPACITOR AND ITS MANUFACTURING PROCEDURE IT1245495B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1696090 1990-01-26
JP8986990 1990-04-03
JP2251306A JP2528731B2 (en) 1990-01-26 1990-09-19 Semiconductor memory device and manufacturing method thereof

Publications (3)

Publication Number Publication Date
ITMI910177A0 ITMI910177A0 (en) 1991-01-24
ITMI910177A1 ITMI910177A1 (en) 1992-07-24
IT1245495B true IT1245495B (en) 1994-09-27

Family

ID=27281633

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI910177A IT1245495B (en) 1990-01-26 1991-01-24 DYNAMIC RANDOM ACCESS MEMORY HAVING A STACKED TYPE CAPACITOR AND ITS MANUFACTURING PROCEDURE

Country Status (2)

Country Link
DE (1) DE4102184C2 (en)
IT (1) IT1245495B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2689031B2 (en) * 1991-04-01 1997-12-10 三菱電機株式会社 Semiconductor memory device and method of manufacturing the same
KR940004606B1 (en) * 1991-09-13 1994-05-25 금성일렉트론 주식회사 Method of fabricating a semiconductor memory capacitor
TW221720B (en) * 1991-11-15 1994-03-11 Gold Star Co
DE4222467C1 (en) * 1992-07-08 1993-06-24 Siemens Ag, 8000 Muenchen, De
JPH06151749A (en) * 1992-11-04 1994-05-31 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JP3272517B2 (en) * 1993-12-01 2002-04-08 三菱電機株式会社 Method for manufacturing semiconductor device
GB2336714B (en) * 1997-12-24 2000-03-08 United Semiconductor Corp Method of fabricating capacitor
TW427014B (en) * 1997-12-24 2001-03-21 United Microelectronics Corp The manufacturing method of the capacitors of DRAM

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3918924C2 (en) * 1988-06-10 1996-03-21 Mitsubishi Electric Corp Manufacturing method for a semiconductor memory device
JPH0221652A (en) * 1988-07-08 1990-01-24 Mitsubishi Electric Corp Semiconductor storage device
JP2519569B2 (en) * 1990-04-27 1996-07-31 三菱電機株式会社 Semiconductor memory device and manufacturing method thereof

Also Published As

Publication number Publication date
DE4102184C2 (en) 1995-03-16
ITMI910177A0 (en) 1991-01-24
DE4102184A1 (en) 1991-08-08
ITMI910177A1 (en) 1992-07-24

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960423