KR970005726B1 - Semiconductor memory device and manufacturing method thereof - Google Patents

Semiconductor memory device and manufacturing method thereof Download PDF

Info

Publication number
KR970005726B1
KR970005726B1 KR91017322A KR910017322A KR970005726B1 KR 970005726 B1 KR970005726 B1 KR 970005726B1 KR 91017322 A KR91017322 A KR 91017322A KR 910017322 A KR910017322 A KR 910017322A KR 970005726 B1 KR970005726 B1 KR 970005726B1
Authority
KR
South Korea
Prior art keywords
memory device
electrode
semiconductor memory
electrode layer
fabricating
Prior art date
Application number
KR91017322A
Other languages
Korean (ko)
Other versions
KR930009081A (en
Inventor
Jae-Ahn Yu
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to KR91017322A priority Critical patent/KR970005726B1/en
Publication of KR930009081A publication Critical patent/KR930009081A/en
Application granted granted Critical
Publication of KR970005726B1 publication Critical patent/KR970005726B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A method for fabricating a semiconductor memory device is disclosed. According to the method for fabricating the semiconductor memory device, first, second and third gate electrodes(50,52,90) as a first electrode are electrically connected each other. A first storage electrode layer(50) is formed, with occupying a predetermined region of a gate electrode(30) and a wordline(34). An interconnection part(12) is connected to a source/drain region(not shown in a drawing) of the semiconductor substrate(10). A plate electrode layer(70) as a second electrode is formed and a dielectric layer electrically separates the first storage electrode layer(50) from the plate electrode layer(70). Thereby, a storage capacity is increased due to an increase of the surface area of the capacitor electrode, improving a characteristic of DRAM which needs a periodic refresh.
KR91017322A 1991-10-02 1991-10-02 Semiconductor memory device and manufacturing method thereof KR970005726B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR91017322A KR970005726B1 (en) 1991-10-02 1991-10-02 Semiconductor memory device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR91017322A KR970005726B1 (en) 1991-10-02 1991-10-02 Semiconductor memory device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
KR930009081A KR930009081A (en) 1993-05-22
KR970005726B1 true KR970005726B1 (en) 1997-04-19

Family

ID=19320718

Family Applications (1)

Application Number Title Priority Date Filing Date
KR91017322A KR970005726B1 (en) 1991-10-02 1991-10-02 Semiconductor memory device and manufacturing method thereof

Country Status (1)

Country Link
KR (1) KR970005726B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6131819A (en) * 1998-10-15 2000-10-17 Wet Enterprises, Inc. Decorative illuminated water display

Also Published As

Publication number Publication date
KR930009081A (en) 1993-05-22

Similar Documents

Publication Publication Date Title
US5504028A (en) Method of forming a dynamic random memory device
US5043780A (en) DRAM cell having a texturized polysilicon lower capacitor plate for increased capacitance
US5930106A (en) DRAM capacitors made from silicon-germanium and electrode-limited conduction dielectric films
KR930017082A (en) Semiconductor device with bonding layer and manufacturing method thereof
KR930020690A (en) Dynamic memory cells
KR910019230A (en) Semiconductor memory device and manufacturing method
EP0337436A3 (en) Semiconductor memory device having improved dynamic memory cell structure
EP0112670A1 (en) Semiconductor memory device having stacked capacitor-tape memory cells
US6004844A (en) Unit cell layout and transfer gate design for high density DRAMs
KR930003329A (en) Semiconductor integrated circuit device and manufacturing method
US5208176A (en) Method of fabricating an enhanced dynamic random access memory (DRAM) cell capacitor using multiple polysilicon texturization
TW428312B (en) A new scheme of capacitor and bit-line at same level and its fabrication method for 8F2 DRAM cell with minimum bit-line coupling noise
EP0398569A3 (en) Dynamic random access memory device
KR940012615A (en) Semiconductor memory device and manufacturing method
HK129094A (en) Three-dimensional 1-transistor cell structure with a trench capacitor for a dynamic semiconductor memory, and method for its manufacture
EP0154871A3 (en) One-transistor dynamic random-access memory
DE59109236D1 (en) DRAM cell structure with capacitor over bit line and method for its production
US5463236A (en) Semiconductor memory device having improved isolation structure among memory cells
JP2702121B2 (en) Semiconductor storage device
US4388121A (en) Reduced field implant for dynamic memory cell array
JPS6173367A (en) Semiconductor device
KR970005726B1 (en) Semiconductor memory device and manufacturing method thereof
HK125595A (en) Memory cell design for dynamic semiconductor memories
US4173819A (en) Method of manufacturing a dynamic random access memory using MOS FETS
JPH0691216B2 (en) Semiconductor memory device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application
J2X1 Appeal (before the patent court)

Free format text: APPEAL AGAINST DECISION TO DECLINE REFUSAL

G160 Decision to publish patent application
B701 Decision to grant
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20020605

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee