IT1225612B - Processo di fabbricazione di dispositivi integrati cmos con lunghezza di gate ridotta e transistori a canale superficiale - Google Patents
Processo di fabbricazione di dispositivi integrati cmos con lunghezza di gate ridotta e transistori a canale superficialeInfo
- Publication number
- IT1225612B IT1225612B IT8883653A IT8365388A IT1225612B IT 1225612 B IT1225612 B IT 1225612B IT 8883653 A IT8883653 A IT 8883653A IT 8365388 A IT8365388 A IT 8365388A IT 1225612 B IT1225612 B IT 1225612B
- Authority
- IT
- Italy
- Prior art keywords
- manufacturing process
- gate length
- channel transistors
- cmos devices
- surface channel
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT8883653A IT1225612B (it) | 1988-07-29 | 1988-07-29 | Processo di fabbricazione di dispositivi integrati cmos con lunghezza di gate ridotta e transistori a canale superficiale |
EP19890830330 EP0362147A3 (en) | 1988-07-29 | 1989-07-17 | Fabrication of cmos integrated devices with reduced gate length |
US07/381,283 US4987088A (en) | 1988-07-29 | 1989-07-18 | Fabrication of CMOS devices with reduced gate length |
JP1196482A JPH0276255A (ja) | 1988-07-29 | 1989-07-28 | 短いゲート長さを有するcmosデバイスの製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT8883653A IT1225612B (it) | 1988-07-29 | 1988-07-29 | Processo di fabbricazione di dispositivi integrati cmos con lunghezza di gate ridotta e transistori a canale superficiale |
Publications (2)
Publication Number | Publication Date |
---|---|
IT8883653A0 IT8883653A0 (it) | 1988-07-29 |
IT1225612B true IT1225612B (it) | 1990-11-22 |
Family
ID=11323664
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT8883653A IT1225612B (it) | 1988-07-29 | 1988-07-29 | Processo di fabbricazione di dispositivi integrati cmos con lunghezza di gate ridotta e transistori a canale superficiale |
Country Status (4)
Country | Link |
---|---|
US (1) | US4987088A (it) |
EP (1) | EP0362147A3 (it) |
JP (1) | JPH0276255A (it) |
IT (1) | IT1225612B (it) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04252032A (ja) * | 1990-05-24 | 1992-09-08 | Micron Technol Inc | Nウエルスチーム酸化工程を省略し、ブランケットpウエル打ち込み工程によりシリコン基板上にnウエルおよびpウエルを形成させる方法 |
JP3879173B2 (ja) * | 1996-03-25 | 2007-02-07 | 住友電気工業株式会社 | 化合物半導体気相成長方法 |
US5939934A (en) * | 1996-12-03 | 1999-08-17 | Stmicroelectronics, Inc. | Integrated circuit passively biasing transistor effective threshold voltage and related methods |
US5883544A (en) * | 1996-12-03 | 1999-03-16 | Stmicroelectronics, Inc. | Integrated circuit actively biasing the threshold voltage of transistors and related methods |
US5834966A (en) * | 1996-12-08 | 1998-11-10 | Stmicroelectronics, Inc. | Integrated circuit sensing and digitally biasing the threshold voltage of transistors and related methods |
US5929695A (en) * | 1997-06-02 | 1999-07-27 | Stmicroelectronics, Inc. | Integrated circuit having selective bias of transistors for low voltage and low standby current and related methods |
FR2794898B1 (fr) | 1999-06-11 | 2001-09-14 | France Telecom | Dispositif semi-conducteur a tension de seuil compensee et procede de fabrication |
US10903210B2 (en) * | 2015-05-05 | 2021-01-26 | International Business Machines Corporation | Sub-fin doped bulk fin field effect transistor (FinFET), Integrated Circuit (IC) and method of manufacture |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4075754A (en) * | 1974-02-26 | 1978-02-28 | Harris Corporation | Self aligned gate for di-CMOS |
DE3133841A1 (de) * | 1981-08-27 | 1983-03-17 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen |
US4613885A (en) * | 1982-02-01 | 1986-09-23 | Texas Instruments Incorporated | High-voltage CMOS process |
US4598460A (en) * | 1984-12-10 | 1986-07-08 | Solid State Scientific, Inc. | Method of making a CMOS EPROM with independently selectable thresholds |
US4745083A (en) * | 1986-11-19 | 1988-05-17 | Sprague Electric Company | Method of making a fast IGFET |
US4839301A (en) * | 1988-12-19 | 1989-06-13 | Micron Technology, Inc. | Blanket CMOS channel stop implant employing a combination of n-channel and p-channel punch-through implants |
-
1988
- 1988-07-29 IT IT8883653A patent/IT1225612B/it active
-
1989
- 1989-07-17 EP EP19890830330 patent/EP0362147A3/en not_active Withdrawn
- 1989-07-18 US US07/381,283 patent/US4987088A/en not_active Expired - Lifetime
- 1989-07-28 JP JP1196482A patent/JPH0276255A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
EP0362147A2 (en) | 1990-04-04 |
US4987088A (en) | 1991-01-22 |
IT8883653A0 (it) | 1988-07-29 |
EP0362147A3 (en) | 1991-01-23 |
JPH0276255A (ja) | 1990-03-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
IT8883655A0 (it) | Processo per la fabbricazione di dispositivi integrati cmos con lunghezze di gate ridotte e drain leggermente drogato | |
DE68925308D1 (de) | Integrierte Grabentransistorstruktur und Herstellungsverfahren | |
EP0322665A3 (en) | Process for manufacturing cmos integrated devices with reduced gate lengths | |
BR9103259A (pt) | Substrato de titanio e seu processo de fabricacao | |
PT97381A (pt) | Processo de fabricacao de embolo e embolo | |
DE69430513D1 (de) | Harzvergossenes Halbleiterbauteil und dessen Herstellungsverfahren | |
BR8903582A (pt) | Vidraca com superficie anti-geada e seu processo de fabricacao | |
DE69220120D1 (de) | Integrierte optische Wellenleitervorrichtungen und Herstellungsverfahren | |
KR910007146A (ko) | T형의 반도체 돌출부를 가지는 mosfet와 그 제조방법 | |
IT1225612B (it) | Processo di fabbricazione di dispositivi integrati cmos con lunghezza di gate ridotta e transistori a canale superficiale | |
BR9303940A (pt) | Processo de fabricar um conjunto de correia flexivel e o respectivo conjunto | |
EP0439165A3 (en) | Field-effect transistor having a vertical structure and method of manufacturing the same | |
BR8801815A (pt) | Transistor de alto desempenho com emissor de parede lateral e processo de formacao do mesmo | |
EP0668610A3 (en) | Method for producing a field effect transistor with a Schottky gate. | |
FR2693034B1 (fr) | Transistor à couche mince et son procédé de fabrication. | |
BR9300027A (pt) | Lentes compostas e seu processo de fabricacao | |
BR8905540A (pt) | Dispositivo semicondutor que possui transistores verticais bipolares complementares e processo de fabricacao do mesmo | |
BR8402085A (pt) | Tiristor autoprotegido e processo de fabricacao | |
IT1191558B (it) | Dispositivo a semiconduttore integrato di tipo mos con spessore dell'ossido di porta non uniforme e procedimento di fabbricazione dello stesso | |
EP0416574A3 (en) | E2prom with a floating gate formed in a semiconductor substrate and method of fabricating the same | |
IT1244239B (it) | Terminazione dello stadio di potenza di un dispositivo monolitico a semicondutture e relativo processo di fabbricazione | |
IT8521201A0 (it) | Transistore mos a canale n con limitazione dell'effetto di perforazione (punch-through) erelativo processo di formazione. | |
DE69416734T2 (de) | Logikgatter bestehend aus Halbleitertransistoren | |
EP0311109A3 (en) | Method of manufacturing a field-effect transistor having a junction gate | |
BR8207853A (pt) | Substrato litografico e seu processo de fabricacao |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970730 |