IT1198108B - Cella di memori aeeprom a due livelli di polisilicio con zona di ossiso di tunnel - Google Patents
Cella di memori aeeprom a due livelli di polisilicio con zona di ossiso di tunnelInfo
- Publication number
- IT1198108B IT1198108B IT22372/86A IT2237286A IT1198108B IT 1198108 B IT1198108 B IT 1198108B IT 22372/86 A IT22372/86 A IT 22372/86A IT 2237286 A IT2237286 A IT 2237286A IT 1198108 B IT1198108 B IT 1198108B
- Authority
- IT
- Italy
- Prior art keywords
- polysilicio
- aisprom
- oxyde
- tunnel
- level
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT22372/86A IT1198108B (it) | 1986-11-18 | 1986-11-18 | Cella di memori aeeprom a due livelli di polisilicio con zona di ossiso di tunnel |
EP87202038A EP0271932A3 (en) | 1986-11-18 | 1987-10-23 | Eeprom memory cell with two levels of polysilicon and a tunnel oxide zone |
JP62288599A JPS63136572A (ja) | 1986-11-18 | 1987-11-17 | 2層のポリシリコン層とトンネル酸化区域を有するeepromメモリセル |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT22372/86A IT1198108B (it) | 1986-11-18 | 1986-11-18 | Cella di memori aeeprom a due livelli di polisilicio con zona di ossiso di tunnel |
Publications (2)
Publication Number | Publication Date |
---|---|
IT8622372A0 IT8622372A0 (it) | 1986-11-18 |
IT1198108B true IT1198108B (it) | 1988-12-21 |
Family
ID=11195368
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT22372/86A IT1198108B (it) | 1986-11-18 | 1986-11-18 | Cella di memori aeeprom a due livelli di polisilicio con zona di ossiso di tunnel |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0271932A3 (it) |
JP (1) | JPS63136572A (it) |
IT (1) | IT1198108B (it) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5060034A (en) * | 1988-11-01 | 1991-10-22 | Casio Computer Co., Ltd. | Memory device using thin film transistors having an insulation film with si/n composition ratio of 0.85 to 1.1 |
US7800156B2 (en) | 2008-02-25 | 2010-09-21 | Tower Semiconductor Ltd. | Asymmetric single poly NMOS non-volatile memory cell |
US8344440B2 (en) | 2008-02-25 | 2013-01-01 | Tower Semiconductor Ltd. | Three-terminal single poly NMOS non-volatile memory cell with shorter program/erase times |
US7859043B2 (en) | 2008-02-25 | 2010-12-28 | Tower Semiconductor Ltd. | Three-terminal single poly NMOS non-volatile memory cell |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5292441A (en) * | 1976-01-30 | 1977-08-03 | Toshiba Corp | Semiconductor memory unit |
DE2743422A1 (de) * | 1977-09-27 | 1979-03-29 | Siemens Ag | Wortweise loeschbarer, nicht fluechtiger speicher in floating-gate-technik |
US4479203A (en) * | 1981-11-16 | 1984-10-23 | Motorola, Inc. | Electrically erasable programmable read only memory cell |
JPS59121880A (ja) * | 1982-12-28 | 1984-07-14 | Toshiba Corp | 不揮発性半導体記憶装置 |
-
1986
- 1986-11-18 IT IT22372/86A patent/IT1198108B/it active
-
1987
- 1987-10-23 EP EP87202038A patent/EP0271932A3/en not_active Withdrawn
- 1987-11-17 JP JP62288599A patent/JPS63136572A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
EP0271932A3 (en) | 1988-12-07 |
JPS63136572A (ja) | 1988-06-08 |
EP0271932A2 (en) | 1988-06-22 |
IT8622372A0 (it) | 1986-11-18 |
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